Commit | Line | Data |
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4bbbc1ad JY |
1 | /* |
2 | * GPMC support functions | |
3 | * | |
4 | * Copyright (C) 2005-2006 Nokia Corporation | |
5 | * | |
6 | * Author: Juha Yrjola | |
7 | * | |
44169075 SS |
8 | * Copyright (C) 2009 Texas Instruments |
9 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
10 | * | |
4bbbc1ad JY |
11 | * This program is free software; you can redistribute it and/or modify |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
fd1dc87d PW |
15 | #undef DEBUG |
16 | ||
db97eb7d | 17 | #include <linux/irq.h> |
4bbbc1ad JY |
18 | #include <linux/kernel.h> |
19 | #include <linux/init.h> | |
20 | #include <linux/err.h> | |
21 | #include <linux/clk.h> | |
f37e4580 ID |
22 | #include <linux/ioport.h> |
23 | #include <linux/spinlock.h> | |
fced80c7 | 24 | #include <linux/io.h> |
fd1dc87d | 25 | #include <linux/module.h> |
db97eb7d | 26 | #include <linux/interrupt.h> |
da496873 | 27 | #include <linux/platform_device.h> |
bc6b1e7b DM |
28 | #include <linux/of.h> |
29 | #include <linux/of_mtd.h> | |
30 | #include <linux/of_device.h> | |
31 | #include <linux/mtd/nand.h> | |
4bbbc1ad | 32 | |
bc3668ea | 33 | #include <linux/platform_data/mtd-nand-omap2.h> |
4bbbc1ad | 34 | |
7f245162 | 35 | #include <asm/mach-types.h> |
72d0f1c3 | 36 | |
dbc04161 | 37 | #include "soc.h" |
7d7e1eba | 38 | #include "common.h" |
25c7d49e | 39 | #include "omap_device.h" |
3ef5d007 | 40 | #include "gpmc.h" |
bc6b1e7b | 41 | #include "gpmc-nand.h" |
75d3625e | 42 | #include "gpmc-onenand.h" |
7d7e1eba | 43 | |
4be48fd5 AM |
44 | #define DEVICE_NAME "omap-gpmc" |
45 | ||
fd1dc87d | 46 | /* GPMC register offsets */ |
4bbbc1ad JY |
47 | #define GPMC_REVISION 0x00 |
48 | #define GPMC_SYSCONFIG 0x10 | |
49 | #define GPMC_SYSSTATUS 0x14 | |
50 | #define GPMC_IRQSTATUS 0x18 | |
51 | #define GPMC_IRQENABLE 0x1c | |
52 | #define GPMC_TIMEOUT_CONTROL 0x40 | |
53 | #define GPMC_ERR_ADDRESS 0x44 | |
54 | #define GPMC_ERR_TYPE 0x48 | |
55 | #define GPMC_CONFIG 0x50 | |
56 | #define GPMC_STATUS 0x54 | |
57 | #define GPMC_PREFETCH_CONFIG1 0x1e0 | |
58 | #define GPMC_PREFETCH_CONFIG2 0x1e4 | |
15e02a3b | 59 | #define GPMC_PREFETCH_CONTROL 0x1ec |
4bbbc1ad JY |
60 | #define GPMC_PREFETCH_STATUS 0x1f0 |
61 | #define GPMC_ECC_CONFIG 0x1f4 | |
62 | #define GPMC_ECC_CONTROL 0x1f8 | |
63 | #define GPMC_ECC_SIZE_CONFIG 0x1fc | |
948d38e7 | 64 | #define GPMC_ECC1_RESULT 0x200 |
8d602cf5 | 65 | #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */ |
2fdf0c98 AM |
66 | #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */ |
67 | #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */ | |
68 | #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */ | |
4bbbc1ad | 69 | |
2c65e744 YY |
70 | /* GPMC ECC control settings */ |
71 | #define GPMC_ECC_CTRL_ECCCLEAR 0x100 | |
72 | #define GPMC_ECC_CTRL_ECCDISABLE 0x000 | |
73 | #define GPMC_ECC_CTRL_ECCREG1 0x001 | |
74 | #define GPMC_ECC_CTRL_ECCREG2 0x002 | |
75 | #define GPMC_ECC_CTRL_ECCREG3 0x003 | |
76 | #define GPMC_ECC_CTRL_ECCREG4 0x004 | |
77 | #define GPMC_ECC_CTRL_ECCREG5 0x005 | |
78 | #define GPMC_ECC_CTRL_ECCREG6 0x006 | |
79 | #define GPMC_ECC_CTRL_ECCREG7 0x007 | |
80 | #define GPMC_ECC_CTRL_ECCREG8 0x008 | |
81 | #define GPMC_ECC_CTRL_ECCREG9 0x009 | |
82 | ||
559d94b0 AM |
83 | #define GPMC_CONFIG2_CSEXTRADELAY BIT(7) |
84 | #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) | |
85 | #define GPMC_CONFIG4_OEEXTRADELAY BIT(7) | |
86 | #define GPMC_CONFIG4_WEEXTRADELAY BIT(23) | |
87 | #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6) | |
88 | #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7) | |
89 | ||
948d38e7 | 90 | #define GPMC_CS0_OFFSET 0x60 |
4bbbc1ad | 91 | #define GPMC_CS_SIZE 0x30 |
2fdf0c98 | 92 | #define GPMC_BCH_SIZE 0x10 |
4bbbc1ad | 93 | |
f37e4580 ID |
94 | #define GPMC_MEM_START 0x00000000 |
95 | #define GPMC_MEM_END 0x3FFFFFFF | |
96 | #define BOOT_ROM_SPACE 0x100000 /* 1MB */ | |
97 | ||
98 | #define GPMC_CHUNK_SHIFT 24 /* 16 MB */ | |
99 | #define GPMC_SECTION_SHIFT 28 /* 128 MB */ | |
100 | ||
59e9c5ae | 101 | #define CS_NUM_SHIFT 24 |
102 | #define ENABLE_PREFETCH (0x1 << 7) | |
103 | #define DMA_MPU_MODE 2 | |
104 | ||
da496873 AM |
105 | #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf) |
106 | #define GPMC_REVISION_MINOR(l) (l & 0xf) | |
107 | ||
108 | #define GPMC_HAS_WR_ACCESS 0x1 | |
109 | #define GPMC_HAS_WR_DATA_MUX_BUS 0x2 | |
110 | ||
6b6c32fc AM |
111 | /* XXX: Only NAND irq has been considered,currently these are the only ones used |
112 | */ | |
113 | #define GPMC_NR_IRQ 2 | |
114 | ||
115 | struct gpmc_client_irq { | |
116 | unsigned irq; | |
117 | u32 bitmask; | |
118 | }; | |
119 | ||
a2d3e7ba RN |
120 | /* Structure to save gpmc cs context */ |
121 | struct gpmc_cs_config { | |
122 | u32 config1; | |
123 | u32 config2; | |
124 | u32 config3; | |
125 | u32 config4; | |
126 | u32 config5; | |
127 | u32 config6; | |
128 | u32 config7; | |
129 | int is_valid; | |
130 | }; | |
131 | ||
132 | /* | |
133 | * Structure to save/restore gpmc context | |
134 | * to support core off on OMAP3 | |
135 | */ | |
136 | struct omap3_gpmc_regs { | |
137 | u32 sysconfig; | |
138 | u32 irqenable; | |
139 | u32 timeout_ctrl; | |
140 | u32 config; | |
141 | u32 prefetch_config1; | |
142 | u32 prefetch_config2; | |
143 | u32 prefetch_control; | |
144 | struct gpmc_cs_config cs_context[GPMC_CS_NUM]; | |
145 | }; | |
146 | ||
6b6c32fc AM |
147 | static struct gpmc_client_irq gpmc_client_irq[GPMC_NR_IRQ]; |
148 | static struct irq_chip gpmc_irq_chip; | |
149 | static unsigned gpmc_irq_start; | |
150 | ||
f37e4580 ID |
151 | static struct resource gpmc_mem_root; |
152 | static struct resource gpmc_cs_mem[GPMC_CS_NUM]; | |
87b247c4 | 153 | static DEFINE_SPINLOCK(gpmc_mem_lock); |
6797b4fe JH |
154 | /* Define chip-selects as reserved by default until probe completes */ |
155 | static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1); | |
da496873 AM |
156 | static struct device *gpmc_dev; |
157 | static int gpmc_irq; | |
158 | static resource_size_t phys_base, mem_size; | |
159 | static unsigned gpmc_capability; | |
fd1dc87d | 160 | static void __iomem *gpmc_base; |
4bbbc1ad | 161 | |
fd1dc87d | 162 | static struct clk *gpmc_l3_clk; |
4bbbc1ad | 163 | |
db97eb7d SG |
164 | static irqreturn_t gpmc_handle_irq(int irq, void *dev); |
165 | ||
4bbbc1ad JY |
166 | static void gpmc_write_reg(int idx, u32 val) |
167 | { | |
168 | __raw_writel(val, gpmc_base + idx); | |
169 | } | |
170 | ||
171 | static u32 gpmc_read_reg(int idx) | |
172 | { | |
173 | return __raw_readl(gpmc_base + idx); | |
174 | } | |
175 | ||
176 | void gpmc_cs_write_reg(int cs, int idx, u32 val) | |
177 | { | |
178 | void __iomem *reg_addr; | |
179 | ||
948d38e7 | 180 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
4bbbc1ad JY |
181 | __raw_writel(val, reg_addr); |
182 | } | |
183 | ||
3fc089e7 | 184 | static u32 gpmc_cs_read_reg(int cs, int idx) |
4bbbc1ad | 185 | { |
fd1dc87d PW |
186 | void __iomem *reg_addr; |
187 | ||
948d38e7 | 188 | reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx; |
fd1dc87d | 189 | return __raw_readl(reg_addr); |
4bbbc1ad JY |
190 | } |
191 | ||
fd1dc87d | 192 | /* TODO: Add support for gpmc_fck to clock framework and use it */ |
3fc089e7 | 193 | static unsigned long gpmc_get_fclk_period(void) |
4bbbc1ad | 194 | { |
fd1dc87d PW |
195 | unsigned long rate = clk_get_rate(gpmc_l3_clk); |
196 | ||
197 | if (rate == 0) { | |
198 | printk(KERN_WARNING "gpmc_l3_clk not enabled\n"); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | rate /= 1000; | |
203 | rate = 1000000000 / rate; /* In picoseconds */ | |
204 | ||
205 | return rate; | |
4bbbc1ad JY |
206 | } |
207 | ||
3fc089e7 | 208 | static unsigned int gpmc_ns_to_ticks(unsigned int time_ns) |
4bbbc1ad JY |
209 | { |
210 | unsigned long tick_ps; | |
211 | ||
212 | /* Calculate in picosecs to yield more exact results */ | |
213 | tick_ps = gpmc_get_fclk_period(); | |
214 | ||
215 | return (time_ns * 1000 + tick_ps - 1) / tick_ps; | |
216 | } | |
217 | ||
3fc089e7 | 218 | static unsigned int gpmc_ps_to_ticks(unsigned int time_ps) |
a3551f5b AH |
219 | { |
220 | unsigned long tick_ps; | |
221 | ||
222 | /* Calculate in picosecs to yield more exact results */ | |
223 | tick_ps = gpmc_get_fclk_period(); | |
224 | ||
225 | return (time_ps + tick_ps - 1) / tick_ps; | |
226 | } | |
227 | ||
fd1dc87d PW |
228 | unsigned int gpmc_ticks_to_ns(unsigned int ticks) |
229 | { | |
230 | return ticks * gpmc_get_fclk_period() / 1000; | |
231 | } | |
232 | ||
3fc089e7 | 233 | static unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns) |
23300597 KS |
234 | { |
235 | unsigned long ticks = gpmc_ns_to_ticks(time_ns); | |
236 | ||
237 | return ticks * gpmc_get_fclk_period() / 1000; | |
238 | } | |
239 | ||
246da26d AM |
240 | static unsigned int gpmc_ticks_to_ps(unsigned int ticks) |
241 | { | |
242 | return ticks * gpmc_get_fclk_period(); | |
243 | } | |
244 | ||
245 | static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps) | |
246 | { | |
247 | unsigned long ticks = gpmc_ps_to_ticks(time_ps); | |
248 | ||
249 | return ticks * gpmc_get_fclk_period(); | |
250 | } | |
251 | ||
559d94b0 AM |
252 | static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value) |
253 | { | |
254 | u32 l; | |
255 | ||
256 | l = gpmc_cs_read_reg(cs, reg); | |
257 | if (value) | |
258 | l |= mask; | |
259 | else | |
260 | l &= ~mask; | |
261 | gpmc_cs_write_reg(cs, reg, l); | |
262 | } | |
263 | ||
264 | static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p) | |
265 | { | |
266 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1, | |
267 | GPMC_CONFIG1_TIME_PARA_GRAN, | |
268 | p->time_para_granularity); | |
269 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2, | |
270 | GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay); | |
271 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3, | |
272 | GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay); | |
273 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
274 | GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay); | |
275 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4, | |
276 | GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay); | |
277 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
278 | GPMC_CONFIG6_CYCLE2CYCLESAMECSEN, | |
279 | p->cycle2cyclesamecsen); | |
280 | gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6, | |
281 | GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN, | |
282 | p->cycle2cyclediffcsen); | |
283 | } | |
284 | ||
4bbbc1ad JY |
285 | #ifdef DEBUG |
286 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
2aab6468 | 287 | int time, const char *name) |
4bbbc1ad JY |
288 | #else |
289 | static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, | |
290 | int time) | |
291 | #endif | |
292 | { | |
293 | u32 l; | |
294 | int ticks, mask, nr_bits; | |
295 | ||
296 | if (time == 0) | |
297 | ticks = 0; | |
298 | else | |
299 | ticks = gpmc_ns_to_ticks(time); | |
300 | nr_bits = end_bit - st_bit + 1; | |
1c22cc13 DB |
301 | if (ticks >= 1 << nr_bits) { |
302 | #ifdef DEBUG | |
303 | printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", | |
304 | cs, name, time, ticks, 1 << nr_bits); | |
305 | #endif | |
4bbbc1ad | 306 | return -1; |
1c22cc13 | 307 | } |
4bbbc1ad JY |
308 | |
309 | mask = (1 << nr_bits) - 1; | |
310 | l = gpmc_cs_read_reg(cs, reg); | |
311 | #ifdef DEBUG | |
1c22cc13 DB |
312 | printk(KERN_INFO |
313 | "GPMC CS%d: %-10s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", | |
2aab6468 | 314 | cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000, |
1c22cc13 | 315 | (l >> st_bit) & mask, time); |
4bbbc1ad JY |
316 | #endif |
317 | l &= ~(mask << st_bit); | |
318 | l |= ticks << st_bit; | |
319 | gpmc_cs_write_reg(cs, reg, l); | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | #ifdef DEBUG | |
325 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
326 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ | |
327 | t->field, #field) < 0) \ | |
328 | return -1 | |
329 | #else | |
330 | #define GPMC_SET_ONE(reg, st, end, field) \ | |
331 | if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \ | |
332 | return -1 | |
333 | #endif | |
334 | ||
1b47ca1a | 335 | int gpmc_calc_divider(unsigned int sync_clk) |
4bbbc1ad JY |
336 | { |
337 | int div; | |
338 | u32 l; | |
339 | ||
a3551f5b | 340 | l = sync_clk + (gpmc_get_fclk_period() - 1); |
4bbbc1ad JY |
341 | div = l / gpmc_get_fclk_period(); |
342 | if (div > 4) | |
343 | return -1; | |
1c22cc13 | 344 | if (div <= 0) |
4bbbc1ad JY |
345 | div = 1; |
346 | ||
347 | return div; | |
348 | } | |
349 | ||
350 | int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t) | |
351 | { | |
352 | int div; | |
353 | u32 l; | |
354 | ||
1b47ca1a | 355 | div = gpmc_calc_divider(t->sync_clk); |
4bbbc1ad | 356 | if (div < 0) |
a032d33b | 357 | return div; |
4bbbc1ad JY |
358 | |
359 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on); | |
360 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off); | |
361 | GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off); | |
362 | ||
363 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on); | |
364 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off); | |
365 | GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off); | |
366 | ||
367 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on); | |
368 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off); | |
369 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on); | |
370 | GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off); | |
371 | ||
372 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle); | |
373 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle); | |
374 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access); | |
375 | ||
376 | GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access); | |
377 | ||
559d94b0 AM |
378 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround); |
379 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay); | |
380 | ||
381 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 18, 19, wait_monitoring); | |
382 | GPMC_SET_ONE(GPMC_CS_CONFIG1, 25, 26, clk_activation); | |
383 | ||
da496873 | 384 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) |
cc26b3b0 | 385 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus); |
da496873 | 386 | if (gpmc_capability & GPMC_HAS_WR_ACCESS) |
cc26b3b0 | 387 | GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access); |
cc26b3b0 | 388 | |
1c22cc13 DB |
389 | /* caller is expected to have initialized CONFIG1 to cover |
390 | * at least sync vs async | |
391 | */ | |
392 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
393 | if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) { | |
4bbbc1ad | 394 | #ifdef DEBUG |
1c22cc13 DB |
395 | printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n", |
396 | cs, (div * gpmc_get_fclk_period()) / 1000, div); | |
4bbbc1ad | 397 | #endif |
1c22cc13 DB |
398 | l &= ~0x03; |
399 | l |= (div - 1); | |
400 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l); | |
401 | } | |
4bbbc1ad | 402 | |
559d94b0 AM |
403 | gpmc_cs_bool_timings(cs, &t->bool_timings); |
404 | ||
4bbbc1ad JY |
405 | return 0; |
406 | } | |
407 | ||
f37e4580 ID |
408 | static void gpmc_cs_enable_mem(int cs, u32 base, u32 size) |
409 | { | |
410 | u32 l; | |
411 | u32 mask; | |
412 | ||
413 | mask = (1 << GPMC_SECTION_SHIFT) - size; | |
414 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
415 | l &= ~0x3f; | |
416 | l = (base >> GPMC_CHUNK_SHIFT) & 0x3f; | |
417 | l &= ~(0x0f << 8); | |
418 | l |= ((mask >> GPMC_CHUNK_SHIFT) & 0x0f) << 8; | |
a2d3e7ba | 419 | l |= GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
420 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
421 | } | |
422 | ||
423 | static void gpmc_cs_disable_mem(int cs) | |
424 | { | |
425 | u32 l; | |
426 | ||
427 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 428 | l &= ~GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
429 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l); |
430 | } | |
431 | ||
432 | static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size) | |
433 | { | |
434 | u32 l; | |
435 | u32 mask; | |
436 | ||
437 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
438 | *base = (l & 0x3f) << GPMC_CHUNK_SHIFT; | |
439 | mask = (l >> 8) & 0x0f; | |
440 | *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT); | |
441 | } | |
442 | ||
443 | static int gpmc_cs_mem_enabled(int cs) | |
444 | { | |
445 | u32 l; | |
446 | ||
447 | l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7); | |
a2d3e7ba | 448 | return l & GPMC_CONFIG7_CSVALID; |
f37e4580 ID |
449 | } |
450 | ||
3fc089e7 | 451 | static int gpmc_cs_set_reserved(int cs, int reserved) |
4bbbc1ad | 452 | { |
c40fae95 TL |
453 | if (cs > GPMC_CS_NUM) |
454 | return -ENODEV; | |
455 | ||
f37e4580 ID |
456 | gpmc_cs_map &= ~(1 << cs); |
457 | gpmc_cs_map |= (reserved ? 1 : 0) << cs; | |
c40fae95 TL |
458 | |
459 | return 0; | |
f37e4580 ID |
460 | } |
461 | ||
3fc089e7 | 462 | static int gpmc_cs_reserved(int cs) |
f37e4580 | 463 | { |
c40fae95 TL |
464 | if (cs > GPMC_CS_NUM) |
465 | return -ENODEV; | |
466 | ||
f37e4580 ID |
467 | return gpmc_cs_map & (1 << cs); |
468 | } | |
469 | ||
470 | static unsigned long gpmc_mem_align(unsigned long size) | |
471 | { | |
472 | int order; | |
473 | ||
474 | size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1); | |
475 | order = GPMC_CHUNK_SHIFT - 1; | |
476 | do { | |
477 | size >>= 1; | |
478 | order++; | |
479 | } while (size); | |
480 | size = 1 << order; | |
481 | return size; | |
482 | } | |
483 | ||
484 | static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) | |
485 | { | |
486 | struct resource *res = &gpmc_cs_mem[cs]; | |
487 | int r; | |
488 | ||
489 | size = gpmc_mem_align(size); | |
490 | spin_lock(&gpmc_mem_lock); | |
491 | res->start = base; | |
492 | res->end = base + size - 1; | |
493 | r = request_resource(&gpmc_mem_root, res); | |
494 | spin_unlock(&gpmc_mem_lock); | |
495 | ||
496 | return r; | |
497 | } | |
498 | ||
da496873 AM |
499 | static int gpmc_cs_delete_mem(int cs) |
500 | { | |
501 | struct resource *res = &gpmc_cs_mem[cs]; | |
502 | int r; | |
503 | ||
504 | spin_lock(&gpmc_mem_lock); | |
505 | r = release_resource(&gpmc_cs_mem[cs]); | |
506 | res->start = 0; | |
507 | res->end = 0; | |
508 | spin_unlock(&gpmc_mem_lock); | |
509 | ||
510 | return r; | |
511 | } | |
512 | ||
f37e4580 ID |
513 | int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) |
514 | { | |
515 | struct resource *res = &gpmc_cs_mem[cs]; | |
516 | int r = -1; | |
517 | ||
518 | if (cs > GPMC_CS_NUM) | |
519 | return -ENODEV; | |
520 | ||
521 | size = gpmc_mem_align(size); | |
522 | if (size > (1 << GPMC_SECTION_SHIFT)) | |
523 | return -ENOMEM; | |
524 | ||
525 | spin_lock(&gpmc_mem_lock); | |
526 | if (gpmc_cs_reserved(cs)) { | |
527 | r = -EBUSY; | |
528 | goto out; | |
529 | } | |
530 | if (gpmc_cs_mem_enabled(cs)) | |
531 | r = adjust_resource(res, res->start & ~(size - 1), size); | |
532 | if (r < 0) | |
533 | r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0, | |
534 | size, NULL, NULL); | |
535 | if (r < 0) | |
536 | goto out; | |
537 | ||
6d135242 | 538 | gpmc_cs_enable_mem(cs, res->start, resource_size(res)); |
f37e4580 ID |
539 | *base = res->start; |
540 | gpmc_cs_set_reserved(cs, 1); | |
541 | out: | |
542 | spin_unlock(&gpmc_mem_lock); | |
543 | return r; | |
544 | } | |
fd1dc87d | 545 | EXPORT_SYMBOL(gpmc_cs_request); |
f37e4580 ID |
546 | |
547 | void gpmc_cs_free(int cs) | |
548 | { | |
549 | spin_lock(&gpmc_mem_lock); | |
e7fdc605 | 550 | if (cs >= GPMC_CS_NUM || cs < 0 || !gpmc_cs_reserved(cs)) { |
f37e4580 ID |
551 | printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); |
552 | BUG(); | |
553 | spin_unlock(&gpmc_mem_lock); | |
554 | return; | |
555 | } | |
556 | gpmc_cs_disable_mem(cs); | |
557 | release_resource(&gpmc_cs_mem[cs]); | |
558 | gpmc_cs_set_reserved(cs, 0); | |
559 | spin_unlock(&gpmc_mem_lock); | |
560 | } | |
fd1dc87d | 561 | EXPORT_SYMBOL(gpmc_cs_free); |
f37e4580 | 562 | |
948d38e7 SG |
563 | /** |
564 | * gpmc_cs_configure - write request to configure gpmc | |
565 | * @cs: chip select number | |
566 | * @cmd: command type | |
567 | * @wval: value to write | |
568 | * @return status of the operation | |
569 | */ | |
570 | int gpmc_cs_configure(int cs, int cmd, int wval) | |
571 | { | |
572 | int err = 0; | |
573 | u32 regval = 0; | |
574 | ||
575 | switch (cmd) { | |
db97eb7d SG |
576 | case GPMC_ENABLE_IRQ: |
577 | gpmc_write_reg(GPMC_IRQENABLE, wval); | |
578 | break; | |
579 | ||
948d38e7 SG |
580 | case GPMC_SET_IRQ_STATUS: |
581 | gpmc_write_reg(GPMC_IRQSTATUS, wval); | |
582 | break; | |
583 | ||
584 | case GPMC_CONFIG_WP: | |
585 | regval = gpmc_read_reg(GPMC_CONFIG); | |
586 | if (wval) | |
587 | regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */ | |
588 | else | |
589 | regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */ | |
590 | gpmc_write_reg(GPMC_CONFIG, regval); | |
591 | break; | |
592 | ||
593 | case GPMC_CONFIG_RDY_BSY: | |
594 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
595 | if (wval) | |
596 | regval |= WR_RD_PIN_MONITORING; | |
597 | else | |
598 | regval &= ~WR_RD_PIN_MONITORING; | |
599 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
600 | break; | |
601 | ||
602 | case GPMC_CONFIG_DEV_SIZE: | |
603 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
8ef5d844 YY |
604 | |
605 | /* clear 2 target bits */ | |
606 | regval &= ~GPMC_CONFIG1_DEVICESIZE(3); | |
607 | ||
608 | /* set the proper value */ | |
948d38e7 | 609 | regval |= GPMC_CONFIG1_DEVICESIZE(wval); |
8ef5d844 | 610 | |
948d38e7 SG |
611 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); |
612 | break; | |
613 | ||
614 | case GPMC_CONFIG_DEV_TYPE: | |
615 | regval = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1); | |
c9fb8094 MJ |
616 | /* clear 4 target bits */ |
617 | regval &= ~(GPMC_CONFIG1_DEVICETYPE(3) | | |
618 | GPMC_CONFIG1_MUXTYPE(3)); | |
619 | /* set the proper value */ | |
948d38e7 SG |
620 | regval |= GPMC_CONFIG1_DEVICETYPE(wval); |
621 | if (wval == GPMC_DEVICETYPE_NOR) | |
622 | regval |= GPMC_CONFIG1_MUXADDDATA; | |
623 | gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, regval); | |
624 | break; | |
625 | ||
626 | default: | |
627 | printk(KERN_ERR "gpmc_configure_cs: Not supported\n"); | |
628 | err = -EINVAL; | |
629 | } | |
630 | ||
631 | return err; | |
632 | } | |
633 | EXPORT_SYMBOL(gpmc_cs_configure); | |
634 | ||
52bd138d AM |
635 | void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs) |
636 | { | |
2fdf0c98 AM |
637 | int i; |
638 | ||
52bd138d AM |
639 | reg->gpmc_status = gpmc_base + GPMC_STATUS; |
640 | reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET + | |
641 | GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs; | |
642 | reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET + | |
643 | GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs; | |
644 | reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET + | |
645 | GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs; | |
646 | reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1; | |
647 | reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2; | |
648 | reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL; | |
649 | reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS; | |
650 | reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG; | |
651 | reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL; | |
652 | reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG; | |
653 | reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT; | |
2fdf0c98 AM |
654 | |
655 | for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) { | |
656 | reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 + | |
657 | GPMC_BCH_SIZE * i; | |
658 | reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 + | |
659 | GPMC_BCH_SIZE * i; | |
660 | reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 + | |
661 | GPMC_BCH_SIZE * i; | |
662 | reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 + | |
663 | GPMC_BCH_SIZE * i; | |
664 | } | |
52bd138d AM |
665 | } |
666 | ||
6b6c32fc AM |
667 | int gpmc_get_client_irq(unsigned irq_config) |
668 | { | |
669 | int i; | |
670 | ||
671 | if (hweight32(irq_config) > 1) | |
672 | return 0; | |
673 | ||
674 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
675 | if (gpmc_client_irq[i].bitmask & irq_config) | |
676 | return gpmc_client_irq[i].irq; | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | static int gpmc_irq_endis(unsigned irq, bool endis) | |
682 | { | |
683 | int i; | |
684 | u32 regval; | |
685 | ||
686 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
687 | if (irq == gpmc_client_irq[i].irq) { | |
688 | regval = gpmc_read_reg(GPMC_IRQENABLE); | |
689 | if (endis) | |
690 | regval |= gpmc_client_irq[i].bitmask; | |
691 | else | |
692 | regval &= ~gpmc_client_irq[i].bitmask; | |
693 | gpmc_write_reg(GPMC_IRQENABLE, regval); | |
694 | break; | |
695 | } | |
696 | ||
697 | return 0; | |
698 | } | |
699 | ||
700 | static void gpmc_irq_disable(struct irq_data *p) | |
701 | { | |
702 | gpmc_irq_endis(p->irq, false); | |
703 | } | |
704 | ||
705 | static void gpmc_irq_enable(struct irq_data *p) | |
706 | { | |
707 | gpmc_irq_endis(p->irq, true); | |
708 | } | |
709 | ||
710 | static void gpmc_irq_noop(struct irq_data *data) { } | |
711 | ||
712 | static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; } | |
713 | ||
da496873 | 714 | static int gpmc_setup_irq(void) |
6b6c32fc AM |
715 | { |
716 | int i; | |
717 | u32 regval; | |
718 | ||
719 | if (!gpmc_irq) | |
720 | return -EINVAL; | |
721 | ||
722 | gpmc_irq_start = irq_alloc_descs(-1, 0, GPMC_NR_IRQ, 0); | |
71856843 | 723 | if (gpmc_irq_start < 0) { |
6b6c32fc AM |
724 | pr_err("irq_alloc_descs failed\n"); |
725 | return gpmc_irq_start; | |
726 | } | |
727 | ||
728 | gpmc_irq_chip.name = "gpmc"; | |
729 | gpmc_irq_chip.irq_startup = gpmc_irq_noop_ret; | |
730 | gpmc_irq_chip.irq_enable = gpmc_irq_enable; | |
731 | gpmc_irq_chip.irq_disable = gpmc_irq_disable; | |
732 | gpmc_irq_chip.irq_shutdown = gpmc_irq_noop; | |
733 | gpmc_irq_chip.irq_ack = gpmc_irq_noop; | |
734 | gpmc_irq_chip.irq_mask = gpmc_irq_noop; | |
735 | gpmc_irq_chip.irq_unmask = gpmc_irq_noop; | |
736 | ||
737 | gpmc_client_irq[0].bitmask = GPMC_IRQ_FIFOEVENTENABLE; | |
738 | gpmc_client_irq[1].bitmask = GPMC_IRQ_COUNT_EVENT; | |
739 | ||
740 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
741 | gpmc_client_irq[i].irq = gpmc_irq_start + i; | |
742 | irq_set_chip_and_handler(gpmc_client_irq[i].irq, | |
743 | &gpmc_irq_chip, handle_simple_irq); | |
744 | set_irq_flags(gpmc_client_irq[i].irq, | |
745 | IRQF_VALID | IRQF_NOAUTOEN); | |
746 | } | |
747 | ||
748 | /* Disable interrupts */ | |
749 | gpmc_write_reg(GPMC_IRQENABLE, 0); | |
750 | ||
751 | /* clear interrupts */ | |
752 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
753 | gpmc_write_reg(GPMC_IRQSTATUS, regval); | |
754 | ||
755 | return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL); | |
756 | } | |
757 | ||
351a102d | 758 | static int gpmc_free_irq(void) |
da496873 AM |
759 | { |
760 | int i; | |
761 | ||
762 | if (gpmc_irq) | |
763 | free_irq(gpmc_irq, NULL); | |
764 | ||
765 | for (i = 0; i < GPMC_NR_IRQ; i++) { | |
766 | irq_set_handler(gpmc_client_irq[i].irq, NULL); | |
767 | irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip); | |
768 | irq_modify_status(gpmc_client_irq[i].irq, 0, 0); | |
769 | } | |
770 | ||
771 | irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ); | |
772 | ||
773 | return 0; | |
774 | } | |
775 | ||
351a102d | 776 | static void gpmc_mem_exit(void) |
da496873 AM |
777 | { |
778 | int cs; | |
779 | ||
780 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
781 | if (!gpmc_cs_mem_enabled(cs)) | |
782 | continue; | |
783 | gpmc_cs_delete_mem(cs); | |
784 | } | |
785 | ||
786 | } | |
787 | ||
351a102d | 788 | static int gpmc_mem_init(void) |
f37e4580 | 789 | { |
8119024e | 790 | int cs, rc; |
f37e4580 ID |
791 | unsigned long boot_rom_space = 0; |
792 | ||
7f245162 KP |
793 | /* never allocate the first page, to facilitate bug detection; |
794 | * even if we didn't boot from ROM. | |
795 | */ | |
796 | boot_rom_space = BOOT_ROM_SPACE; | |
f37e4580 ID |
797 | gpmc_mem_root.start = GPMC_MEM_START + boot_rom_space; |
798 | gpmc_mem_root.end = GPMC_MEM_END; | |
799 | ||
800 | /* Reserve all regions that has been set up by bootloader */ | |
801 | for (cs = 0; cs < GPMC_CS_NUM; cs++) { | |
802 | u32 base, size; | |
803 | ||
804 | if (!gpmc_cs_mem_enabled(cs)) | |
805 | continue; | |
806 | gpmc_cs_get_memconf(cs, &base, &size); | |
8119024e | 807 | rc = gpmc_cs_insert_mem(cs, base, size); |
71856843 | 808 | if (rc < 0) { |
8119024e JH |
809 | while (--cs >= 0) |
810 | if (gpmc_cs_mem_enabled(cs)) | |
811 | gpmc_cs_delete_mem(cs); | |
812 | return rc; | |
813 | } | |
f37e4580 | 814 | } |
8119024e JH |
815 | |
816 | return 0; | |
4bbbc1ad JY |
817 | } |
818 | ||
246da26d AM |
819 | static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk) |
820 | { | |
821 | u32 temp; | |
822 | int div; | |
823 | ||
824 | div = gpmc_calc_divider(sync_clk); | |
825 | temp = gpmc_ps_to_ticks(time_ps); | |
826 | temp = (temp + div - 1) / div; | |
827 | return gpmc_ticks_to_ps(temp * div); | |
828 | } | |
829 | ||
830 | /* XXX: can the cycles be avoided ? */ | |
831 | static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t, | |
832 | struct gpmc_device_timings *dev_t) | |
833 | { | |
834 | bool mux = dev_t->mux; | |
835 | u32 temp; | |
836 | ||
837 | /* adv_rd_off */ | |
838 | temp = dev_t->t_avdp_r; | |
839 | /* XXX: mux check required ? */ | |
840 | if (mux) { | |
841 | /* XXX: t_avdp not to be required for sync, only added for tusb | |
842 | * this indirectly necessitates requirement of t_avdp_r and | |
843 | * t_avdp_w instead of having a single t_avdp | |
844 | */ | |
845 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh); | |
846 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
847 | } | |
848 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
849 | ||
850 | /* oe_on */ | |
851 | temp = dev_t->t_oeasu; /* XXX: remove this ? */ | |
852 | if (mux) { | |
853 | temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach); | |
854 | temp = max_t(u32, temp, gpmc_t->adv_rd_off + | |
855 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe)); | |
856 | } | |
857 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
858 | ||
859 | /* access */ | |
860 | /* XXX: any scope for improvement ?, by combining oe_on | |
861 | * and clk_activation, need to check whether | |
862 | * access = clk_activation + round to sync clk ? | |
863 | */ | |
864 | temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk); | |
865 | temp += gpmc_t->clk_activation; | |
866 | if (dev_t->cyc_oe) | |
867 | temp = max_t(u32, temp, gpmc_t->oe_on + | |
868 | gpmc_ticks_to_ps(dev_t->cyc_oe)); | |
869 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
870 | ||
871 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
872 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
873 | ||
874 | /* rd_cycle */ | |
875 | temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez); | |
876 | temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) + | |
877 | gpmc_t->access; | |
878 | /* XXX: barter t_ce_rdyz with t_cez_r ? */ | |
879 | if (dev_t->t_ce_rdyz) | |
880 | temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz); | |
881 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
886 | static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t, | |
887 | struct gpmc_device_timings *dev_t) | |
888 | { | |
889 | bool mux = dev_t->mux; | |
890 | u32 temp; | |
891 | ||
892 | /* adv_wr_off */ | |
893 | temp = dev_t->t_avdp_w; | |
894 | if (mux) { | |
895 | temp = max_t(u32, temp, | |
896 | gpmc_t->clk_activation + dev_t->t_avdh); | |
897 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
898 | } | |
899 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
900 | ||
901 | /* wr_data_mux_bus */ | |
902 | temp = max_t(u32, dev_t->t_weasu, | |
903 | gpmc_t->clk_activation + dev_t->t_rdyo); | |
904 | /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?, | |
905 | * and in that case remember to handle we_on properly | |
906 | */ | |
907 | if (mux) { | |
908 | temp = max_t(u32, temp, | |
909 | gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
910 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
911 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
912 | } | |
913 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
914 | ||
915 | /* we_on */ | |
916 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
917 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
918 | else | |
919 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
920 | ||
921 | /* wr_access */ | |
922 | /* XXX: gpmc_capability check reqd ? , even if not, will not harm */ | |
923 | gpmc_t->wr_access = gpmc_t->access; | |
924 | ||
925 | /* we_off */ | |
926 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
927 | temp = max_t(u32, temp, | |
928 | gpmc_t->wr_access + gpmc_ticks_to_ps(1)); | |
929 | temp = max_t(u32, temp, | |
930 | gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl)); | |
931 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
932 | ||
933 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
934 | dev_t->t_wph); | |
935 | ||
936 | /* wr_cycle */ | |
937 | temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk); | |
938 | temp += gpmc_t->wr_access; | |
939 | /* XXX: barter t_ce_rdyz with t_cez_w ? */ | |
940 | if (dev_t->t_ce_rdyz) | |
941 | temp = max_t(u32, temp, | |
942 | gpmc_t->cs_wr_off + dev_t->t_ce_rdyz); | |
943 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
944 | ||
945 | return 0; | |
946 | } | |
947 | ||
948 | static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t, | |
949 | struct gpmc_device_timings *dev_t) | |
950 | { | |
951 | bool mux = dev_t->mux; | |
952 | u32 temp; | |
953 | ||
954 | /* adv_rd_off */ | |
955 | temp = dev_t->t_avdp_r; | |
956 | if (mux) | |
957 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
958 | gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp); | |
959 | ||
960 | /* oe_on */ | |
961 | temp = dev_t->t_oeasu; | |
962 | if (mux) | |
963 | temp = max_t(u32, temp, | |
964 | gpmc_t->adv_rd_off + dev_t->t_aavdh); | |
965 | gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp); | |
966 | ||
967 | /* access */ | |
968 | temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */ | |
969 | gpmc_t->oe_on + dev_t->t_oe); | |
970 | temp = max_t(u32, temp, | |
971 | gpmc_t->cs_on + dev_t->t_ce); | |
972 | temp = max_t(u32, temp, | |
973 | gpmc_t->adv_on + dev_t->t_aa); | |
974 | gpmc_t->access = gpmc_round_ps_to_ticks(temp); | |
975 | ||
976 | gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1); | |
977 | gpmc_t->cs_rd_off = gpmc_t->oe_off; | |
978 | ||
979 | /* rd_cycle */ | |
980 | temp = max_t(u32, dev_t->t_rd_cycle, | |
981 | gpmc_t->cs_rd_off + dev_t->t_cez_r); | |
982 | temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez); | |
983 | gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp); | |
984 | ||
985 | return 0; | |
986 | } | |
987 | ||
988 | static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t, | |
989 | struct gpmc_device_timings *dev_t) | |
990 | { | |
991 | bool mux = dev_t->mux; | |
992 | u32 temp; | |
993 | ||
994 | /* adv_wr_off */ | |
995 | temp = dev_t->t_avdp_w; | |
996 | if (mux) | |
997 | temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp); | |
998 | gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp); | |
999 | ||
1000 | /* wr_data_mux_bus */ | |
1001 | temp = dev_t->t_weasu; | |
1002 | if (mux) { | |
1003 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh); | |
1004 | temp = max_t(u32, temp, gpmc_t->adv_wr_off + | |
1005 | gpmc_ticks_to_ps(dev_t->cyc_aavdh_we)); | |
1006 | } | |
1007 | gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp); | |
1008 | ||
1009 | /* we_on */ | |
1010 | if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) | |
1011 | gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu); | |
1012 | else | |
1013 | gpmc_t->we_on = gpmc_t->wr_data_mux_bus; | |
1014 | ||
1015 | /* we_off */ | |
1016 | temp = gpmc_t->we_on + dev_t->t_wpl; | |
1017 | gpmc_t->we_off = gpmc_round_ps_to_ticks(temp); | |
1018 | ||
1019 | gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off + | |
1020 | dev_t->t_wph); | |
1021 | ||
1022 | /* wr_cycle */ | |
1023 | temp = max_t(u32, dev_t->t_wr_cycle, | |
1024 | gpmc_t->cs_wr_off + dev_t->t_cez_w); | |
1025 | gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp); | |
1026 | ||
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t, | |
1031 | struct gpmc_device_timings *dev_t) | |
1032 | { | |
1033 | u32 temp; | |
1034 | ||
1035 | gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) * | |
1036 | gpmc_get_fclk_period(); | |
1037 | ||
1038 | gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk( | |
1039 | dev_t->t_bacc, | |
1040 | gpmc_t->sync_clk); | |
1041 | ||
1042 | temp = max_t(u32, dev_t->t_ces, dev_t->t_avds); | |
1043 | gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp); | |
1044 | ||
1045 | if (gpmc_calc_divider(gpmc_t->sync_clk) != 1) | |
1046 | return 0; | |
1047 | ||
1048 | if (dev_t->ce_xdelay) | |
1049 | gpmc_t->bool_timings.cs_extra_delay = true; | |
1050 | if (dev_t->avd_xdelay) | |
1051 | gpmc_t->bool_timings.adv_extra_delay = true; | |
1052 | if (dev_t->oe_xdelay) | |
1053 | gpmc_t->bool_timings.oe_extra_delay = true; | |
1054 | if (dev_t->we_xdelay) | |
1055 | gpmc_t->bool_timings.we_extra_delay = true; | |
1056 | ||
1057 | return 0; | |
1058 | } | |
1059 | ||
1060 | static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t, | |
1061 | struct gpmc_device_timings *dev_t) | |
1062 | { | |
1063 | u32 temp; | |
1064 | ||
1065 | /* cs_on */ | |
1066 | gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu); | |
1067 | ||
1068 | /* adv_on */ | |
1069 | temp = dev_t->t_avdasu; | |
1070 | if (dev_t->t_ce_avd) | |
1071 | temp = max_t(u32, temp, | |
1072 | gpmc_t->cs_on + dev_t->t_ce_avd); | |
1073 | gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp); | |
1074 | ||
1075 | if (dev_t->sync_write || dev_t->sync_read) | |
1076 | gpmc_calc_sync_common_timings(gpmc_t, dev_t); | |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
1081 | /* TODO: remove this function once all peripherals are confirmed to | |
1082 | * work with generic timing. Simultaneously gpmc_cs_set_timings() | |
1083 | * has to be modified to handle timings in ps instead of ns | |
1084 | */ | |
1085 | static void gpmc_convert_ps_to_ns(struct gpmc_timings *t) | |
1086 | { | |
1087 | t->cs_on /= 1000; | |
1088 | t->cs_rd_off /= 1000; | |
1089 | t->cs_wr_off /= 1000; | |
1090 | t->adv_on /= 1000; | |
1091 | t->adv_rd_off /= 1000; | |
1092 | t->adv_wr_off /= 1000; | |
1093 | t->we_on /= 1000; | |
1094 | t->we_off /= 1000; | |
1095 | t->oe_on /= 1000; | |
1096 | t->oe_off /= 1000; | |
1097 | t->page_burst_access /= 1000; | |
1098 | t->access /= 1000; | |
1099 | t->rd_cycle /= 1000; | |
1100 | t->wr_cycle /= 1000; | |
1101 | t->bus_turnaround /= 1000; | |
1102 | t->cycle2cycle_delay /= 1000; | |
1103 | t->wait_monitoring /= 1000; | |
1104 | t->clk_activation /= 1000; | |
1105 | t->wr_access /= 1000; | |
1106 | t->wr_data_mux_bus /= 1000; | |
1107 | } | |
1108 | ||
1109 | int gpmc_calc_timings(struct gpmc_timings *gpmc_t, | |
1110 | struct gpmc_device_timings *dev_t) | |
1111 | { | |
1112 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1113 | ||
1114 | gpmc_calc_common_timings(gpmc_t, dev_t); | |
1115 | ||
1116 | if (dev_t->sync_read) | |
1117 | gpmc_calc_sync_read_timings(gpmc_t, dev_t); | |
1118 | else | |
1119 | gpmc_calc_async_read_timings(gpmc_t, dev_t); | |
1120 | ||
1121 | if (dev_t->sync_write) | |
1122 | gpmc_calc_sync_write_timings(gpmc_t, dev_t); | |
1123 | else | |
1124 | gpmc_calc_async_write_timings(gpmc_t, dev_t); | |
1125 | ||
1126 | /* TODO: remove, see function definition */ | |
1127 | gpmc_convert_ps_to_ns(gpmc_t); | |
1128 | ||
1129 | return 0; | |
1130 | } | |
1131 | ||
bc6b1e7b DM |
1132 | #ifdef CONFIG_OF |
1133 | static struct of_device_id gpmc_dt_ids[] = { | |
1134 | { .compatible = "ti,omap2420-gpmc" }, | |
1135 | { .compatible = "ti,omap2430-gpmc" }, | |
1136 | { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */ | |
1137 | { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */ | |
1138 | { .compatible = "ti,am3352-gpmc" }, /* am335x devices */ | |
1139 | { } | |
1140 | }; | |
1141 | MODULE_DEVICE_TABLE(of, gpmc_dt_ids); | |
1142 | ||
1143 | static void __maybe_unused gpmc_read_timings_dt(struct device_node *np, | |
1144 | struct gpmc_timings *gpmc_t) | |
1145 | { | |
1146 | u32 val; | |
1147 | ||
1148 | memset(gpmc_t, 0, sizeof(*gpmc_t)); | |
1149 | ||
1150 | /* minimum clock period for syncronous mode */ | |
1151 | if (!of_property_read_u32(np, "gpmc,sync-clk", &val)) | |
1152 | gpmc_t->sync_clk = val; | |
1153 | ||
1154 | /* chip select timtings */ | |
1155 | if (!of_property_read_u32(np, "gpmc,cs-on", &val)) | |
1156 | gpmc_t->cs_on = val; | |
1157 | ||
1158 | if (!of_property_read_u32(np, "gpmc,cs-rd-off", &val)) | |
1159 | gpmc_t->cs_rd_off = val; | |
1160 | ||
1161 | if (!of_property_read_u32(np, "gpmc,cs-wr-off", &val)) | |
1162 | gpmc_t->cs_wr_off = val; | |
1163 | ||
1164 | /* ADV signal timings */ | |
1165 | if (!of_property_read_u32(np, "gpmc,adv-on", &val)) | |
1166 | gpmc_t->adv_on = val; | |
1167 | ||
1168 | if (!of_property_read_u32(np, "gpmc,adv-rd-off", &val)) | |
1169 | gpmc_t->adv_rd_off = val; | |
1170 | ||
1171 | if (!of_property_read_u32(np, "gpmc,adv-wr-off", &val)) | |
1172 | gpmc_t->adv_wr_off = val; | |
1173 | ||
1174 | /* WE signal timings */ | |
1175 | if (!of_property_read_u32(np, "gpmc,we-on", &val)) | |
1176 | gpmc_t->we_on = val; | |
1177 | ||
1178 | if (!of_property_read_u32(np, "gpmc,we-off", &val)) | |
1179 | gpmc_t->we_off = val; | |
1180 | ||
1181 | /* OE signal timings */ | |
1182 | if (!of_property_read_u32(np, "gpmc,oe-on", &val)) | |
1183 | gpmc_t->oe_on = val; | |
1184 | ||
1185 | if (!of_property_read_u32(np, "gpmc,oe-off", &val)) | |
1186 | gpmc_t->oe_off = val; | |
1187 | ||
1188 | /* access and cycle timings */ | |
1189 | if (!of_property_read_u32(np, "gpmc,page-burst-access", &val)) | |
1190 | gpmc_t->page_burst_access = val; | |
1191 | ||
1192 | if (!of_property_read_u32(np, "gpmc,access", &val)) | |
1193 | gpmc_t->access = val; | |
1194 | ||
1195 | if (!of_property_read_u32(np, "gpmc,rd-cycle", &val)) | |
1196 | gpmc_t->rd_cycle = val; | |
1197 | ||
1198 | if (!of_property_read_u32(np, "gpmc,wr-cycle", &val)) | |
1199 | gpmc_t->wr_cycle = val; | |
1200 | ||
1201 | /* only for OMAP3430 */ | |
1202 | if (!of_property_read_u32(np, "gpmc,wr-access", &val)) | |
1203 | gpmc_t->wr_access = val; | |
1204 | ||
1205 | if (!of_property_read_u32(np, "gpmc,wr-data-mux-bus", &val)) | |
1206 | gpmc_t->wr_data_mux_bus = val; | |
1207 | } | |
1208 | ||
1209 | #ifdef CONFIG_MTD_NAND | |
1210 | ||
1211 | static const char * const nand_ecc_opts[] = { | |
1212 | [OMAP_ECC_HAMMING_CODE_DEFAULT] = "sw", | |
1213 | [OMAP_ECC_HAMMING_CODE_HW] = "hw", | |
1214 | [OMAP_ECC_HAMMING_CODE_HW_ROMCODE] = "hw-romcode", | |
1215 | [OMAP_ECC_BCH4_CODE_HW] = "bch4", | |
1216 | [OMAP_ECC_BCH8_CODE_HW] = "bch8", | |
1217 | }; | |
1218 | ||
1219 | static int gpmc_probe_nand_child(struct platform_device *pdev, | |
1220 | struct device_node *child) | |
1221 | { | |
1222 | u32 val; | |
1223 | const char *s; | |
1224 | struct gpmc_timings gpmc_t; | |
1225 | struct omap_nand_platform_data *gpmc_nand_data; | |
1226 | ||
1227 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1228 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1229 | child->full_name); | |
1230 | return -ENODEV; | |
1231 | } | |
1232 | ||
1233 | gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data), | |
1234 | GFP_KERNEL); | |
1235 | if (!gpmc_nand_data) | |
1236 | return -ENOMEM; | |
1237 | ||
1238 | gpmc_nand_data->cs = val; | |
1239 | gpmc_nand_data->of_node = child; | |
1240 | ||
1241 | if (!of_property_read_string(child, "ti,nand-ecc-opt", &s)) | |
1242 | for (val = 0; val < ARRAY_SIZE(nand_ecc_opts); val++) | |
1243 | if (!strcasecmp(s, nand_ecc_opts[val])) { | |
1244 | gpmc_nand_data->ecc_opt = val; | |
1245 | break; | |
1246 | } | |
1247 | ||
1248 | val = of_get_nand_bus_width(child); | |
1249 | if (val == 16) | |
1250 | gpmc_nand_data->devsize = NAND_BUSWIDTH_16; | |
1251 | ||
1252 | gpmc_read_timings_dt(child, &gpmc_t); | |
1253 | gpmc_nand_init(gpmc_nand_data, &gpmc_t); | |
1254 | ||
1255 | return 0; | |
1256 | } | |
1257 | #else | |
1258 | static int gpmc_probe_nand_child(struct platform_device *pdev, | |
1259 | struct device_node *child) | |
1260 | { | |
1261 | return 0; | |
1262 | } | |
1263 | #endif | |
1264 | ||
75d3625e EG |
1265 | #ifdef CONFIG_MTD_ONENAND |
1266 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1267 | struct device_node *child) | |
1268 | { | |
1269 | u32 val; | |
1270 | struct omap_onenand_platform_data *gpmc_onenand_data; | |
1271 | ||
1272 | if (of_property_read_u32(child, "reg", &val) < 0) { | |
1273 | dev_err(&pdev->dev, "%s has no 'reg' property\n", | |
1274 | child->full_name); | |
1275 | return -ENODEV; | |
1276 | } | |
1277 | ||
1278 | gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data), | |
1279 | GFP_KERNEL); | |
1280 | if (!gpmc_onenand_data) | |
1281 | return -ENOMEM; | |
1282 | ||
1283 | gpmc_onenand_data->cs = val; | |
1284 | gpmc_onenand_data->of_node = child; | |
1285 | gpmc_onenand_data->dma_channel = -1; | |
1286 | ||
1287 | if (!of_property_read_u32(child, "dma-channel", &val)) | |
1288 | gpmc_onenand_data->dma_channel = val; | |
1289 | ||
1290 | gpmc_onenand_init(gpmc_onenand_data); | |
1291 | ||
1292 | return 0; | |
1293 | } | |
1294 | #else | |
1295 | static int gpmc_probe_onenand_child(struct platform_device *pdev, | |
1296 | struct device_node *child) | |
1297 | { | |
1298 | return 0; | |
1299 | } | |
1300 | #endif | |
1301 | ||
bc6b1e7b DM |
1302 | static int gpmc_probe_dt(struct platform_device *pdev) |
1303 | { | |
1304 | int ret; | |
1305 | struct device_node *child; | |
1306 | const struct of_device_id *of_id = | |
1307 | of_match_device(gpmc_dt_ids, &pdev->dev); | |
1308 | ||
1309 | if (!of_id) | |
1310 | return 0; | |
1311 | ||
1312 | for_each_node_by_name(child, "nand") { | |
1313 | ret = gpmc_probe_nand_child(pdev, child); | |
a1672370 EG |
1314 | if (ret < 0) { |
1315 | of_node_put(child); | |
bc6b1e7b | 1316 | return ret; |
a1672370 | 1317 | } |
bc6b1e7b DM |
1318 | } |
1319 | ||
75d3625e EG |
1320 | for_each_node_by_name(child, "onenand") { |
1321 | ret = gpmc_probe_onenand_child(pdev, child); | |
1322 | if (ret < 0) { | |
1323 | of_node_put(child); | |
1324 | return ret; | |
1325 | } | |
1326 | } | |
bc6b1e7b DM |
1327 | return 0; |
1328 | } | |
1329 | #else | |
1330 | static int gpmc_probe_dt(struct platform_device *pdev) | |
1331 | { | |
1332 | return 0; | |
1333 | } | |
1334 | #endif | |
1335 | ||
351a102d | 1336 | static int gpmc_probe(struct platform_device *pdev) |
4bbbc1ad | 1337 | { |
8119024e | 1338 | int rc; |
6b6c32fc | 1339 | u32 l; |
da496873 | 1340 | struct resource *res; |
4bbbc1ad | 1341 | |
da496873 AM |
1342 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1343 | if (res == NULL) | |
1344 | return -ENOENT; | |
8d08436d | 1345 | |
da496873 AM |
1346 | phys_base = res->start; |
1347 | mem_size = resource_size(res); | |
fd1dc87d | 1348 | |
5857bd98 TR |
1349 | gpmc_base = devm_ioremap_resource(&pdev->dev, res); |
1350 | if (IS_ERR(gpmc_base)) | |
1351 | return PTR_ERR(gpmc_base); | |
da496873 AM |
1352 | |
1353 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
1354 | if (res == NULL) | |
1355 | dev_warn(&pdev->dev, "Failed to get resource: irq\n"); | |
1356 | else | |
1357 | gpmc_irq = res->start; | |
1358 | ||
1359 | gpmc_l3_clk = clk_get(&pdev->dev, "fck"); | |
1360 | if (IS_ERR(gpmc_l3_clk)) { | |
1361 | dev_err(&pdev->dev, "error: clk_get\n"); | |
1362 | gpmc_irq = 0; | |
1363 | return PTR_ERR(gpmc_l3_clk); | |
fd1dc87d PW |
1364 | } |
1365 | ||
4d7cb45e | 1366 | clk_prepare_enable(gpmc_l3_clk); |
1daa8c1d | 1367 | |
da496873 AM |
1368 | gpmc_dev = &pdev->dev; |
1369 | ||
4bbbc1ad | 1370 | l = gpmc_read_reg(GPMC_REVISION); |
da496873 AM |
1371 | if (GPMC_REVISION_MAJOR(l) > 0x4) |
1372 | gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS; | |
1373 | dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l), | |
1374 | GPMC_REVISION_MINOR(l)); | |
1375 | ||
8119024e | 1376 | rc = gpmc_mem_init(); |
71856843 | 1377 | if (rc < 0) { |
8119024e JH |
1378 | clk_disable_unprepare(gpmc_l3_clk); |
1379 | clk_put(gpmc_l3_clk); | |
1380 | dev_err(gpmc_dev, "failed to reserve memory\n"); | |
1381 | return rc; | |
1382 | } | |
db97eb7d | 1383 | |
71856843 | 1384 | if (gpmc_setup_irq() < 0) |
da496873 AM |
1385 | dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); |
1386 | ||
31d9adca JH |
1387 | /* Now the GPMC is initialised, unreserve the chip-selects */ |
1388 | gpmc_cs_map = 0; | |
1389 | ||
bc6b1e7b DM |
1390 | rc = gpmc_probe_dt(pdev); |
1391 | if (rc < 0) { | |
1392 | clk_disable_unprepare(gpmc_l3_clk); | |
1393 | clk_put(gpmc_l3_clk); | |
1394 | dev_err(gpmc_dev, "failed to probe DT parameters\n"); | |
1395 | return rc; | |
1396 | } | |
1397 | ||
da496873 AM |
1398 | return 0; |
1399 | } | |
1400 | ||
351a102d | 1401 | static int gpmc_remove(struct platform_device *pdev) |
da496873 AM |
1402 | { |
1403 | gpmc_free_irq(); | |
1404 | gpmc_mem_exit(); | |
1405 | gpmc_dev = NULL; | |
1406 | return 0; | |
1407 | } | |
1408 | ||
1409 | static struct platform_driver gpmc_driver = { | |
1410 | .probe = gpmc_probe, | |
351a102d | 1411 | .remove = gpmc_remove, |
da496873 AM |
1412 | .driver = { |
1413 | .name = DEVICE_NAME, | |
1414 | .owner = THIS_MODULE, | |
bc6b1e7b | 1415 | .of_match_table = of_match_ptr(gpmc_dt_ids), |
da496873 AM |
1416 | }, |
1417 | }; | |
1418 | ||
1419 | static __init int gpmc_init(void) | |
1420 | { | |
1421 | return platform_driver_register(&gpmc_driver); | |
1422 | } | |
1423 | ||
1424 | static __exit void gpmc_exit(void) | |
1425 | { | |
1426 | platform_driver_unregister(&gpmc_driver); | |
1427 | ||
db97eb7d | 1428 | } |
da496873 | 1429 | |
b76c8b19 | 1430 | omap_postcore_initcall(gpmc_init); |
da496873 | 1431 | module_exit(gpmc_exit); |
db97eb7d | 1432 | |
4be48fd5 AM |
1433 | static int __init omap_gpmc_init(void) |
1434 | { | |
1435 | struct omap_hwmod *oh; | |
1436 | struct platform_device *pdev; | |
1437 | char *oh_name = "gpmc"; | |
1438 | ||
2f98ca89 DM |
1439 | /* |
1440 | * if the board boots up with a populated DT, do not | |
1441 | * manually add the device from this initcall | |
1442 | */ | |
1443 | if (of_have_populated_dt()) | |
1444 | return -ENODEV; | |
1445 | ||
4be48fd5 AM |
1446 | oh = omap_hwmod_lookup(oh_name); |
1447 | if (!oh) { | |
1448 | pr_err("Could not look up %s\n", oh_name); | |
1449 | return -ENODEV; | |
1450 | } | |
1451 | ||
c1d1cd59 | 1452 | pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0); |
4be48fd5 AM |
1453 | WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name); |
1454 | ||
1455 | return IS_ERR(pdev) ? PTR_ERR(pdev) : 0; | |
1456 | } | |
b76c8b19 | 1457 | omap_postcore_initcall(omap_gpmc_init); |
4be48fd5 | 1458 | |
db97eb7d SG |
1459 | static irqreturn_t gpmc_handle_irq(int irq, void *dev) |
1460 | { | |
6b6c32fc AM |
1461 | int i; |
1462 | u32 regval; | |
1463 | ||
1464 | regval = gpmc_read_reg(GPMC_IRQSTATUS); | |
1465 | ||
1466 | if (!regval) | |
1467 | return IRQ_NONE; | |
1468 | ||
1469 | for (i = 0; i < GPMC_NR_IRQ; i++) | |
1470 | if (regval & gpmc_client_irq[i].bitmask) | |
1471 | generic_handle_irq(gpmc_client_irq[i].irq); | |
db97eb7d | 1472 | |
6b6c32fc | 1473 | gpmc_write_reg(GPMC_IRQSTATUS, regval); |
db97eb7d SG |
1474 | |
1475 | return IRQ_HANDLED; | |
4bbbc1ad | 1476 | } |
a2d3e7ba RN |
1477 | |
1478 | #ifdef CONFIG_ARCH_OMAP3 | |
1479 | static struct omap3_gpmc_regs gpmc_context; | |
1480 | ||
b2fa3b7c | 1481 | void omap3_gpmc_save_context(void) |
a2d3e7ba RN |
1482 | { |
1483 | int i; | |
b2fa3b7c | 1484 | |
a2d3e7ba RN |
1485 | gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG); |
1486 | gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE); | |
1487 | gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL); | |
1488 | gpmc_context.config = gpmc_read_reg(GPMC_CONFIG); | |
1489 | gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1); | |
1490 | gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2); | |
1491 | gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL); | |
1492 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
1493 | gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i); | |
1494 | if (gpmc_context.cs_context[i].is_valid) { | |
1495 | gpmc_context.cs_context[i].config1 = | |
1496 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG1); | |
1497 | gpmc_context.cs_context[i].config2 = | |
1498 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG2); | |
1499 | gpmc_context.cs_context[i].config3 = | |
1500 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG3); | |
1501 | gpmc_context.cs_context[i].config4 = | |
1502 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG4); | |
1503 | gpmc_context.cs_context[i].config5 = | |
1504 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG5); | |
1505 | gpmc_context.cs_context[i].config6 = | |
1506 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG6); | |
1507 | gpmc_context.cs_context[i].config7 = | |
1508 | gpmc_cs_read_reg(i, GPMC_CS_CONFIG7); | |
1509 | } | |
1510 | } | |
1511 | } | |
1512 | ||
b2fa3b7c | 1513 | void omap3_gpmc_restore_context(void) |
a2d3e7ba RN |
1514 | { |
1515 | int i; | |
b2fa3b7c | 1516 | |
a2d3e7ba RN |
1517 | gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig); |
1518 | gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable); | |
1519 | gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl); | |
1520 | gpmc_write_reg(GPMC_CONFIG, gpmc_context.config); | |
1521 | gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1); | |
1522 | gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2); | |
1523 | gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control); | |
1524 | for (i = 0; i < GPMC_CS_NUM; i++) { | |
1525 | if (gpmc_context.cs_context[i].is_valid) { | |
1526 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG1, | |
1527 | gpmc_context.cs_context[i].config1); | |
1528 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG2, | |
1529 | gpmc_context.cs_context[i].config2); | |
1530 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG3, | |
1531 | gpmc_context.cs_context[i].config3); | |
1532 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG4, | |
1533 | gpmc_context.cs_context[i].config4); | |
1534 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG5, | |
1535 | gpmc_context.cs_context[i].config5); | |
1536 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG6, | |
1537 | gpmc_context.cs_context[i].config6); | |
1538 | gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, | |
1539 | gpmc_context.cs_context[i].config7); | |
1540 | } | |
1541 | } | |
1542 | } | |
1543 | #endif /* CONFIG_ARCH_OMAP3 */ |