Commit | Line | Data |
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2f70a1e9 VS |
1 | /* |
2 | * gpmc-nand.c | |
3 | * | |
4 | * Copyright (C) 2009 Texas Instruments | |
5 | * Vimal Singh <vimalsingh@ti.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/platform_device.h> | |
14 | #include <linux/io.h> | |
d5ce2b65 | 15 | #include <linux/mtd/nand.h> |
2203747c | 16 | #include <linux/platform_data/mtd-nand-omap2.h> |
2f70a1e9 VS |
17 | |
18 | #include <asm/mach/flash.h> | |
19 | ||
3ef5d007 | 20 | #include "gpmc.h" |
dbc04161 | 21 | #include "soc.h" |
bc3668ea AM |
22 | #include "gpmc-nand.h" |
23 | ||
24 | /* minimum size for IO mapping */ | |
25 | #define NAND_IO_SIZE 4 | |
dbc04161 | 26 | |
2ee30f05 AM |
27 | static struct resource gpmc_nand_resource[] = { |
28 | { | |
29 | .flags = IORESOURCE_MEM, | |
30 | }, | |
31 | { | |
32 | .flags = IORESOURCE_IRQ, | |
33 | }, | |
34 | { | |
35 | .flags = IORESOURCE_IRQ, | |
36 | }, | |
2f70a1e9 VS |
37 | }; |
38 | ||
39 | static struct platform_device gpmc_nand_device = { | |
40 | .name = "omap2-nand", | |
41 | .id = 0, | |
2ee30f05 AM |
42 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), |
43 | .resource = gpmc_nand_resource, | |
2f70a1e9 VS |
44 | }; |
45 | ||
504f3c6d | 46 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
3852ccd6 | 47 | { |
0611c419 | 48 | /* platforms which support all ECC schemes */ |
2e091d13 | 49 | if (soc_is_am33xx() || soc_is_am43xx() || cpu_is_omap44xx() || |
0611c419 PG |
50 | soc_is_omap54xx() || soc_is_dra7xx()) |
51 | return 1; | |
52 | ||
33753cd2 CF |
53 | if (ecc_opt == OMAP_ECC_BCH4_CODE_HW_DETECTION_SW || |
54 | ecc_opt == OMAP_ECC_BCH8_CODE_HW_DETECTION_SW) { | |
55 | if (cpu_is_omap24xx()) | |
56 | return 0; | |
57 | else if (cpu_is_omap3630() && (GET_OMAP_REVISION() == 0)) | |
58 | return 0; | |
59 | else | |
60 | return 1; | |
61 | } | |
62 | ||
0611c419 PG |
63 | /* OMAP3xxx do not have ELM engine, so cannot support ECC schemes |
64 | * which require H/W based ECC error detection */ | |
65 | if ((cpu_is_omap34xx() || cpu_is_omap3630()) && | |
66 | ((ecc_opt == OMAP_ECC_BCH4_CODE_HW) || | |
67 | (ecc_opt == OMAP_ECC_BCH8_CODE_HW))) | |
3852ccd6 | 68 | return 0; |
3852ccd6 | 69 | |
0611c419 PG |
70 | /* legacy platforms support only HAM1 (1-bit Hamming) ECC scheme */ |
71 | if (ecc_opt == OMAP_ECC_HAM1_CODE_HW) | |
72 | return 1; | |
73 | else | |
74 | return 0; | |
3852ccd6 AM |
75 | } |
76 | ||
d0020cc6 EG |
77 | /* This function will go away once the device-tree convertion is complete */ |
78 | static void gpmc_set_legacy(struct omap_nand_platform_data *gpmc_nand_data, | |
79 | struct gpmc_settings *s) | |
80 | { | |
81 | /* Enable RD PIN Monitoring Reg */ | |
82 | if (gpmc_nand_data->dev_ready) { | |
83 | s->wait_on_read = true; | |
84 | s->wait_on_write = true; | |
85 | } | |
bbc28cdb EG |
86 | |
87 | if (gpmc_nand_data->devsize == NAND_BUSWIDTH_16) | |
88 | s->device_width = GPMC_DEVWIDTH_16BIT; | |
89 | else | |
90 | s->device_width = GPMC_DEVWIDTH_8BIT; | |
d0020cc6 EG |
91 | } |
92 | ||
504f3c6d DM |
93 | int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, |
94 | struct gpmc_timings *gpmc_t) | |
2f70a1e9 | 95 | { |
2f70a1e9 | 96 | int err = 0; |
24db7ecc | 97 | struct gpmc_settings s; |
2f70a1e9 VS |
98 | struct device *dev = &gpmc_nand_device.dev; |
99 | ||
24db7ecc JH |
100 | memset(&s, 0, sizeof(struct gpmc_settings)); |
101 | ||
2f70a1e9 VS |
102 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; |
103 | ||
104 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | |
2ee30f05 | 105 | (unsigned long *)&gpmc_nand_resource[0].start); |
2f70a1e9 | 106 | if (err < 0) { |
097c9dae EG |
107 | dev_err(dev, "Cannot request GPMC CS %d, error %d\n", |
108 | gpmc_nand_data->cs, err); | |
2f70a1e9 VS |
109 | return err; |
110 | } | |
111 | ||
2ee30f05 AM |
112 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + |
113 | NAND_IO_SIZE - 1; | |
9222e3a7 | 114 | |
2ee30f05 AM |
115 | gpmc_nand_resource[1].start = |
116 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | |
117 | gpmc_nand_resource[2].start = | |
118 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | |
bc3668ea AM |
119 | |
120 | if (gpmc_t) { | |
4d584361 | 121 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); |
bc3668ea AM |
122 | if (err < 0) { |
123 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); | |
124 | return err; | |
125 | } | |
e2e699b1 | 126 | } |
2f70a1e9 | 127 | |
d0020cc6 | 128 | if (gpmc_nand_data->of_node) |
e2e699b1 | 129 | gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); |
d0020cc6 EG |
130 | else |
131 | gpmc_set_legacy(gpmc_nand_data, &s); | |
24db7ecc | 132 | |
e2e699b1 | 133 | s.device_nand = true; |
f40739fa | 134 | |
e2e699b1 EG |
135 | err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); |
136 | if (err < 0) | |
137 | goto out_free_cs; | |
24db7ecc | 138 | |
e2e699b1 EG |
139 | err = gpmc_configure(GPMC_CONFIG_WP, 0); |
140 | if (err < 0) | |
141 | goto out_free_cs; | |
2f70a1e9 | 142 | |
d126d015 AM |
143 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
144 | ||
0611c419 PG |
145 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { |
146 | dev_err(dev, "Unsupported NAND ECC scheme selected\n"); | |
3852ccd6 | 147 | return -EINVAL; |
0611c419 | 148 | } |
3852ccd6 | 149 | |
2f70a1e9 VS |
150 | err = platform_device_register(&gpmc_nand_device); |
151 | if (err < 0) { | |
152 | dev_err(dev, "Unable to register NAND device\n"); | |
153 | goto out_free_cs; | |
154 | } | |
155 | ||
156 | return 0; | |
157 | ||
158 | out_free_cs: | |
159 | gpmc_cs_free(gpmc_nand_data->cs); | |
160 | ||
161 | return err; | |
162 | } |