Commit | Line | Data |
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97f67898 RN |
1 | /* |
2 | * OMAP4-specific DPLL control functions | |
3 | * | |
4 | * Copyright (C) 2011 Texas Instruments, Inc. | |
5 | * Rajendra Nayak | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/clk.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/bitops.h> | |
17 | ||
97f67898 | 18 | #include "clock.h" |
a1900f2e | 19 | #include "clock44xx.h" |
97f67898 RN |
20 | #include "cm-regbits-44xx.h" |
21 | ||
3ff51ed8 JH |
22 | /* |
23 | * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that | |
24 | * can supported when using the DPLL low-power mode. Frequencies are | |
25 | * defined in OMAP4430/60 Public TRM section 3.6.3.3.2 "Enable Control, | |
26 | * Status, and Low-Power Operation Mode". | |
27 | */ | |
28 | #define OMAP4_DPLL_LP_FINT_MAX 1000000 | |
29 | #define OMAP4_DPLL_LP_FOUT_MAX 100000000 | |
30 | ||
97f67898 | 31 | /* Supported only on OMAP4 */ |
32cc0021 | 32 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) |
97f67898 RN |
33 | { |
34 | u32 v; | |
35 | u32 mask; | |
36 | ||
74b9b62b | 37 | if (!clk || !clk->clksel_reg) |
97f67898 RN |
38 | return -EINVAL; |
39 | ||
40 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
41 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
42 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
43 | ||
519ab8b2 | 44 | v = omap2_clk_readl(clk, clk->clksel_reg); |
97f67898 RN |
45 | v &= mask; |
46 | v >>= __ffs(mask); | |
47 | ||
48 | return v; | |
49 | } | |
50 | ||
32cc0021 | 51 | void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
52 | { |
53 | u32 v; | |
54 | u32 mask; | |
55 | ||
74b9b62b | 56 | if (!clk || !clk->clksel_reg) |
97f67898 RN |
57 | return; |
58 | ||
59 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
60 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
61 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
62 | ||
519ab8b2 | 63 | v = omap2_clk_readl(clk, clk->clksel_reg); |
97f67898 RN |
64 | /* Clear the bit to allow gatectrl */ |
65 | v &= ~mask; | |
519ab8b2 | 66 | omap2_clk_writel(v, clk, clk->clksel_reg); |
97f67898 RN |
67 | } |
68 | ||
32cc0021 | 69 | void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) |
97f67898 RN |
70 | { |
71 | u32 v; | |
72 | u32 mask; | |
73 | ||
74b9b62b | 74 | if (!clk || !clk->clksel_reg) |
97f67898 RN |
75 | return; |
76 | ||
77 | mask = clk->flags & CLOCK_CLKOUTX2 ? | |
78 | OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK : | |
79 | OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK; | |
80 | ||
519ab8b2 | 81 | v = omap2_clk_readl(clk, clk->clksel_reg); |
97f67898 RN |
82 | /* Set the bit to deny gatectrl */ |
83 | v |= mask; | |
519ab8b2 | 84 | omap2_clk_writel(v, clk, clk->clksel_reg); |
97f67898 | 85 | } |
70db8a62 | 86 | |
32cc0021 MT |
87 | const struct clk_hw_omap_ops clkhwops_omap4_dpllmx = { |
88 | .allow_idle = omap4_dpllmx_allow_gatectrl, | |
89 | .deny_idle = omap4_dpllmx_deny_gatectrl, | |
90 | }; | |
70db8a62 | 91 | |
3ff51ed8 JH |
92 | /** |
93 | * omap4_dpll_lpmode_recalc - compute DPLL low-power setting | |
94 | * @dd: pointer to the dpll data structure | |
95 | * | |
96 | * Calculates if low-power mode can be enabled based upon the last | |
97 | * multiplier and divider values calculated. If low-power mode can be | |
98 | * enabled, then the bit to enable low-power mode is stored in the | |
99 | * last_rounded_lpmode variable. This implementation is based upon the | |
100 | * criteria for enabling low-power mode as described in the OMAP4430/60 | |
101 | * Public TRM section 3.6.3.3.2 "Enable Control, Status, and Low-Power | |
102 | * Operation Mode". | |
103 | */ | |
104 | static void omap4_dpll_lpmode_recalc(struct dpll_data *dd) | |
105 | { | |
106 | long fint, fout; | |
107 | ||
108 | fint = __clk_get_rate(dd->clk_ref) / (dd->last_rounded_n + 1); | |
109 | fout = fint * dd->last_rounded_m; | |
110 | ||
111 | if ((fint < OMAP4_DPLL_LP_FINT_MAX) && (fout < OMAP4_DPLL_LP_FOUT_MAX)) | |
112 | dd->last_rounded_lpmode = 1; | |
113 | else | |
114 | dd->last_rounded_lpmode = 0; | |
115 | } | |
116 | ||
a1900f2e MT |
117 | /** |
118 | * omap4_dpll_regm4xen_recalc - compute DPLL rate, considering REGM4XEN bit | |
119 | * @clk: struct clk * of the DPLL to compute the rate for | |
120 | * | |
121 | * Compute the output rate for the OMAP4 DPLL represented by @clk. | |
122 | * Takes the REGM4XEN bit into consideration, which is needed for the | |
123 | * OMAP4 ABE DPLL. Returns the DPLL's output rate (before M-dividers) | |
124 | * upon success, or 0 upon error. | |
125 | */ | |
32cc0021 MT |
126 | unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw, |
127 | unsigned long parent_rate) | |
128 | { | |
129 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
130 | u32 v; |
131 | unsigned long rate; | |
132 | struct dpll_data *dd; | |
133 | ||
134 | if (!clk || !clk->dpll_data) | |
135 | return 0; | |
136 | ||
137 | dd = clk->dpll_data; | |
138 | ||
139 | rate = omap2_get_dpll_rate(clk); | |
140 | ||
141 | /* regm4xen adds a multiplier of 4 to DPLL calculations */ | |
519ab8b2 | 142 | v = omap2_clk_readl(clk, dd->control_reg); |
a1900f2e MT |
143 | if (v & OMAP4430_DPLL_REGM4XEN_MASK) |
144 | rate *= OMAP4430_REGM4XEN_MULT; | |
145 | ||
146 | return rate; | |
147 | } | |
148 | ||
149 | /** | |
150 | * omap4_dpll_regm4xen_round_rate - round DPLL rate, considering REGM4XEN bit | |
151 | * @clk: struct clk * of the DPLL to round a rate for | |
152 | * @target_rate: the desired rate of the DPLL | |
153 | * | |
154 | * Compute the rate that would be programmed into the DPLL hardware | |
155 | * for @clk if set_rate() were to be provided with the rate | |
156 | * @target_rate. Takes the REGM4XEN bit into consideration, which is | |
157 | * needed for the OMAP4 ABE DPLL. Returns the rounded rate (before | |
158 | * M-dividers) upon success, -EINVAL if @clk is null or not a DPLL, or | |
159 | * ~0 if an error occurred in omap2_dpll_round_rate(). | |
160 | */ | |
32cc0021 MT |
161 | long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw, |
162 | unsigned long target_rate, | |
163 | unsigned long *parent_rate) | |
164 | { | |
165 | struct clk_hw_omap *clk = to_clk_hw_omap(hw); | |
a1900f2e MT |
166 | struct dpll_data *dd; |
167 | long r; | |
168 | ||
169 | if (!clk || !clk->dpll_data) | |
170 | return -EINVAL; | |
171 | ||
172 | dd = clk->dpll_data; | |
173 | ||
3ff51ed8 | 174 | dd->last_rounded_m4xen = 0; |
a1900f2e | 175 | |
3ff51ed8 JH |
176 | /* |
177 | * First try to compute the DPLL configuration for | |
178 | * target rate without using the 4X multiplier. | |
179 | */ | |
32cc0021 | 180 | r = omap2_dpll_round_rate(hw, target_rate, NULL); |
3ff51ed8 JH |
181 | if (r != ~0) |
182 | goto out; | |
183 | ||
184 | /* | |
185 | * If we did not find a valid DPLL configuration, try again, but | |
186 | * this time see if using the 4X multiplier can help. Enabling the | |
187 | * 4X multiplier is equivalent to dividing the target rate by 4. | |
188 | */ | |
189 | r = omap2_dpll_round_rate(hw, target_rate / OMAP4430_REGM4XEN_MULT, | |
190 | NULL); | |
a1900f2e MT |
191 | if (r == ~0) |
192 | return r; | |
193 | ||
3ff51ed8 JH |
194 | dd->last_rounded_rate *= OMAP4430_REGM4XEN_MULT; |
195 | dd->last_rounded_m4xen = 1; | |
196 | ||
197 | out: | |
198 | omap4_dpll_lpmode_recalc(dd); | |
a1900f2e | 199 | |
3ff51ed8 | 200 | return dd->last_rounded_rate; |
a1900f2e | 201 | } |