Commit | Line | Data |
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a1391d27 RN |
1 | /* |
2 | * OMAP3/4 - specific DPLL control functions | |
3 | * | |
358965d7 RW |
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. |
5 | * Copyright (C) 2009-2010 Nokia Corporation | |
a1391d27 RN |
6 | * |
7 | * Written by Paul Walmsley | |
358965d7 RW |
8 | * Testing and integration fixes by Jouni Högander |
9 | * | |
10 | * 36xx support added by Vishwanath BS, Richard Woodruff, and Nishanth | |
11 | * Menon | |
a1391d27 RN |
12 | * |
13 | * Parts of this code are based on code written by | |
14 | * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
a1391d27 RN |
21 | #include <linux/kernel.h> |
22 | #include <linux/device.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/delay.h> | |
26 | #include <linux/clk.h> | |
27 | #include <linux/io.h> | |
a1391d27 | 28 | #include <linux/bitops.h> |
6d803ba7 | 29 | #include <linux/clkdev.h> |
a1391d27 | 30 | |
16975a79 RN |
31 | #include <plat/cpu.h> |
32 | #include <plat/clock.h> | |
a1391d27 RN |
33 | |
34 | #include "clock.h" | |
59fb659b | 35 | #include "cm2xxx_3xxx.h" |
a1391d27 RN |
36 | #include "cm-regbits-34xx.h" |
37 | ||
38 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | |
39 | #define DPLL_AUTOIDLE_DISABLE 0x0 | |
40 | #define DPLL_AUTOIDLE_LOW_POWER_STOP 0x1 | |
41 | ||
42 | #define MAX_DPLL_WAIT_TRIES 1000000 | |
43 | ||
60c3f651 | 44 | /* Private functions */ |
a1391d27 RN |
45 | |
46 | /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ | |
47 | static void _omap3_dpll_write_clken(struct clk *clk, u8 clken_bits) | |
48 | { | |
49 | const struct dpll_data *dd; | |
50 | u32 v; | |
51 | ||
52 | dd = clk->dpll_data; | |
53 | ||
54 | v = __raw_readl(dd->control_reg); | |
55 | v &= ~dd->enable_mask; | |
56 | v |= clken_bits << __ffs(dd->enable_mask); | |
57 | __raw_writel(v, dd->control_reg); | |
58 | } | |
59 | ||
60 | /* _omap3_wait_dpll_status: wait for a DPLL to enter a specific state */ | |
61 | static int _omap3_wait_dpll_status(struct clk *clk, u8 state) | |
62 | { | |
63 | const struct dpll_data *dd; | |
64 | int i = 0; | |
65 | int ret = -EINVAL; | |
66 | ||
67 | dd = clk->dpll_data; | |
68 | ||
69 | state <<= __ffs(dd->idlest_mask); | |
70 | ||
71 | while (((__raw_readl(dd->idlest_reg) & dd->idlest_mask) != state) && | |
72 | i < MAX_DPLL_WAIT_TRIES) { | |
73 | i++; | |
74 | udelay(1); | |
75 | } | |
76 | ||
77 | if (i == MAX_DPLL_WAIT_TRIES) { | |
78 | printk(KERN_ERR "clock: %s failed transition to '%s'\n", | |
79 | clk->name, (state) ? "locked" : "bypassed"); | |
80 | } else { | |
81 | pr_debug("clock: %s transition to '%s' in %d loops\n", | |
82 | clk->name, (state) ? "locked" : "bypassed", i); | |
83 | ||
84 | ret = 0; | |
85 | } | |
86 | ||
87 | return ret; | |
88 | } | |
89 | ||
90 | /* From 3430 TRM ES2 4.7.6.2 */ | |
91 | static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n) | |
92 | { | |
93 | unsigned long fint; | |
94 | u16 f = 0; | |
95 | ||
96 | fint = clk->dpll_data->clk_ref->rate / n; | |
97 | ||
98 | pr_debug("clock: fint is %lu\n", fint); | |
99 | ||
100 | if (fint >= 750000 && fint <= 1000000) | |
101 | f = 0x3; | |
102 | else if (fint > 1000000 && fint <= 1250000) | |
103 | f = 0x4; | |
104 | else if (fint > 1250000 && fint <= 1500000) | |
105 | f = 0x5; | |
106 | else if (fint > 1500000 && fint <= 1750000) | |
107 | f = 0x6; | |
108 | else if (fint > 1750000 && fint <= 2100000) | |
109 | f = 0x7; | |
110 | else if (fint > 7500000 && fint <= 10000000) | |
111 | f = 0xB; | |
112 | else if (fint > 10000000 && fint <= 12500000) | |
113 | f = 0xC; | |
114 | else if (fint > 12500000 && fint <= 15000000) | |
115 | f = 0xD; | |
116 | else if (fint > 15000000 && fint <= 17500000) | |
117 | f = 0xE; | |
118 | else if (fint > 17500000 && fint <= 21000000) | |
119 | f = 0xF; | |
120 | else | |
121 | pr_debug("clock: unknown freqsel setting for %d\n", n); | |
122 | ||
123 | return f; | |
124 | } | |
125 | ||
a1391d27 RN |
126 | /* |
127 | * _omap3_noncore_dpll_lock - instruct a DPLL to lock and wait for readiness | |
128 | * @clk: pointer to a DPLL struct clk | |
129 | * | |
130 | * Instructs a non-CORE DPLL to lock. Waits for the DPLL to report | |
131 | * readiness before returning. Will save and restore the DPLL's | |
132 | * autoidle state across the enable, per the CDP code. If the DPLL | |
133 | * locked successfully, return 0; if the DPLL did not lock in the time | |
134 | * allotted, or DPLL3 was passed in, return -EINVAL. | |
135 | */ | |
136 | static int _omap3_noncore_dpll_lock(struct clk *clk) | |
137 | { | |
55ffe163 | 138 | const struct dpll_data *dd; |
a1391d27 | 139 | u8 ai; |
55ffe163 VP |
140 | u8 state = 1; |
141 | int r = 0; | |
a1391d27 RN |
142 | |
143 | pr_debug("clock: locking DPLL %s\n", clk->name); | |
144 | ||
55ffe163 VP |
145 | dd = clk->dpll_data; |
146 | state <<= __ffs(dd->idlest_mask); | |
147 | ||
148 | /* Check if already locked */ | |
149 | if ((__raw_readl(dd->idlest_reg) & dd->idlest_mask) == state) | |
150 | goto done; | |
151 | ||
a1391d27 RN |
152 | ai = omap3_dpll_autoidle_read(clk); |
153 | ||
d76316fe VB |
154 | if (ai) |
155 | omap3_dpll_deny_idle(clk); | |
a1391d27 RN |
156 | |
157 | _omap3_dpll_write_clken(clk, DPLL_LOCKED); | |
158 | ||
159 | r = _omap3_wait_dpll_status(clk, 1); | |
160 | ||
161 | if (ai) | |
162 | omap3_dpll_allow_idle(clk); | |
163 | ||
55ffe163 | 164 | done: |
a1391d27 RN |
165 | return r; |
166 | } | |
167 | ||
168 | /* | |
169 | * _omap3_noncore_dpll_bypass - instruct a DPLL to bypass and wait for readiness | |
170 | * @clk: pointer to a DPLL struct clk | |
171 | * | |
172 | * Instructs a non-CORE DPLL to enter low-power bypass mode. In | |
173 | * bypass mode, the DPLL's rate is set equal to its parent clock's | |
174 | * rate. Waits for the DPLL to report readiness before returning. | |
175 | * Will save and restore the DPLL's autoidle state across the enable, | |
176 | * per the CDP code. If the DPLL entered bypass mode successfully, | |
177 | * return 0; if the DPLL did not enter bypass in the time allotted, or | |
178 | * DPLL3 was passed in, or the DPLL does not support low-power bypass, | |
179 | * return -EINVAL. | |
180 | */ | |
181 | static int _omap3_noncore_dpll_bypass(struct clk *clk) | |
182 | { | |
183 | int r; | |
184 | u8 ai; | |
185 | ||
186 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) | |
187 | return -EINVAL; | |
188 | ||
189 | pr_debug("clock: configuring DPLL %s for low-power bypass\n", | |
190 | clk->name); | |
191 | ||
192 | ai = omap3_dpll_autoidle_read(clk); | |
193 | ||
194 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_BYPASS); | |
195 | ||
196 | r = _omap3_wait_dpll_status(clk, 0); | |
197 | ||
198 | if (ai) | |
199 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
200 | |
201 | return r; | |
202 | } | |
203 | ||
204 | /* | |
205 | * _omap3_noncore_dpll_stop - instruct a DPLL to stop | |
206 | * @clk: pointer to a DPLL struct clk | |
207 | * | |
208 | * Instructs a non-CORE DPLL to enter low-power stop. Will save and | |
209 | * restore the DPLL's autoidle state across the stop, per the CDP | |
210 | * code. If DPLL3 was passed in, or the DPLL does not support | |
211 | * low-power stop, return -EINVAL; otherwise, return 0. | |
212 | */ | |
213 | static int _omap3_noncore_dpll_stop(struct clk *clk) | |
214 | { | |
215 | u8 ai; | |
216 | ||
217 | if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP))) | |
218 | return -EINVAL; | |
219 | ||
220 | pr_debug("clock: stopping DPLL %s\n", clk->name); | |
221 | ||
222 | ai = omap3_dpll_autoidle_read(clk); | |
223 | ||
224 | _omap3_dpll_write_clken(clk, DPLL_LOW_POWER_STOP); | |
225 | ||
226 | if (ai) | |
227 | omap3_dpll_allow_idle(clk); | |
a1391d27 RN |
228 | |
229 | return 0; | |
230 | } | |
231 | ||
358965d7 | 232 | /** |
a36795c1 | 233 | * _lookup_dco - Lookup DCO used by j-type DPLL |
358965d7 RW |
234 | * @clk: pointer to a DPLL struct clk |
235 | * @dco: digital control oscillator selector | |
358965d7 RW |
236 | * @m: DPLL multiplier to set |
237 | * @n: DPLL divider to set | |
238 | * | |
239 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
240 | * | |
241 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
242 | * out in non-multi-OMAP builds for those chips? | |
243 | */ | |
a36795c1 | 244 | static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n) |
358965d7 | 245 | { |
a36795c1 | 246 | unsigned long fint, clkinp; /* watch out for overflow */ |
358965d7 RW |
247 | |
248 | clkinp = clk->parent->rate; | |
249 | fint = (clkinp / n) * m; | |
250 | ||
251 | if (fint < 1000000000) | |
252 | *dco = 2; | |
253 | else | |
254 | *dco = 4; | |
a36795c1 JH |
255 | } |
256 | ||
257 | /** | |
258 | * _lookup_sddiv - Calculate sigma delta divider for j-type DPLL | |
259 | * @clk: pointer to a DPLL struct clk | |
260 | * @sd_div: target sigma-delta divider | |
261 | * @m: DPLL multiplier to set | |
262 | * @n: DPLL divider to set | |
263 | * | |
264 | * See 36xx TRM section 3.5.3.3.3.2 "Type B DPLL (Low-Jitter)" | |
265 | * | |
266 | * XXX This code is not needed for 3430/AM35xx; can it be optimized | |
267 | * out in non-multi-OMAP builds for those chips? | |
268 | */ | |
269 | static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n) | |
270 | { | |
271 | unsigned long clkinp, sd; /* watch out for overflow */ | |
272 | int mod1, mod2; | |
273 | ||
274 | clkinp = clk->parent->rate; | |
275 | ||
358965d7 RW |
276 | /* |
277 | * target sigma-delta to near 250MHz | |
278 | * sd = ceil[(m/(n+1)) * (clkinp_MHz / 250)] | |
279 | */ | |
280 | clkinp /= 100000; /* shift from MHz to 10*Hz for 38.4 and 19.2 */ | |
281 | mod1 = (clkinp * m) % (250 * n); | |
282 | sd = (clkinp * m) / (250 * n); | |
283 | mod2 = sd % 10; | |
284 | sd /= 10; | |
285 | ||
286 | if (mod1 || mod2) | |
287 | sd++; | |
288 | *sd_div = sd; | |
289 | } | |
290 | ||
60c3f651 PW |
291 | /* |
292 | * _omap3_noncore_dpll_program - set non-core DPLL M,N values directly | |
293 | * @clk: struct clk * of DPLL to set | |
294 | * @m: DPLL multiplier to set | |
295 | * @n: DPLL divider to set | |
296 | * @freqsel: FREQSEL value to set | |
297 | * | |
298 | * Program the DPLL with the supplied M, N values, and wait for the DPLL to | |
299 | * lock.. Returns -EINVAL upon error, or 0 upon success. | |
300 | */ | |
301 | static int omap3_noncore_dpll_program(struct clk *clk, u16 m, u8 n, u16 freqsel) | |
302 | { | |
303 | struct dpll_data *dd = clk->dpll_data; | |
a36795c1 | 304 | u8 dco, sd_div; |
60c3f651 PW |
305 | u32 v; |
306 | ||
307 | /* 3430 ES2 TRM: 4.7.6.9 DPLL Programming Sequence */ | |
308 | _omap3_noncore_dpll_bypass(clk); | |
309 | ||
5eb75f55 VB |
310 | /* |
311 | * Set jitter correction. No jitter correction for OMAP4 and 3630 | |
312 | * since freqsel field is no longer present | |
313 | */ | |
314 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | |
60c3f651 PW |
315 | v = __raw_readl(dd->control_reg); |
316 | v &= ~dd->freqsel_mask; | |
317 | v |= freqsel << __ffs(dd->freqsel_mask); | |
318 | __raw_writel(v, dd->control_reg); | |
319 | } | |
320 | ||
321 | /* Set DPLL multiplier, divider */ | |
322 | v = __raw_readl(dd->mult_div1_reg); | |
323 | v &= ~(dd->mult_mask | dd->div1_mask); | |
324 | v |= m << __ffs(dd->mult_mask); | |
325 | v |= (n - 1) << __ffs(dd->div1_mask); | |
358965d7 | 326 | |
a36795c1 JH |
327 | /* Configure dco and sd_div for dplls that have these fields */ |
328 | if (dd->dco_mask) { | |
329 | _lookup_dco(clk, &dco, m, n); | |
330 | v &= ~(dd->dco_mask); | |
331 | v |= dco << __ffs(dd->dco_mask); | |
332 | } | |
333 | if (dd->sddiv_mask) { | |
334 | _lookup_sddiv(clk, &sd_div, m, n); | |
335 | v &= ~(dd->sddiv_mask); | |
336 | v |= sd_div << __ffs(dd->sddiv_mask); | |
358965d7 RW |
337 | } |
338 | ||
60c3f651 PW |
339 | __raw_writel(v, dd->mult_div1_reg); |
340 | ||
341 | /* We let the clock framework set the other output dividers later */ | |
342 | ||
343 | /* REVISIT: Set ramp-up delay? */ | |
344 | ||
345 | _omap3_noncore_dpll_lock(clk); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | /* Public functions */ | |
351 | ||
352 | /** | |
353 | * omap3_dpll_recalc - recalculate DPLL rate | |
354 | * @clk: DPLL struct clk | |
355 | * | |
356 | * Recalculate and propagate the DPLL rate. | |
357 | */ | |
358 | unsigned long omap3_dpll_recalc(struct clk *clk) | |
359 | { | |
360 | return omap2_get_dpll_rate(clk); | |
361 | } | |
362 | ||
363 | /* Non-CORE DPLL (e.g., DPLLs that do not control SDRC) clock functions */ | |
364 | ||
a1391d27 RN |
365 | /** |
366 | * omap3_noncore_dpll_enable - instruct a DPLL to enter bypass or lock mode | |
367 | * @clk: pointer to a DPLL struct clk | |
368 | * | |
369 | * Instructs a non-CORE DPLL to enable, e.g., to enter bypass or lock. | |
370 | * The choice of modes depends on the DPLL's programmed rate: if it is | |
371 | * the same as the DPLL's parent clock, it will enter bypass; | |
372 | * otherwise, it will enter lock. This code will wait for the DPLL to | |
373 | * indicate readiness before returning, unless the DPLL takes too long | |
374 | * to enter the target state. Intended to be used as the struct clk's | |
375 | * enable function. If DPLL3 was passed in, or the DPLL does not | |
376 | * support low-power stop, or if the DPLL took too long to enter | |
377 | * bypass or lock, return -EINVAL; otherwise, return 0. | |
378 | */ | |
379 | int omap3_noncore_dpll_enable(struct clk *clk) | |
380 | { | |
381 | int r; | |
382 | struct dpll_data *dd; | |
383 | ||
384 | dd = clk->dpll_data; | |
385 | if (!dd) | |
386 | return -EINVAL; | |
387 | ||
388 | if (clk->rate == dd->clk_bypass->rate) { | |
389 | WARN_ON(clk->parent != dd->clk_bypass); | |
390 | r = _omap3_noncore_dpll_bypass(clk); | |
391 | } else { | |
392 | WARN_ON(clk->parent != dd->clk_ref); | |
393 | r = _omap3_noncore_dpll_lock(clk); | |
394 | } | |
395 | /* | |
396 | *FIXME: this is dubious - if clk->rate has changed, what about | |
397 | * propagating? | |
398 | */ | |
399 | if (!r) | |
49642ac8 JH |
400 | clk->rate = (clk->recalc) ? clk->recalc(clk) : |
401 | omap2_get_dpll_rate(clk); | |
a1391d27 RN |
402 | |
403 | return r; | |
404 | } | |
405 | ||
406 | /** | |
407 | * omap3_noncore_dpll_disable - instruct a DPLL to enter low-power stop | |
408 | * @clk: pointer to a DPLL struct clk | |
409 | * | |
410 | * Instructs a non-CORE DPLL to enter low-power stop. This function is | |
411 | * intended for use in struct clkops. No return value. | |
412 | */ | |
413 | void omap3_noncore_dpll_disable(struct clk *clk) | |
414 | { | |
415 | _omap3_noncore_dpll_stop(clk); | |
416 | } | |
417 | ||
418 | ||
419 | /* Non-CORE DPLL rate set code */ | |
420 | ||
a1391d27 RN |
421 | /** |
422 | * omap3_noncore_dpll_set_rate - set non-core DPLL rate | |
423 | * @clk: struct clk * of DPLL to set | |
424 | * @rate: rounded target rate | |
425 | * | |
426 | * Set the DPLL CLKOUT to the target rate. If the DPLL can enter | |
427 | * low-power bypass, and the target rate is the bypass source clock | |
428 | * rate, then configure the DPLL for bypass. Otherwise, round the | |
429 | * target rate if it hasn't been done already, then program and lock | |
430 | * the DPLL. Returns -EINVAL upon error, or 0 upon success. | |
431 | */ | |
432 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate) | |
433 | { | |
434 | struct clk *new_parent = NULL; | |
49642ac8 | 435 | unsigned long hw_rate; |
16975a79 | 436 | u16 freqsel = 0; |
a1391d27 RN |
437 | struct dpll_data *dd; |
438 | int ret; | |
439 | ||
440 | if (!clk || !rate) | |
441 | return -EINVAL; | |
442 | ||
443 | dd = clk->dpll_data; | |
444 | if (!dd) | |
445 | return -EINVAL; | |
446 | ||
49642ac8 JH |
447 | hw_rate = (clk->recalc) ? clk->recalc(clk) : omap2_get_dpll_rate(clk); |
448 | if (rate == hw_rate) | |
a1391d27 RN |
449 | return 0; |
450 | ||
451 | /* | |
452 | * Ensure both the bypass and ref clocks are enabled prior to | |
453 | * doing anything; we need the bypass clock running to reprogram | |
454 | * the DPLL. | |
455 | */ | |
456 | omap2_clk_enable(dd->clk_bypass); | |
457 | omap2_clk_enable(dd->clk_ref); | |
458 | ||
459 | if (dd->clk_bypass->rate == rate && | |
460 | (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) { | |
461 | pr_debug("clock: %s: set rate: entering bypass.\n", clk->name); | |
462 | ||
463 | ret = _omap3_noncore_dpll_bypass(clk); | |
464 | if (!ret) | |
465 | new_parent = dd->clk_bypass; | |
466 | } else { | |
467 | if (dd->last_rounded_rate != rate) | |
273a1ce9 | 468 | rate = clk->round_rate(clk, rate); |
a1391d27 RN |
469 | |
470 | if (dd->last_rounded_rate == 0) | |
471 | return -EINVAL; | |
472 | ||
5eb75f55 VB |
473 | /* No freqsel on OMAP4 and OMAP3630 */ |
474 | if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { | |
16975a79 RN |
475 | freqsel = _omap3_dpll_compute_freqsel(clk, |
476 | dd->last_rounded_n); | |
477 | if (!freqsel) | |
478 | WARN_ON(1); | |
479 | } | |
a1391d27 RN |
480 | |
481 | pr_debug("clock: %s: set rate: locking rate to %lu.\n", | |
482 | clk->name, rate); | |
483 | ||
484 | ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m, | |
485 | dd->last_rounded_n, freqsel); | |
486 | if (!ret) | |
487 | new_parent = dd->clk_ref; | |
488 | } | |
489 | if (!ret) { | |
490 | /* | |
732bee7a | 491 | * Switch the parent clock in the hierarchy, and make sure |
a1391d27 RN |
492 | * that the new parent's usecount is correct. Note: we |
493 | * enable the new parent before disabling the old to avoid | |
494 | * any unnecessary hardware disable->enable transitions. | |
495 | */ | |
496 | if (clk->usecount) { | |
497 | omap2_clk_enable(new_parent); | |
498 | omap2_clk_disable(clk->parent); | |
499 | } | |
500 | clk_reparent(clk, new_parent); | |
501 | clk->rate = rate; | |
502 | } | |
503 | omap2_clk_disable(dd->clk_ref); | |
504 | omap2_clk_disable(dd->clk_bypass); | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | /* DPLL autoidle read/set code */ | |
510 | ||
511 | /** | |
512 | * omap3_dpll_autoidle_read - read a DPLL's autoidle bits | |
513 | * @clk: struct clk * of the DPLL to read | |
514 | * | |
515 | * Return the DPLL's autoidle bits, shifted down to bit 0. Returns | |
516 | * -EINVAL if passed a null pointer or if the struct clk does not | |
517 | * appear to refer to a DPLL. | |
518 | */ | |
519 | u32 omap3_dpll_autoidle_read(struct clk *clk) | |
520 | { | |
521 | const struct dpll_data *dd; | |
522 | u32 v; | |
523 | ||
524 | if (!clk || !clk->dpll_data) | |
525 | return -EINVAL; | |
526 | ||
527 | dd = clk->dpll_data; | |
528 | ||
d76316fe VB |
529 | if (!dd->autoidle_reg) |
530 | return -EINVAL; | |
531 | ||
a1391d27 RN |
532 | v = __raw_readl(dd->autoidle_reg); |
533 | v &= dd->autoidle_mask; | |
534 | v >>= __ffs(dd->autoidle_mask); | |
535 | ||
536 | return v; | |
537 | } | |
538 | ||
539 | /** | |
540 | * omap3_dpll_allow_idle - enable DPLL autoidle bits | |
541 | * @clk: struct clk * of the DPLL to operate on | |
542 | * | |
543 | * Enable DPLL automatic idle control. This automatic idle mode | |
544 | * switching takes effect only when the DPLL is locked, at least on | |
545 | * OMAP3430. The DPLL will enter low-power stop when its downstream | |
546 | * clocks are gated. No return value. | |
547 | */ | |
548 | void omap3_dpll_allow_idle(struct clk *clk) | |
549 | { | |
550 | const struct dpll_data *dd; | |
551 | u32 v; | |
552 | ||
553 | if (!clk || !clk->dpll_data) | |
554 | return; | |
555 | ||
556 | dd = clk->dpll_data; | |
557 | ||
d76316fe VB |
558 | if (!dd->autoidle_reg) { |
559 | pr_debug("clock: DPLL %s: autoidle not supported\n", | |
560 | clk->name); | |
561 | return; | |
562 | } | |
563 | ||
a1391d27 RN |
564 | /* |
565 | * REVISIT: CORE DPLL can optionally enter low-power bypass | |
566 | * by writing 0x5 instead of 0x1. Add some mechanism to | |
567 | * optionally enter this mode. | |
568 | */ | |
569 | v = __raw_readl(dd->autoidle_reg); | |
570 | v &= ~dd->autoidle_mask; | |
571 | v |= DPLL_AUTOIDLE_LOW_POWER_STOP << __ffs(dd->autoidle_mask); | |
572 | __raw_writel(v, dd->autoidle_reg); | |
d76316fe | 573 | |
a1391d27 RN |
574 | } |
575 | ||
576 | /** | |
577 | * omap3_dpll_deny_idle - prevent DPLL from automatically idling | |
578 | * @clk: struct clk * of the DPLL to operate on | |
579 | * | |
580 | * Disable DPLL automatic idle control. No return value. | |
581 | */ | |
582 | void omap3_dpll_deny_idle(struct clk *clk) | |
583 | { | |
584 | const struct dpll_data *dd; | |
585 | u32 v; | |
586 | ||
587 | if (!clk || !clk->dpll_data) | |
588 | return; | |
589 | ||
590 | dd = clk->dpll_data; | |
591 | ||
d76316fe VB |
592 | if (!dd->autoidle_reg) { |
593 | pr_debug("clock: DPLL %s: autoidle not supported\n", | |
594 | clk->name); | |
595 | return; | |
596 | } | |
597 | ||
a1391d27 RN |
598 | v = __raw_readl(dd->autoidle_reg); |
599 | v &= ~dd->autoidle_mask; | |
600 | v |= DPLL_AUTOIDLE_DISABLE << __ffs(dd->autoidle_mask); | |
601 | __raw_writel(v, dd->autoidle_reg); | |
602 | ||
603 | } | |
604 | ||
605 | /* Clock control for DPLL outputs */ | |
606 | ||
607 | /** | |
608 | * omap3_clkoutx2_recalc - recalculate DPLL X2 output virtual clock rate | |
609 | * @clk: DPLL output struct clk | |
610 | * | |
611 | * Using parent clock DPLL data, look up DPLL state. If locked, set our | |
612 | * rate to the dpll_clk * 2; otherwise, just use dpll_clk. | |
613 | */ | |
614 | unsigned long omap3_clkoutx2_recalc(struct clk *clk) | |
615 | { | |
616 | const struct dpll_data *dd; | |
617 | unsigned long rate; | |
618 | u32 v; | |
619 | struct clk *pclk; | |
620 | ||
621 | /* Walk up the parents of clk, looking for a DPLL */ | |
622 | pclk = clk->parent; | |
623 | while (pclk && !pclk->dpll_data) | |
624 | pclk = pclk->parent; | |
625 | ||
626 | /* clk does not have a DPLL as a parent? */ | |
627 | WARN_ON(!pclk); | |
628 | ||
629 | dd = pclk->dpll_data; | |
630 | ||
631 | WARN_ON(!dd->enable_mask); | |
632 | ||
633 | v = __raw_readl(dd->control_reg) & dd->enable_mask; | |
634 | v >>= __ffs(dd->enable_mask); | |
358965d7 | 635 | if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE)) |
a1391d27 RN |
636 | rate = clk->parent->rate; |
637 | else | |
638 | rate = clk->parent->rate * 2; | |
639 | return rate; | |
640 | } | |
353cec46 VH |
641 | |
642 | /* OMAP3/4 non-CORE DPLL clkops */ | |
643 | ||
644 | const struct clkops clkops_omap3_noncore_dpll_ops = { | |
645 | .enable = omap3_noncore_dpll_enable, | |
646 | .disable = omap3_noncore_dpll_disable, | |
647 | .allow_idle = omap3_dpll_allow_idle, | |
648 | .deny_idle = omap3_dpll_deny_idle, | |
649 | }; | |
650 | ||
651 | const struct clkops clkops_omap3_core_dpll_ops = { | |
652 | .allow_idle = omap3_dpll_allow_idle, | |
653 | .deny_idle = omap3_dpll_deny_idle, | |
654 | }; |