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d5e7c864 LV |
1 | /* |
2 | * OMAP2PLUS DMA channel definitions | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
17 | */ | |
18 | ||
19 | #ifndef __OMAP2PLUS_DMA_CHANNEL_H | |
20 | #define __OMAP2PLUS_DMA_CHANNEL_H | |
21 | ||
22 | ||
23 | /* DMA channels for 24xx */ | |
24 | #define OMAP24XX_DMA_NO_DEVICE 0 | |
25 | #define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */ | |
26 | #define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */ | |
27 | #define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */ | |
28 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ | |
29 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ | |
30 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ | |
31 | #define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ | |
32 | #define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ | |
33 | #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ | |
34 | #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ | |
35 | #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ | |
36 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ | |
37 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ | |
38 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ | |
39 | #define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ | |
40 | #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ | |
41 | #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ | |
42 | #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ | |
43 | #define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ | |
44 | #define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ | |
45 | #define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ | |
46 | #define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ | |
47 | #define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ | |
48 | #define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ | |
49 | #define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ | |
50 | #define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ | |
51 | #define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ | |
52 | #define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ | |
53 | #define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ | |
54 | #define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ | |
55 | #define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ | |
56 | #define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ | |
57 | #define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ | |
58 | #define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ | |
59 | #define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ | |
60 | #define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ | |
61 | #define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ | |
62 | #define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ | |
63 | #define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ | |
64 | #define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ | |
65 | #define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ | |
66 | #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ | |
67 | #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ | |
68 | #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ | |
69 | #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ | |
70 | #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ | |
71 | #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ | |
72 | #define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ | |
73 | #define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ | |
74 | #define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ | |
75 | #define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ | |
76 | #define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ | |
77 | #define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ | |
78 | #define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ | |
79 | #define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ | |
80 | #define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ | |
81 | #define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ | |
82 | #define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ | |
83 | #define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ | |
84 | #define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ | |
85 | #define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ | |
86 | #define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ | |
87 | #define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ | |
88 | #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ | |
89 | #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ | |
90 | #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ | |
91 | #define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ | |
92 | #define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ | |
93 | #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ | |
94 | #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ | |
95 | #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ | |
96 | #define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ | |
97 | #define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ | |
98 | #define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ | |
99 | #define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ | |
100 | #define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ | |
101 | #define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ | |
102 | #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ | |
103 | #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ | |
104 | #define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ | |
105 | #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ | |
106 | #define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ | |
107 | #define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ | |
108 | #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ | |
109 | #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ | |
110 | #define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ | |
111 | #define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ | |
112 | #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ | |
113 | #define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ | |
114 | #define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ | |
115 | #define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ | |
116 | #define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ | |
117 | #define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ | |
118 | #define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ | |
119 | #define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ | |
120 | #define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ | |
121 | #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ | |
122 | #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ | |
123 | ||
124 | #define OMAP36XX_DMA_UART4_TX 81 /* S_DMA_80 */ | |
125 | #define OMAP36XX_DMA_UART4_RX 82 /* S_DMA_81 */ | |
126 | ||
127 | /* Only for AM35xx */ | |
128 | #define AM35XX_DMA_UART4_TX 54 | |
129 | #define AM35XX_DMA_UART4_RX 55 | |
130 | ||
131 | #endif /* __OMAP2PLUS_DMA_CHANNEL_H */ |