Commit | Line | Data |
---|---|---|
b7ee79ab SS |
1 | /* |
2 | * OMAP2plus display device setup / initialization. | |
3 | * | |
4 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * Senthilvadivu Guruswamy | |
6 | * Sumit Semwal | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
13 | * kind, whether express or implied; without even the implied warranty | |
14 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
d44b28c4 | 18 | #include <linux/string.h> |
b7ee79ab SS |
19 | #include <linux/kernel.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/io.h> | |
23 | #include <linux/clk.h> | |
24 | #include <linux/err.h> | |
deee6d53 | 25 | #include <linux/delay.h> |
b7ee79ab | 26 | |
a0b38cc4 | 27 | #include <video/omapdss.h> |
2a296c8f | 28 | #include "omap_hwmod.h" |
25c7d49e | 29 | #include "omap_device.h" |
1d5aef49 | 30 | #include "omap-pm.h" |
deee6d53 | 31 | #include "common.h" |
b7ee79ab | 32 | |
e4c060db | 33 | #include "soc.h" |
ee0839c2 | 34 | #include "iomap.h" |
ee9dfd82 | 35 | #include "mux.h" |
dc35835c | 36 | #include "control.h" |
b923d40d | 37 | #include "display.h" |
b13159af | 38 | #include "prm.h" |
b923d40d AT |
39 | |
40 | #define DISPC_CONTROL 0x0040 | |
41 | #define DISPC_CONTROL2 0x0238 | |
465698ee | 42 | #define DISPC_CONTROL3 0x0848 |
b923d40d AT |
43 | #define DISPC_IRQSTATUS 0x0018 |
44 | ||
45 | #define DSS_SYSCONFIG 0x10 | |
46 | #define DSS_SYSSTATUS 0x14 | |
47 | #define DSS_CONTROL 0x40 | |
48 | #define DSS_SDI_CONTROL 0x44 | |
49 | #define DSS_PLL_CONTROL 0x48 | |
50 | ||
51 | #define LCD_EN_MASK (0x1 << 0) | |
52 | #define DIGIT_EN_MASK (0x1 << 1) | |
53 | ||
54 | #define FRAMEDONE_IRQ_SHIFT 0 | |
55 | #define EVSYNC_EVEN_IRQ_SHIFT 2 | |
56 | #define EVSYNC_ODD_IRQ_SHIFT 3 | |
57 | #define FRAMEDONE2_IRQ_SHIFT 22 | |
465698ee | 58 | #define FRAMEDONE3_IRQ_SHIFT 30 |
b923d40d AT |
59 | #define FRAMEDONETV_IRQ_SHIFT 24 |
60 | ||
61 | /* | |
62 | * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC | |
63 | * reset before deciding that something has gone wrong | |
64 | */ | |
65 | #define FRAMEDONE_IRQ_TIMEOUT 100 | |
dc35835c | 66 | |
b7ee79ab SS |
67 | static struct platform_device omap_display_device = { |
68 | .name = "omapdss", | |
69 | .id = -1, | |
70 | .dev = { | |
71 | .platform_data = NULL, | |
72 | }, | |
73 | }; | |
74 | ||
179e0453 AT |
75 | struct omap_dss_hwmod_data { |
76 | const char *oh_name; | |
77 | const char *dev_name; | |
78 | const int id; | |
79 | }; | |
80 | ||
bcad6dc3 | 81 | static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = { |
179e0453 AT |
82 | { "dss_core", "omapdss_dss", -1 }, |
83 | { "dss_dispc", "omapdss_dispc", -1 }, | |
84 | { "dss_rfbi", "omapdss_rfbi", -1 }, | |
85 | { "dss_venc", "omapdss_venc", -1 }, | |
86 | }; | |
87 | ||
bcad6dc3 | 88 | static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = { |
179e0453 AT |
89 | { "dss_core", "omapdss_dss", -1 }, |
90 | { "dss_dispc", "omapdss_dispc", -1 }, | |
91 | { "dss_rfbi", "omapdss_rfbi", -1 }, | |
92 | { "dss_venc", "omapdss_venc", -1 }, | |
7c68dd96 | 93 | { "dss_dsi1", "omapdss_dsi", 0 }, |
179e0453 AT |
94 | }; |
95 | ||
bcad6dc3 | 96 | static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = { |
179e0453 AT |
97 | { "dss_core", "omapdss_dss", -1 }, |
98 | { "dss_dispc", "omapdss_dispc", -1 }, | |
99 | { "dss_rfbi", "omapdss_rfbi", -1 }, | |
7c68dd96 TV |
100 | { "dss_dsi1", "omapdss_dsi", 0 }, |
101 | { "dss_dsi2", "omapdss_dsi", 1 }, | |
179e0453 AT |
102 | { "dss_hdmi", "omapdss_hdmi", -1 }, |
103 | }; | |
104 | ||
ffc81fc5 | 105 | static void __init omap4_tpd12s015_mux_pads(void) |
ee9dfd82 | 106 | { |
ee9dfd82 M |
107 | omap_mux_init_signal("hdmi_cec", |
108 | OMAP_PIN_INPUT_PULLUP); | |
ee9dfd82 M |
109 | omap_mux_init_signal("hdmi_ddc_scl", |
110 | OMAP_PIN_INPUT_PULLUP); | |
111 | omap_mux_init_signal("hdmi_ddc_sda", | |
112 | OMAP_PIN_INPUT_PULLUP); | |
ffc81fc5 TV |
113 | } |
114 | ||
115 | static void __init omap4_hdmi_mux_pads(enum omap_hdmi_flags flags) | |
116 | { | |
117 | u32 reg; | |
118 | u16 control_i2c_1; | |
9a901683 M |
119 | |
120 | /* | |
121 | * CONTROL_I2C_1: HDMI_DDC_SDA_PULLUPRESX (bit 28) and | |
122 | * HDMI_DDC_SCL_PULLUPRESX (bit 24) are set to disable | |
123 | * internal pull up resistor. | |
124 | */ | |
125 | if (flags & OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP) { | |
126 | control_i2c_1 = OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1; | |
127 | reg = omap4_ctrl_pad_readl(control_i2c_1); | |
128 | reg |= (OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK | | |
129 | OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK); | |
130 | omap4_ctrl_pad_writel(reg, control_i2c_1); | |
131 | } | |
ee9dfd82 M |
132 | } |
133 | ||
e8a30b25 | 134 | static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes) |
dc35835c TV |
135 | { |
136 | u32 enable_mask, enable_shift; | |
137 | u32 pipd_mask, pipd_shift; | |
138 | u32 reg; | |
139 | ||
140 | if (dsi_id == 0) { | |
141 | enable_mask = OMAP4_DSI1_LANEENABLE_MASK; | |
142 | enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; | |
143 | pipd_mask = OMAP4_DSI1_PIPD_MASK; | |
144 | pipd_shift = OMAP4_DSI1_PIPD_SHIFT; | |
145 | } else if (dsi_id == 1) { | |
146 | enable_mask = OMAP4_DSI2_LANEENABLE_MASK; | |
147 | enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; | |
148 | pipd_mask = OMAP4_DSI2_PIPD_MASK; | |
149 | pipd_shift = OMAP4_DSI2_PIPD_SHIFT; | |
150 | } else { | |
151 | return -ENODEV; | |
152 | } | |
153 | ||
154 | reg = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); | |
155 | ||
156 | reg &= ~enable_mask; | |
157 | reg &= ~pipd_mask; | |
158 | ||
159 | reg |= (lanes << enable_shift) & enable_mask; | |
160 | reg |= (lanes << pipd_shift) & pipd_mask; | |
161 | ||
162 | omap4_ctrl_pad_writel(reg, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY); | |
163 | ||
164 | return 0; | |
165 | } | |
166 | ||
d1589f09 | 167 | int __init omap_hdmi_init(enum omap_hdmi_flags flags) |
ee9dfd82 | 168 | { |
ffc81fc5 | 169 | if (cpu_is_omap44xx()) { |
9a901683 | 170 | omap4_hdmi_mux_pads(flags); |
ffc81fc5 TV |
171 | omap4_tpd12s015_mux_pads(); |
172 | } | |
ee9dfd82 M |
173 | |
174 | return 0; | |
175 | } | |
176 | ||
e8a30b25 | 177 | static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask) |
5bc416cb | 178 | { |
dc35835c TV |
179 | if (cpu_is_omap44xx()) |
180 | return omap4_dsi_mux_pads(dsi_id, lane_mask); | |
181 | ||
5bc416cb TV |
182 | return 0; |
183 | } | |
184 | ||
e8a30b25 | 185 | static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask) |
5bc416cb | 186 | { |
dc35835c TV |
187 | if (cpu_is_omap44xx()) |
188 | omap4_dsi_mux_pads(dsi_id, 0); | |
5bc416cb TV |
189 | } |
190 | ||
62c1dcfc TV |
191 | static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput) |
192 | { | |
193 | return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput); | |
194 | } | |
195 | ||
966eaed0 TV |
196 | static struct platform_device *create_dss_pdev(const char *pdev_name, |
197 | int pdev_id, const char *oh_name, void *pdata, int pdata_len, | |
198 | struct platform_device *parent) | |
199 | { | |
200 | struct platform_device *pdev; | |
201 | struct omap_device *od; | |
202 | struct omap_hwmod *ohs[1]; | |
203 | struct omap_hwmod *oh; | |
204 | int r; | |
205 | ||
206 | oh = omap_hwmod_lookup(oh_name); | |
207 | if (!oh) { | |
208 | pr_err("Could not look up %s\n", oh_name); | |
209 | r = -ENODEV; | |
210 | goto err; | |
211 | } | |
212 | ||
213 | pdev = platform_device_alloc(pdev_name, pdev_id); | |
214 | if (!pdev) { | |
215 | pr_err("Could not create pdev for %s\n", pdev_name); | |
216 | r = -ENOMEM; | |
217 | goto err; | |
218 | } | |
219 | ||
220 | if (parent != NULL) | |
221 | pdev->dev.parent = &parent->dev; | |
222 | ||
223 | if (pdev->id != -1) | |
224 | dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); | |
225 | else | |
226 | dev_set_name(&pdev->dev, "%s", pdev->name); | |
227 | ||
228 | ohs[0] = oh; | |
c1d1cd59 | 229 | od = omap_device_alloc(pdev, ohs, 1); |
9ee67723 | 230 | if (IS_ERR(od)) { |
966eaed0 TV |
231 | pr_err("Could not alloc omap_device for %s\n", pdev_name); |
232 | r = -ENOMEM; | |
233 | goto err; | |
234 | } | |
235 | ||
236 | r = platform_device_add_data(pdev, pdata, pdata_len); | |
237 | if (r) { | |
238 | pr_err("Could not set pdata for %s\n", pdev_name); | |
239 | goto err; | |
240 | } | |
241 | ||
242 | r = omap_device_register(pdev); | |
243 | if (r) { | |
244 | pr_err("Could not register omap_device for %s\n", pdev_name); | |
245 | goto err; | |
246 | } | |
247 | ||
248 | return pdev; | |
249 | ||
250 | err: | |
251 | return ERR_PTR(r); | |
252 | } | |
253 | ||
53f576a8 TV |
254 | static struct platform_device *create_simple_dss_pdev(const char *pdev_name, |
255 | int pdev_id, void *pdata, int pdata_len, | |
256 | struct platform_device *parent) | |
257 | { | |
258 | struct platform_device *pdev; | |
259 | int r; | |
260 | ||
261 | pdev = platform_device_alloc(pdev_name, pdev_id); | |
262 | if (!pdev) { | |
263 | pr_err("Could not create pdev for %s\n", pdev_name); | |
264 | r = -ENOMEM; | |
265 | goto err; | |
266 | } | |
267 | ||
268 | if (parent != NULL) | |
269 | pdev->dev.parent = &parent->dev; | |
270 | ||
271 | if (pdev->id != -1) | |
272 | dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id); | |
273 | else | |
274 | dev_set_name(&pdev->dev, "%s", pdev->name); | |
275 | ||
276 | r = platform_device_add_data(pdev, pdata, pdata_len); | |
277 | if (r) { | |
278 | pr_err("Could not set pdata for %s\n", pdev_name); | |
279 | goto err; | |
280 | } | |
281 | ||
c3a21fc7 | 282 | r = platform_device_add(pdev); |
53f576a8 | 283 | if (r) { |
c3a21fc7 | 284 | pr_err("Could not register platform_device for %s\n", pdev_name); |
53f576a8 TV |
285 | goto err; |
286 | } | |
287 | ||
288 | return pdev; | |
289 | ||
290 | err: | |
291 | return ERR_PTR(r); | |
292 | } | |
293 | ||
acd18af9 TV |
294 | static enum omapdss_version __init omap_display_get_version(void) |
295 | { | |
296 | if (cpu_is_omap24xx()) | |
297 | return OMAPDSS_VER_OMAP24xx; | |
298 | else if (cpu_is_omap3630()) | |
299 | return OMAPDSS_VER_OMAP3630; | |
300 | else if (cpu_is_omap34xx()) { | |
301 | if (soc_is_am35xx()) { | |
302 | return OMAPDSS_VER_AM35xx; | |
303 | } else { | |
304 | if (omap_rev() < OMAP3430_REV_ES3_0) | |
305 | return OMAPDSS_VER_OMAP34xx_ES1; | |
306 | else | |
307 | return OMAPDSS_VER_OMAP34xx_ES3; | |
308 | } | |
309 | } else if (omap_rev() == OMAP4430_REV_ES1_0) | |
310 | return OMAPDSS_VER_OMAP4430_ES1; | |
311 | else if (omap_rev() == OMAP4430_REV_ES2_0 || | |
312 | omap_rev() == OMAP4430_REV_ES2_1 || | |
313 | omap_rev() == OMAP4430_REV_ES2_2) | |
314 | return OMAPDSS_VER_OMAP4430_ES2; | |
315 | else if (cpu_is_omap44xx()) | |
316 | return OMAPDSS_VER_OMAP4; | |
317 | else if (soc_is_omap54xx()) | |
318 | return OMAPDSS_VER_OMAP5; | |
319 | else | |
320 | return OMAPDSS_VER_UNKNOWN; | |
321 | } | |
322 | ||
b7ee79ab SS |
323 | int __init omap_display_init(struct omap_dss_board_info *board_data) |
324 | { | |
325 | int r = 0; | |
3528c58e | 326 | struct platform_device *pdev; |
179e0453 | 327 | int i, oh_count; |
179e0453 | 328 | const struct omap_dss_hwmod_data *curr_dss_hwmod; |
966eaed0 | 329 | struct platform_device *dss_pdev; |
acd18af9 | 330 | enum omapdss_version ver; |
cf07f531 | 331 | |
00928eaf TV |
332 | /* create omapdss device */ |
333 | ||
acd18af9 TV |
334 | ver = omap_display_get_version(); |
335 | ||
336 | if (ver == OMAPDSS_VER_UNKNOWN) { | |
337 | pr_err("DSS not supported on this SoC\n"); | |
338 | return -ENODEV; | |
339 | } | |
340 | ||
341 | board_data->version = ver; | |
00928eaf TV |
342 | board_data->dsi_enable_pads = omap_dsi_enable_pads; |
343 | board_data->dsi_disable_pads = omap_dsi_disable_pads; | |
344 | board_data->get_context_loss_count = omap_pm_get_dev_context_loss_count; | |
345 | board_data->set_min_bus_tput = omap_dss_set_min_bus_tput; | |
346 | ||
347 | omap_display_device.dev.platform_data = board_data; | |
348 | ||
349 | r = platform_device_register(&omap_display_device); | |
350 | if (r < 0) { | |
351 | pr_err("Unable to register omapdss device\n"); | |
352 | return r; | |
353 | } | |
354 | ||
355 | /* create devices for dss hwmods */ | |
cf07f531 | 356 | |
179e0453 AT |
357 | if (cpu_is_omap24xx()) { |
358 | curr_dss_hwmod = omap2_dss_hwmod_data; | |
359 | oh_count = ARRAY_SIZE(omap2_dss_hwmod_data); | |
360 | } else if (cpu_is_omap34xx()) { | |
361 | curr_dss_hwmod = omap3_dss_hwmod_data; | |
362 | oh_count = ARRAY_SIZE(omap3_dss_hwmod_data); | |
363 | } else { | |
364 | curr_dss_hwmod = omap4_dss_hwmod_data; | |
365 | oh_count = ARRAY_SIZE(omap4_dss_hwmod_data); | |
366 | } | |
545376e7 | 367 | |
966eaed0 TV |
368 | /* |
369 | * First create the pdev for dss_core, which is used as a parent device | |
370 | * by the other dss pdevs. Note: dss_core has to be the first item in | |
371 | * the hwmod list. | |
372 | */ | |
373 | dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name, | |
374 | curr_dss_hwmod[0].id, | |
375 | curr_dss_hwmod[0].oh_name, | |
35deca3d | 376 | board_data, sizeof(*board_data), |
966eaed0 | 377 | NULL); |
fd4b34f6 | 378 | |
966eaed0 TV |
379 | if (IS_ERR(dss_pdev)) { |
380 | pr_err("Could not build omap_device for %s\n", | |
381 | curr_dss_hwmod[0].oh_name); | |
382 | ||
383 | return PTR_ERR(dss_pdev); | |
384 | } | |
385 | ||
386 | for (i = 1; i < oh_count; i++) { | |
387 | pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name, | |
388 | curr_dss_hwmod[i].id, | |
389 | curr_dss_hwmod[i].oh_name, | |
35deca3d | 390 | board_data, sizeof(*board_data), |
966eaed0 TV |
391 | dss_pdev); |
392 | ||
393 | if (IS_ERR(pdev)) { | |
394 | pr_err("Could not build omap_device for %s\n", | |
395 | curr_dss_hwmod[i].oh_name); | |
cf07f531 | 396 | |
966eaed0 TV |
397 | return PTR_ERR(pdev); |
398 | } | |
cf07f531 | 399 | } |
b7ee79ab | 400 | |
53f576a8 TV |
401 | /* Create devices for DPI and SDI */ |
402 | ||
35deca3d TV |
403 | pdev = create_simple_dss_pdev("omapdss_dpi", -1, |
404 | board_data, sizeof(*board_data), dss_pdev); | |
53f576a8 TV |
405 | if (IS_ERR(pdev)) { |
406 | pr_err("Could not build platform_device for omapdss_dpi\n"); | |
407 | return PTR_ERR(pdev); | |
408 | } | |
409 | ||
410 | if (cpu_is_omap34xx()) { | |
35deca3d TV |
411 | pdev = create_simple_dss_pdev("omapdss_sdi", -1, |
412 | board_data, sizeof(*board_data), dss_pdev); | |
53f576a8 TV |
413 | if (IS_ERR(pdev)) { |
414 | pr_err("Could not build platform_device for omapdss_sdi\n"); | |
415 | return PTR_ERR(pdev); | |
416 | } | |
417 | } | |
418 | ||
00928eaf | 419 | return 0; |
b7ee79ab | 420 | } |
13662dc5 | 421 | |
b923d40d AT |
422 | static void dispc_disable_outputs(void) |
423 | { | |
424 | u32 v, irq_mask = 0; | |
465698ee | 425 | bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false; |
b923d40d AT |
426 | int i; |
427 | struct omap_dss_dispc_dev_attr *da; | |
428 | struct omap_hwmod *oh; | |
429 | ||
430 | oh = omap_hwmod_lookup("dss_dispc"); | |
431 | if (!oh) { | |
432 | WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n"); | |
433 | return; | |
434 | } | |
435 | ||
436 | if (!oh->dev_attr) { | |
437 | pr_err("display: could not disable outputs during reset due to missing dev_attr\n"); | |
438 | return; | |
439 | } | |
440 | ||
441 | da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr; | |
442 | ||
443 | /* store value of LCDENABLE and DIGITENABLE bits */ | |
444 | v = omap_hwmod_read(oh, DISPC_CONTROL); | |
445 | lcd_en = v & LCD_EN_MASK; | |
446 | digit_en = v & DIGIT_EN_MASK; | |
447 | ||
448 | /* store value of LCDENABLE for LCD2 */ | |
449 | if (da->manager_count > 2) { | |
450 | v = omap_hwmod_read(oh, DISPC_CONTROL2); | |
451 | lcd2_en = v & LCD_EN_MASK; | |
452 | } | |
453 | ||
465698ee CM |
454 | /* store value of LCDENABLE for LCD3 */ |
455 | if (da->manager_count > 3) { | |
456 | v = omap_hwmod_read(oh, DISPC_CONTROL3); | |
457 | lcd3_en = v & LCD_EN_MASK; | |
458 | } | |
459 | ||
460 | if (!(lcd_en | digit_en | lcd2_en | lcd3_en)) | |
b923d40d AT |
461 | return; /* no managers currently enabled */ |
462 | ||
463 | /* | |
464 | * If any manager was enabled, we need to disable it before | |
465 | * DSS clocks are disabled or DISPC module is reset | |
466 | */ | |
467 | if (lcd_en) | |
468 | irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT; | |
469 | ||
470 | if (digit_en) { | |
471 | if (da->has_framedonetv_irq) { | |
472 | irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT; | |
473 | } else { | |
474 | irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT | | |
475 | 1 << EVSYNC_ODD_IRQ_SHIFT; | |
476 | } | |
477 | } | |
478 | ||
479 | if (lcd2_en) | |
480 | irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT; | |
465698ee CM |
481 | if (lcd3_en) |
482 | irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT; | |
b923d40d AT |
483 | |
484 | /* | |
485 | * clear any previous FRAMEDONE, FRAMEDONETV, | |
465698ee | 486 | * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts |
b923d40d AT |
487 | */ |
488 | omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS); | |
489 | ||
490 | /* disable LCD and TV managers */ | |
491 | v = omap_hwmod_read(oh, DISPC_CONTROL); | |
492 | v &= ~(LCD_EN_MASK | DIGIT_EN_MASK); | |
493 | omap_hwmod_write(v, oh, DISPC_CONTROL); | |
494 | ||
495 | /* disable LCD2 manager */ | |
496 | if (da->manager_count > 2) { | |
497 | v = omap_hwmod_read(oh, DISPC_CONTROL2); | |
498 | v &= ~LCD_EN_MASK; | |
499 | omap_hwmod_write(v, oh, DISPC_CONTROL2); | |
500 | } | |
501 | ||
465698ee CM |
502 | /* disable LCD3 manager */ |
503 | if (da->manager_count > 3) { | |
504 | v = omap_hwmod_read(oh, DISPC_CONTROL3); | |
505 | v &= ~LCD_EN_MASK; | |
506 | omap_hwmod_write(v, oh, DISPC_CONTROL3); | |
507 | } | |
508 | ||
b923d40d AT |
509 | i = 0; |
510 | while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) != | |
511 | irq_mask) { | |
512 | i++; | |
513 | if (i > FRAMEDONE_IRQ_TIMEOUT) { | |
465698ee | 514 | pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n"); |
b923d40d AT |
515 | break; |
516 | } | |
517 | mdelay(1); | |
518 | } | |
519 | } | |
520 | ||
13662dc5 TV |
521 | int omap_dss_reset(struct omap_hwmod *oh) |
522 | { | |
523 | struct omap_hwmod_opt_clk *oc; | |
524 | int c = 0; | |
525 | int i, r; | |
526 | ||
527 | if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) { | |
528 | pr_err("dss_core: hwmod data doesn't contain reset data\n"); | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
533 | if (oc->_clk) | |
4d7cb45e | 534 | clk_prepare_enable(oc->_clk); |
13662dc5 | 535 | |
b923d40d AT |
536 | dispc_disable_outputs(); |
537 | ||
538 | /* clear SDI registers */ | |
539 | if (cpu_is_omap3430()) { | |
540 | omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL); | |
541 | omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL); | |
542 | } | |
543 | ||
544 | /* | |
545 | * clear DSS_CONTROL register to switch DSS clock sources to | |
546 | * PRCM clock, if any | |
547 | */ | |
548 | omap_hwmod_write(0x0, oh, DSS_CONTROL); | |
549 | ||
13662dc5 TV |
550 | omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs) |
551 | & SYSS_RESETDONE_MASK), | |
552 | MAX_MODULE_SOFTRESET_WAIT, c); | |
553 | ||
554 | if (c == MAX_MODULE_SOFTRESET_WAIT) | |
555 | pr_warning("dss_core: waiting for reset to finish failed\n"); | |
556 | else | |
557 | pr_debug("dss_core: softreset done\n"); | |
558 | ||
559 | for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) | |
560 | if (oc->_clk) | |
4d7cb45e | 561 | clk_disable_unprepare(oc->_clk); |
13662dc5 TV |
562 | |
563 | r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0; | |
564 | ||
565 | return r; | |
566 | } |