[linux-2.6-block.git] / arch / arm / mach-omap2 / display.c

/*
 * OMAP2plus display device setup / initialization.
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 *	Senthilvadivu Guruswamy
 *	Sumit Semwal
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/slab.h>
#include <linux/mfd/syscon.h>
#include <linux/regmap.h>

#include <linux/platform_data/omapdss.h>
#include "omap_hwmod.h"
#include "omap_device.h"
#include "omap-pm.h"
#include "common.h"

#include "soc.h"
#include "iomap.h"
#include "control.h"
#include "display.h"
#include "prm.h"

#define DISPC_CONTROL		0x0040
#define DISPC_CONTROL2		0x0238
#define DISPC_CONTROL3		0x0848
#define DISPC_IRQSTATUS		0x0018

#define DSS_CONTROL		0x40
#define DSS_SDI_CONTROL		0x44
#define DSS_PLL_CONTROL		0x48

#define LCD_EN_MASK		(0x1 << 0)
#define DIGIT_EN_MASK		(0x1 << 1)

#define FRAMEDONE_IRQ_SHIFT	0
#define EVSYNC_EVEN_IRQ_SHIFT	2
#define EVSYNC_ODD_IRQ_SHIFT	3
#define FRAMEDONE2_IRQ_SHIFT	22
#define FRAMEDONE3_IRQ_SHIFT	30
#define FRAMEDONETV_IRQ_SHIFT	24

/*
 * FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
 *     reset before deciding that something has gone wrong
 */
#define FRAMEDONE_IRQ_TIMEOUT		100

static struct platform_device omap_display_device = {
	.name          = "omapdss",
	.id            = -1,
	.dev            = {
		.platform_data = NULL,
	},
};

#define OMAP4_DSIPHY_SYSCON_OFFSET		0x78

static struct regmap *omap4_dsi_mux_syscon;

static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
{
	u32 enable_mask, enable_shift;
	u32 pipd_mask, pipd_shift;
	u32 reg;

	if (dsi_id == 0) {
		enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI1_PIPD_MASK;
		pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	} else if (dsi_id == 1) {
		enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
		enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
		pipd_mask = OMAP4_DSI2_PIPD_MASK;
		pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	} else {
		return -ENODEV;
	}

	regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);

	reg &= ~enable_mask;
	reg &= ~pipd_mask;

	reg |= (lanes << enable_shift) & enable_mask;
	reg |= (lanes << pipd_shift) & pipd_mask;

	regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);

	return 0;
}

static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		return omap4_dsi_mux_pads(dsi_id, lane_mask);

	return 0;
}

static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
{
	if (cpu_is_omap44xx())
		omap4_dsi_mux_pads(dsi_id, 0);
}

static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
{
	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}

static enum omapdss_version __init omap_display_get_version(void)
{
	if (cpu_is_omap24xx())
		return OMAPDSS_VER_OMAP24xx;
	else if (cpu_is_omap3630())
		return OMAPDSS_VER_OMAP3630;
	else if (cpu_is_omap34xx()) {
		if (soc_is_am35xx()) {
			return OMAPDSS_VER_AM35xx;
		} else {
			if (omap_rev() < OMAP3430_REV_ES3_0)
				return OMAPDSS_VER_OMAP34xx_ES1;
			else
				return OMAPDSS_VER_OMAP34xx_ES3;
		}
	} else if (omap_rev() == OMAP4430_REV_ES1_0)
		return OMAPDSS_VER_OMAP4430_ES1;
	else if (omap_rev() == OMAP4430_REV_ES2_0 ||
			omap_rev() == OMAP4430_REV_ES2_1 ||
			omap_rev() == OMAP4430_REV_ES2_2)
		return OMAPDSS_VER_OMAP4430_ES2;
	else if (cpu_is_omap44xx())
		return OMAPDSS_VER_OMAP4;
	else if (soc_is_omap54xx())
		return OMAPDSS_VER_OMAP5;
	else if (soc_is_am43xx())
		return OMAPDSS_VER_AM43xx;
	else if (soc_is_dra7xx())
		return OMAPDSS_VER_DRA7xx;
	else
		return OMAPDSS_VER_UNKNOWN;
}

static void dispc_disable_outputs(void)
{
	u32 v, irq_mask = 0;
	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
	int i;
	struct omap_dss_dispc_dev_attr *da;
	struct omap_hwmod *oh;

	oh = omap_hwmod_lookup("dss_dispc");
	if (!oh) {
		WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
		return;
	}

	if (!oh->dev_attr) {
		pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
		return;
	}

	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;

	/* store value of LCDENABLE and DIGITENABLE bits */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	lcd_en = v & LCD_EN_MASK;
	digit_en = v & DIGIT_EN_MASK;

	/* store value of LCDENABLE for LCD2 */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		lcd2_en = v & LCD_EN_MASK;
	}

	/* store value of LCDENABLE for LCD3 */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		lcd3_en = v & LCD_EN_MASK;
	}

	if (!(lcd_en | digit_en | lcd2_en | lcd3_en))
		return; /* no managers currently enabled */

	/*
	 * If any manager was enabled, we need to disable it before
	 * DSS clocks are disabled or DISPC module is reset
	 */
	if (lcd_en)
		irq_mask |= 1 << FRAMEDONE_IRQ_SHIFT;

	if (digit_en) {
		if (da->has_framedonetv_irq) {
			irq_mask |= 1 << FRAMEDONETV_IRQ_SHIFT;
		} else {
			irq_mask |= 1 << EVSYNC_EVEN_IRQ_SHIFT |
				1 << EVSYNC_ODD_IRQ_SHIFT;
		}
	}

	if (lcd2_en)
		irq_mask |= 1 << FRAMEDONE2_IRQ_SHIFT;
	if (lcd3_en)
		irq_mask |= 1 << FRAMEDONE3_IRQ_SHIFT;

	/*
	 * clear any previous FRAMEDONE, FRAMEDONETV,
	 * EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
	 */
	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);

	/* disable LCD and TV managers */
	v = omap_hwmod_read(oh, DISPC_CONTROL);
	v &= ~(LCD_EN_MASK | DIGIT_EN_MASK);
	omap_hwmod_write(v, oh, DISPC_CONTROL);

	/* disable LCD2 manager */
	if (da->manager_count > 2) {
		v = omap_hwmod_read(oh, DISPC_CONTROL2);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL2);
	}

	/* disable LCD3 manager */
	if (da->manager_count > 3) {
		v = omap_hwmod_read(oh, DISPC_CONTROL3);
		v &= ~LCD_EN_MASK;
		omap_hwmod_write(v, oh, DISPC_CONTROL3);
	}

	i = 0;
	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	       irq_mask) {
		i++;
		if (i > FRAMEDONE_IRQ_TIMEOUT) {
			pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
			break;
		}
		mdelay(1);
	}
}

int omap_dss_reset(struct omap_hwmod *oh)
{
	struct omap_hwmod_opt_clk *oc;
	int c = 0;
	int i, r;

	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
		pr_err("dss_core: hwmod data doesn't contain reset data\n");
		return -EINVAL;
	}

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_prepare_enable(oc->_clk);

	dispc_disable_outputs();

	/* clear SDI registers */
	if (cpu_is_omap3430()) {
		omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
		omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	}

	/*
	 * clear DSS_CONTROL register to switch DSS clock sources to
	 * PRCM clock, if any
	 */
	omap_hwmod_write(0x0, oh, DSS_CONTROL);

	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
				& SYSS_RESETDONE_MASK),
			MAX_MODULE_SOFTRESET_WAIT, c);

	if (c == MAX_MODULE_SOFTRESET_WAIT)
		pr_warn("dss_core: waiting for reset to finish failed\n");
	else
		pr_debug("dss_core: softreset done\n");

	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
		if (oc->_clk)
			clk_disable_unprepare(oc->_clk);

	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;

	return r;
}

static const char * const omapdss_compat_names[] __initconst = {
	"ti,omap2-dss",
	"ti,omap3-dss",
	"ti,omap4-dss",
	"ti,omap5-dss",
	"ti,dra7-dss",
};

static struct device_node * __init omapdss_find_dss_of_node(void)
{
	struct device_node *node;
	int i;

	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
		node = of_find_compatible_node(NULL, NULL,
			omapdss_compat_names[i]);
		if (node)
			return node;
	}

	return NULL;
}

int __init omapdss_init_of(void)
{
	int r;
	enum omapdss_version ver;
	struct device_node *node;
	struct platform_device *pdev;

	static struct omap_dss_board_info board_data = {
		.dsi_enable_pads = omap_dsi_enable_pads,
		.dsi_disable_pads = omap_dsi_disable_pads,
		.set_min_bus_tput = omap_dss_set_min_bus_tput,
	};

	/* only create dss helper devices if dss is enabled in the .dts */

	node = omapdss_find_dss_of_node();
	if (!node)
		return 0;

	if (!of_device_is_available(node))
		return 0;

	ver = omap_display_get_version();

	if (ver == OMAPDSS_VER_UNKNOWN) {
		pr_err("DSS not supported on this SoC\n");
		return -ENODEV;
	}

	pdev = of_find_device_by_node(node);

	if (!pdev) {
		pr_err("Unable to find DSS platform device\n");
		return -ENODEV;
	}

	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
	if (r) {
		pr_err("Unable to populate DSS submodule devices\n");
		return r;
	}

	board_data.version = ver;

	omap_display_device.dev.platform_data = &board_data;

	r = platform_device_register(&omap_display_device);
	if (r < 0) {
		pr_err("Unable to register omapdss device\n");
		return r;
	}

	/* create DRM device */
	r = omap_init_drm();
	if (r < 0) {
		pr_err("Unable to register omapdrm device\n");
		return r;
	}

	/* create vrfb device */
	r = omap_init_vrfb();
	if (r < 0) {
		pr_err("Unable to register omapvrfb device\n");
		return r;
	}

	/* create FB device */
	r = omap_init_fb();
	if (r < 0) {
		pr_err("Unable to register omapfb device\n");
		return r;
	}

	/* create V4L2 display device */
	r = omap_init_vout();
	if (r < 0) {
		pr_err("Unable to register omap_vout device\n");
		return r;
	}

	/* add DSI info for omap4 */
	node = of_find_node_by_name(NULL, "omap4_padconf_global");
	if (node)
		omap4_dsi_mux_syscon = syscon_node_to_regmap(node);

	return 0;
}
Commit	Line	Data
b7ee79ab SS	1	/*
	2	* OMAP2plus display device setup / initialization.
	3	*
	4	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	5	* Senthilvadivu Guruswamy
	6	* Sumit Semwal
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
d44b28c4	18	#include <linux/string.h>
b7ee79ab SS	19	#include <linux/kernel.h>
	20	#include <linux/init.h>
	21	#include <linux/platform_device.h>
	22	#include <linux/io.h>
	23	#include <linux/clk.h>
	24	#include <linux/err.h>
deee6d53	25	#include <linux/delay.h>
dcdf407b TV	26	#include <linux/of.h>
dcdf407b TV	27	#include <linux/of_platform.h>
6a0e6b38	28	#include <linux/slab.h>
23d34981 TK	29	#include <linux/mfd/syscon.h>
23d34981 TK	30	#include <linux/regmap.h>
b7ee79ab	31
f8e0db97	32	#include <linux/platform_data/omapdss.h>
2a296c8f	33	#include "omap_hwmod.h"
25c7d49e	34	#include "omap_device.h"
1d5aef49	35	#include "omap-pm.h"
deee6d53	36	#include "common.h"
b7ee79ab	37
e4c060db	38	#include "soc.h"
ee0839c2	39	#include "iomap.h"
dc35835c	40	#include "control.h"
b923d40d	41	#include "display.h"
b13159af	42	#include "prm.h"
b923d40d AT	43
	44	#define DISPC_CONTROL 0x0040
	45	#define DISPC_CONTROL2 0x0238
465698ee	46	#define DISPC_CONTROL3 0x0848
b923d40d AT	47	#define DISPC_IRQSTATUS 0x0018
b923d40d AT	48
b923d40d AT	49	#define DSS_CONTROL 0x40
	50	#define DSS_SDI_CONTROL 0x44
	51	#define DSS_PLL_CONTROL 0x48
	52
	53	#define LCD_EN_MASK (0x1 << 0)
	54	#define DIGIT_EN_MASK (0x1 << 1)
	55
	56	#define FRAMEDONE_IRQ_SHIFT 0
	57	#define EVSYNC_EVEN_IRQ_SHIFT 2
	58	#define EVSYNC_ODD_IRQ_SHIFT 3
	59	#define FRAMEDONE2_IRQ_SHIFT 22
465698ee	60	#define FRAMEDONE3_IRQ_SHIFT 30
b923d40d AT	61	#define FRAMEDONETV_IRQ_SHIFT 24
	62
	63	/*
	64	* FRAMEDONE_IRQ_TIMEOUT: how long (in milliseconds) to wait during DISPC
	65	* reset before deciding that something has gone wrong
	66	*/
	67	#define FRAMEDONE_IRQ_TIMEOUT 100
dc35835c	68
b7ee79ab SS	69	static struct platform_device omap_display_device = {
	70	.name = "omapdss",
	71	.id = -1,
	72	.dev = {
	73	.platform_data = NULL,
	74	},
	75	};
	76
23d34981 TK	77	#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
	78
	79	static struct regmap *omap4_dsi_mux_syscon;
	80
130f769e TV	81	static int omap4_dsi_mux_pads(int dsi_id, unsigned lanes)
	82	{
	83	u32 enable_mask, enable_shift;
	84	u32 pipd_mask, pipd_shift;
	85	u32 reg;
	86
	87	if (dsi_id == 0) {
	88	enable_mask = OMAP4_DSI1_LANEENABLE_MASK;
	89	enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT;
	90	pipd_mask = OMAP4_DSI1_PIPD_MASK;
	91	pipd_shift = OMAP4_DSI1_PIPD_SHIFT;
	92	} else if (dsi_id == 1) {
	93	enable_mask = OMAP4_DSI2_LANEENABLE_MASK;
	94	enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT;
	95	pipd_mask = OMAP4_DSI2_PIPD_MASK;
	96	pipd_shift = OMAP4_DSI2_PIPD_SHIFT;
	97	} else {
	98	return -ENODEV;
	99	}
	100
23d34981	101	regmap_read(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, &reg);
130f769e TV	102
	103	reg &= ~enable_mask;
	104	reg &= ~pipd_mask;
	105
	106	reg \|= (lanes << enable_shift) & enable_mask;
	107	reg \|= (lanes << pipd_shift) & pipd_mask;
	108
23d34981	109	regmap_write(omap4_dsi_mux_syscon, OMAP4_DSIPHY_SYSCON_OFFSET, reg);
130f769e TV	110
	111	return 0;
	112	}
	113
e8a30b25	114	static int omap_dsi_enable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	115	{
130f769e TV	116	if (cpu_is_omap44xx())
	117	return omap4_dsi_mux_pads(dsi_id, lane_mask);
	118
5bc416cb TV	119	return 0;
	120	}
	121
e8a30b25	122	static void omap_dsi_disable_pads(int dsi_id, unsigned lane_mask)
5bc416cb	123	{
130f769e TV	124	if (cpu_is_omap44xx())
130f769e TV	125	omap4_dsi_mux_pads(dsi_id, 0);
5bc416cb TV	126	}
5bc416cb TV	127
62c1dcfc TV	128	static int omap_dss_set_min_bus_tput(struct device *dev, unsigned long tput)
	129	{
	130	return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
	131	}
	132
acd18af9 TV	133	static enum omapdss_version __init omap_display_get_version(void)
	134	{
	135	if (cpu_is_omap24xx())
	136	return OMAPDSS_VER_OMAP24xx;
	137	else if (cpu_is_omap3630())
	138	return OMAPDSS_VER_OMAP3630;
	139	else if (cpu_is_omap34xx()) {
	140	if (soc_is_am35xx()) {
	141	return OMAPDSS_VER_AM35xx;
	142	} else {
	143	if (omap_rev() < OMAP3430_REV_ES3_0)
	144	return OMAPDSS_VER_OMAP34xx_ES1;
	145	else
	146	return OMAPDSS_VER_OMAP34xx_ES3;
	147	}
	148	} else if (omap_rev() == OMAP4430_REV_ES1_0)
	149	return OMAPDSS_VER_OMAP4430_ES1;
	150	else if (omap_rev() == OMAP4430_REV_ES2_0 \|\|
	151	omap_rev() == OMAP4430_REV_ES2_1 \|\|
	152	omap_rev() == OMAP4430_REV_ES2_2)
	153	return OMAPDSS_VER_OMAP4430_ES2;
	154	else if (cpu_is_omap44xx())
	155	return OMAPDSS_VER_OMAP4;
	156	else if (soc_is_omap54xx())
	157	return OMAPDSS_VER_OMAP5;
d6279d4a SP	158	else if (soc_is_am43xx())
d6279d4a SP	159	return OMAPDSS_VER_AM43xx;
403ee909 TV	160	else if (soc_is_dra7xx())
403ee909 TV	161	return OMAPDSS_VER_DRA7xx;
acd18af9 TV	162	else
	163	return OMAPDSS_VER_UNKNOWN;
	164	}
	165
b923d40d AT	166	static void dispc_disable_outputs(void)
	167	{
	168	u32 v, irq_mask = 0;
465698ee	169	bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
b923d40d AT	170	int i;
	171	struct omap_dss_dispc_dev_attr *da;
	172	struct omap_hwmod *oh;
	173
	174	oh = omap_hwmod_lookup("dss_dispc");
	175	if (!oh) {
	176	WARN(1, "display: could not disable outputs during reset - could not find dss_dispc hwmod\n");
	177	return;
	178	}
	179
	180	if (!oh->dev_attr) {
	181	pr_err("display: could not disable outputs during reset due to missing dev_attr\n");
	182	return;
	183	}
	184
	185	da = (struct omap_dss_dispc_dev_attr *)oh->dev_attr;
	186
	187	/* store value of LCDENABLE and DIGITENABLE bits */
	188	v = omap_hwmod_read(oh, DISPC_CONTROL);
	189	lcd_en = v & LCD_EN_MASK;
	190	digit_en = v & DIGIT_EN_MASK;
	191
	192	/* store value of LCDENABLE for LCD2 */
	193	if (da->manager_count > 2) {
	194	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	195	lcd2_en = v & LCD_EN_MASK;
	196	}
	197
465698ee CM	198	/* store value of LCDENABLE for LCD3 */
	199	if (da->manager_count > 3) {
	200	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	201	lcd3_en = v & LCD_EN_MASK;
	202	}
	203
	204	if (!(lcd_en \| digit_en \| lcd2_en \| lcd3_en))
b923d40d AT	205	return; /* no managers currently enabled */
	206
	207	/*
	208	* If any manager was enabled, we need to disable it before
	209	* DSS clocks are disabled or DISPC module is reset
	210	*/
	211	if (lcd_en)
	212	irq_mask \|= 1 << FRAMEDONE_IRQ_SHIFT;
	213
	214	if (digit_en) {
	215	if (da->has_framedonetv_irq) {
	216	irq_mask \|= 1 << FRAMEDONETV_IRQ_SHIFT;
	217	} else {
	218	irq_mask \|= 1 << EVSYNC_EVEN_IRQ_SHIFT \|
	219	1 << EVSYNC_ODD_IRQ_SHIFT;
	220	}
	221	}
	222
	223	if (lcd2_en)
	224	irq_mask \|= 1 << FRAMEDONE2_IRQ_SHIFT;
465698ee CM	225	if (lcd3_en)
465698ee CM	226	irq_mask \|= 1 << FRAMEDONE3_IRQ_SHIFT;
b923d40d AT	227
	228	/*
	229	* clear any previous FRAMEDONE, FRAMEDONETV,
465698ee	230	* EVSYNC_EVEN/ODD, FRAMEDONE2 or FRAMEDONE3 interrupts
b923d40d AT	231	*/
	232	omap_hwmod_write(irq_mask, oh, DISPC_IRQSTATUS);
	233
	234	/* disable LCD and TV managers */
	235	v = omap_hwmod_read(oh, DISPC_CONTROL);
	236	v &= ~(LCD_EN_MASK \| DIGIT_EN_MASK);
	237	omap_hwmod_write(v, oh, DISPC_CONTROL);
	238
	239	/* disable LCD2 manager */
	240	if (da->manager_count > 2) {
	241	v = omap_hwmod_read(oh, DISPC_CONTROL2);
	242	v &= ~LCD_EN_MASK;
	243	omap_hwmod_write(v, oh, DISPC_CONTROL2);
	244	}
	245
465698ee CM	246	/* disable LCD3 manager */
	247	if (da->manager_count > 3) {
	248	v = omap_hwmod_read(oh, DISPC_CONTROL3);
	249	v &= ~LCD_EN_MASK;
	250	omap_hwmod_write(v, oh, DISPC_CONTROL3);
	251	}
	252
b923d40d AT	253	i = 0;
	254	while ((omap_hwmod_read(oh, DISPC_IRQSTATUS) & irq_mask) !=
	255	irq_mask) {
	256	i++;
	257	if (i > FRAMEDONE_IRQ_TIMEOUT) {
465698ee	258	pr_err("didn't get FRAMEDONE1/2/3 or TV interrupt\n");
b923d40d AT	259	break;
	260	}
	261	mdelay(1);
	262	}
	263	}
	264
13662dc5 TV	265	int omap_dss_reset(struct omap_hwmod *oh)
	266	{
	267	struct omap_hwmod_opt_clk *oc;
	268	int c = 0;
	269	int i, r;
	270
	271	if (!(oh->class->sysc->sysc_flags & SYSS_HAS_RESET_STATUS)) {
	272	pr_err("dss_core: hwmod data doesn't contain reset data\n");
	273	return -EINVAL;
	274	}
	275
	276	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	277	if (oc->_clk)
4d7cb45e	278	clk_prepare_enable(oc->_clk);
13662dc5	279
b923d40d AT	280	dispc_disable_outputs();
	281
	282	/* clear SDI registers */
	283	if (cpu_is_omap3430()) {
	284	omap_hwmod_write(0x0, oh, DSS_SDI_CONTROL);
	285	omap_hwmod_write(0x0, oh, DSS_PLL_CONTROL);
	286	}
	287
	288	/*
	289	* clear DSS_CONTROL register to switch DSS clock sources to
	290	* PRCM clock, if any
	291	*/
	292	omap_hwmod_write(0x0, oh, DSS_CONTROL);
	293
13662dc5 TV	294	omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
	295	& SYSS_RESETDONE_MASK),
	296	MAX_MODULE_SOFTRESET_WAIT, c);
	297
	298	if (c == MAX_MODULE_SOFTRESET_WAIT)
3d0cb73e	299	pr_warn("dss_core: waiting for reset to finish failed\n");
13662dc5 TV	300	else
	301	pr_debug("dss_core: softreset done\n");
	302
	303	for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
	304	if (oc->_clk)
4d7cb45e	305	clk_disable_unprepare(oc->_clk);
13662dc5 TV	306
	307	r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
	308
	309	return r;
	310	}
dcdf407b	311
5b5992ac TV	312	static const char * const omapdss_compat_names[] __initconst = {
	313	"ti,omap2-dss",
	314	"ti,omap3-dss",
	315	"ti,omap4-dss",
	316	"ti,omap5-dss",
403ee909	317	"ti,dra7-dss",
5b5992ac TV	318	};
5b5992ac TV	319
7afa44e0	320	static struct device_node * __init omapdss_find_dss_of_node(void)
dcdf407b TV	321	{
dcdf407b TV	322	struct device_node *node;
5b5992ac	323	int i;
dcdf407b	324
5b5992ac TV	325	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {
	326	node = of_find_compatible_node(NULL, NULL,
	327	omapdss_compat_names[i]);
	328	if (node)
	329	return node;
	330	}
9a308948	331
dcdf407b TV	332	return NULL;
	333	}
	334
	335	int __init omapdss_init_of(void)
	336	{
	337	int r;
	338	enum omapdss_version ver;
	339	struct device_node *node;
	340	struct platform_device *pdev;
	341
	342	static struct omap_dss_board_info board_data = {
	343	.dsi_enable_pads = omap_dsi_enable_pads,
	344	.dsi_disable_pads = omap_dsi_disable_pads,
dcdf407b TV	345	.set_min_bus_tput = omap_dss_set_min_bus_tput,
	346	};
	347
	348	/* only create dss helper devices if dss is enabled in the .dts */
	349
	350	node = omapdss_find_dss_of_node();
	351	if (!node)
	352	return 0;
	353
	354	if (!of_device_is_available(node))
	355	return 0;
	356
	357	ver = omap_display_get_version();
	358
	359	if (ver == OMAPDSS_VER_UNKNOWN) {
	360	pr_err("DSS not supported on this SoC\n");
	361	return -ENODEV;
	362	}
	363
	364	pdev = of_find_device_by_node(node);
	365
	366	if (!pdev) {
	367	pr_err("Unable to find DSS platform device\n");
	368	return -ENODEV;
	369	}
	370
	371	r = of_platform_populate(node, NULL, NULL, &pdev->dev);
	372	if (r) {
	373	pr_err("Unable to populate DSS submodule devices\n");
	374	return r;
	375	}
	376
	377	board_data.version = ver;
	378
	379	omap_display_device.dev.platform_data = &board_data;
	380
	381	r = platform_device_register(&omap_display_device);
	382	if (r < 0) {
	383	pr_err("Unable to register omapdss device\n");
	384	return r;
	385	}
	386
	387	/* create DRM device */
	388	r = omap_init_drm();
	389	if (r < 0) {
	390	pr_err("Unable to register omapdrm device\n");
	391	return r;
	392	}
	393
	394	/* create vrfb device */
	395	r = omap_init_vrfb();
	396	if (r < 0) {
	397	pr_err("Unable to register omapvrfb device\n");
	398	return r;
	399	}
	400
	401	/* create FB device */
	402	r = omap_init_fb();
	403	if (r < 0) {
	404	pr_err("Unable to register omapfb device\n");
	405	return r;
	406	}
	407
	408	/* create V4L2 display device */
409	r = omap_init_vout();
410	if (r < 0) {
411	pr_err("Unable to register omap_vout device\n");
412	return r;
413	}
414
23d34981 TK	415	/* add DSI info for omap4 */
	416	node = of_find_node_by_name(NULL, "omap4_padconf_global");
	417	if (node)
	418	omap4_dsi_mux_syscon = syscon_node_to_regmap(node);
	419
dcdf407b TV	420	return 0;
dcdf407b TV	421	}