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OMAP: hwmod: Do not exit the iteration if one clock init failed
[linux-2.6-block.git] / arch / arm / mach-omap2 / devices.c
CommitLineData
1dbae815
TL		 1/*
2 * linux/arch/arm/mach-omap2/devices.c
3 *
4 * OMAP2 platform device setup/initialization
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
1dbae815
TL		 12#include <linux/module.h>
13#include <linux/kernel.h>
14#include <linux/init.h>
15#include <linux/platform_device.h>
fced80c7 16#include <linux/io.h>
917fa280 17#include <linux/clk.h>
1dbae815 18
a09e64fb 19#include <mach/hardware.h>
1dbae815
TL		 20#include <asm/mach-types.h>
21#include <asm/mach/map.h>
22
ce491cf8
TL		 23#include <plat/control.h>
24#include <plat/tc.h>
25#include <plat/board.h>
26#include <plat/mux.h>
a09e64fb 27#include <mach/gpio.h>
ce491cf8 28#include <plat/mmc.h>
1dbae815 29
4896e394
TL		 30#include "mux.h"
31
828c707e 32#if defined(CONFIG_VIDEO_OMAP2) || defined(CONFIG_VIDEO_OMAP2_MODULE)
c40fae95 33
828c707e 34static struct resource cam_resources[] = {
c40fae95 35 {
828c707e
TL		 36 .start = OMAP24XX_CAMERA_BASE,
37 .end = OMAP24XX_CAMERA_BASE + 0xfff,
38 .flags = IORESOURCE_MEM,
39 },
40 {
41 .start = INT_24XX_CAM_IRQ,
42 .flags = IORESOURCE_IRQ,
43 }
44};
45
46static struct platform_device omap_cam_device = {
47 .name = "omap24xxcam",
48 .id = -1,
49 .num_resources = ARRAY_SIZE(cam_resources),
50 .resource = cam_resources,
51};
52
53static inline void omap_init_camera(void)
54{
55 platform_device_register(&omap_cam_device);
56}
57
58#elif defined(CONFIG_VIDEO_OMAP3) || defined(CONFIG_VIDEO_OMAP3_MODULE)
59
60static struct resource omap3isp_resources[] = {
61 {
62 .start = OMAP3430_ISP_BASE,
63 .end = OMAP3430_ISP_END,
64 .flags = IORESOURCE_MEM,
65 },
66 {
67 .start = OMAP3430_ISP_CBUFF_BASE,
68 .end = OMAP3430_ISP_CBUFF_END,
69 .flags = IORESOURCE_MEM,
70 },
71 {
72 .start = OMAP3430_ISP_CCP2_BASE,
73 .end = OMAP3430_ISP_CCP2_END,
74 .flags = IORESOURCE_MEM,
75 },
76 {
77 .start = OMAP3430_ISP_CCDC_BASE,
78 .end = OMAP3430_ISP_CCDC_END,
79 .flags = IORESOURCE_MEM,
80 },
81 {
82 .start = OMAP3430_ISP_HIST_BASE,
83 .end = OMAP3430_ISP_HIST_END,
84 .flags = IORESOURCE_MEM,
85 },
86 {
87 .start = OMAP3430_ISP_H3A_BASE,
88 .end = OMAP3430_ISP_H3A_END,
89 .flags = IORESOURCE_MEM,
90 },
91 {
92 .start = OMAP3430_ISP_PREV_BASE,
93 .end = OMAP3430_ISP_PREV_END,
94 .flags = IORESOURCE_MEM,
95 },
96 {
97 .start = OMAP3430_ISP_RESZ_BASE,
98 .end = OMAP3430_ISP_RESZ_END,
99 .flags = IORESOURCE_MEM,
100 },
101 {
102 .start = OMAP3430_ISP_SBL_BASE,
103 .end = OMAP3430_ISP_SBL_END,
104 .flags = IORESOURCE_MEM,
105 },
106 {
107 .start = OMAP3430_ISP_CSI2A_BASE,
108 .end = OMAP3430_ISP_CSI2A_END,
109 .flags = IORESOURCE_MEM,
110 },
111 {
112 .start = OMAP3430_ISP_CSI2PHY_BASE,
113 .end = OMAP3430_ISP_CSI2PHY_END,
114 .flags = IORESOURCE_MEM,
115 },
116 {
117 .start = INT_34XX_CAM_IRQ,
118 .flags = IORESOURCE_IRQ,
119 }
120};
121
122static struct platform_device omap3isp_device = {
123 .name = "omap3isp",
124 .id = -1,
125 .num_resources = ARRAY_SIZE(omap3isp_resources),
126 .resource = omap3isp_resources,
127};
128
129static inline void omap_init_camera(void)
130{
131 platform_device_register(&omap3isp_device);
132}
133#else
134static inline void omap_init_camera(void)
135{
136}
137#endif
138
6c20a683 139#if defined(CONFIG_OMAP_MBOX_FWK) || defined(CONFIG_OMAP_MBOX_FWK_MODULE)
c40fae95 140
454bf340 141#define MBOX_REG_SIZE 0x120
6c20a683 142
454bf340 143#ifdef CONFIG_ARCH_OMAP2
d10f2b6e 144static struct resource omap2_mbox_resources[] = {
c40fae95 145 {
6c20a683
HD		 146 .start = OMAP24XX_MAILBOX_BASE,
147 .end = OMAP24XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
c40fae95
TL		 148 .flags = IORESOURCE_MEM,
149 },
150 {
151 .start = INT_24XX_MAIL_U0_MPU,
152 .flags = IORESOURCE_IRQ,
153 },
154 {
155 .start = INT_24XX_MAIL_U3_MPU,
156 .flags = IORESOURCE_IRQ,
157 },
158};
d10f2b6e
TL		 159static int omap2_mbox_resources_sz = ARRAY_SIZE(omap2_mbox_resources);
160#else
161#define omap2_mbox_resources NULL
162#define omap2_mbox_resources_sz 0
454bf340 163#endif
c40fae95 164
454bf340 165#ifdef CONFIG_ARCH_OMAP3
d10f2b6e 166static struct resource omap3_mbox_resources[] = {
6c20a683
HD		 167 {
168 .start = OMAP34XX_MAILBOX_BASE,
169 .end = OMAP34XX_MAILBOX_BASE + MBOX_REG_SIZE - 1,
170 .flags = IORESOURCE_MEM,
171 },
172 {
173 .start = INT_24XX_MAIL_U0_MPU,
174 .flags = IORESOURCE_IRQ,
175 },
176};
d10f2b6e
TL		 177static int omap3_mbox_resources_sz = ARRAY_SIZE(omap3_mbox_resources);
178#else
179#define omap3_mbox_resources NULL
180#define omap3_mbox_resources_sz 0
454bf340
S		 181#endif
182
183#ifdef CONFIG_ARCH_OMAP4
184
185#define OMAP4_MBOX_REG_SIZE 0x130
d10f2b6e 186static struct resource omap4_mbox_resources[] = {
454bf340
S		 187 {
188 .start = OMAP44XX_MAILBOX_BASE,
189 .end = OMAP44XX_MAILBOX_BASE +
190 OMAP4_MBOX_REG_SIZE - 1,
191 .flags = IORESOURCE_MEM,
192 },
193 {
5772ca7d 194 .start = OMAP44XX_IRQ_MAIL_U0,
454bf340
S		 195 .flags = IORESOURCE_IRQ,
196 },
197};
d10f2b6e
TL		 198static int omap4_mbox_resources_sz = ARRAY_SIZE(omap4_mbox_resources);
199#else
200#define omap4_mbox_resources NULL
201#define omap4_mbox_resources_sz 0
454bf340 202#endif
6c20a683 203
c40fae95 204static struct platform_device mbox_device = {
da8cfe03 205 .name = "omap2-mailbox",
c40fae95 206 .id = -1,
c40fae95
TL		 207};
208
209static inline void omap_init_mbox(void)
210{
d10f2b6e
TL		 211 if (cpu_is_omap24xx()) {
212 mbox_device.resource = omap2_mbox_resources;
213 mbox_device.num_resources = omap2_mbox_resources_sz;
214 } else if (cpu_is_omap34xx()) {
215 mbox_device.resource = omap3_mbox_resources;
216 mbox_device.num_resources = omap3_mbox_resources_sz;
217 } else if (cpu_is_omap44xx()) {
218 mbox_device.resource = omap4_mbox_resources;
219 mbox_device.num_resources = omap4_mbox_resources_sz;
6c20a683
HD		 220 } else {
221 pr_err("%s: platform not supported\n", __func__);
222 return;
223 }
c40fae95
TL		 224 platform_device_register(&mbox_device);
225}
226#else
227static inline void omap_init_mbox(void) { }
6c20a683 228#endif /* CONFIG_OMAP_MBOX_FWK */
c40fae95 229
9b6553cd
TL		 230#if defined(CONFIG_OMAP_STI)
231
646e3ed1
TL		 232#if defined(CONFIG_ARCH_OMAP2)
233
234#define OMAP2_STI_BASE 0x48068000
9b6553cd
TL		 235#define OMAP2_STI_CHANNEL_BASE 0x54000000
236#define OMAP2_STI_IRQ 4
237
238static struct resource sti_resources[] = {
239 {
240 .start = OMAP2_STI_BASE,
241 .end = OMAP2_STI_BASE + 0x7ff,
242 .flags = IORESOURCE_MEM,
243 },
244 {
245 .start = OMAP2_STI_CHANNEL_BASE,
246 .end = OMAP2_STI_CHANNEL_BASE + SZ_64K - 1,
247 .flags = IORESOURCE_MEM,
248 },
249 {
250 .start = OMAP2_STI_IRQ,
251 .flags = IORESOURCE_IRQ,
252 }
253};
646e3ed1
TL		 254#elif defined(CONFIG_ARCH_OMAP3)
255
256#define OMAP3_SDTI_BASE 0x54500000
257#define OMAP3_SDTI_CHANNEL_BASE 0x54600000
258
259static struct resource sti_resources[] = {
260 {
261 .start = OMAP3_SDTI_BASE,
262 .end = OMAP3_SDTI_BASE + 0xFFF,
263 .flags = IORESOURCE_MEM,
264 },
265 {
266 .start = OMAP3_SDTI_CHANNEL_BASE,
267 .end = OMAP3_SDTI_CHANNEL_BASE + SZ_1M - 1,
268 .flags = IORESOURCE_MEM,
269 }
270};
271
272#endif
9b6553cd
TL		 273
274static struct platform_device sti_device = {
275 .name = "sti",
276 .id = -1,
9b6553cd
TL		 277 .num_resources = ARRAY_SIZE(sti_resources),
278 .resource = sti_resources,
279};
280
281static inline void omap_init_sti(void)
282{
283 platform_device_register(&sti_device);
284}
285#else
286static inline void omap_init_sti(void) {}
287#endif
288
646e3ed1 289#if defined(CONFIG_SPI_OMAP24XX) || defined(CONFIG_SPI_OMAP24XX_MODULE)
ed7eb9d9 290
ce491cf8 291#include <plat/mcspi.h>
ed7eb9d9
JY		 292
293#define OMAP2_MCSPI1_BASE 0x48098000
294#define OMAP2_MCSPI2_BASE 0x4809a000
646e3ed1
TL		 295#define OMAP2_MCSPI3_BASE 0x480b8000
296#define OMAP2_MCSPI4_BASE 0x480ba000
ed7eb9d9 297
7869c0b9
SR		 298#define OMAP4_MCSPI1_BASE 0x48098100
299#define OMAP4_MCSPI2_BASE 0x4809a100
300#define OMAP4_MCSPI3_BASE 0x480b8100
301#define OMAP4_MCSPI4_BASE 0x480ba100
302
ed7eb9d9 303static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
ed7eb9d9
JY		 304 .num_cs = 4,
305};
306
c40fae95
TL		 307static struct resource omap2_mcspi1_resources[] = {
308 {
309 .start = OMAP2_MCSPI1_BASE,
310 .end = OMAP2_MCSPI1_BASE + 0xff,
311 .flags = IORESOURCE_MEM,
312 },
313};
314
646e3ed1 315static struct platform_device omap2_mcspi1 = {
ed7eb9d9
JY		 316 .name = "omap2_mcspi",
317 .id = 1,
c40fae95
TL		 318 .num_resources = ARRAY_SIZE(omap2_mcspi1_resources),
319 .resource = omap2_mcspi1_resources,
ed7eb9d9
JY		 320 .dev = {
321 .platform_data = &omap2_mcspi1_config,
322 },
323};
324
325static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
ed7eb9d9
JY		 326 .num_cs = 2,
327};
328
c40fae95
TL		 329static struct resource omap2_mcspi2_resources[] = {
330 {
331 .start = OMAP2_MCSPI2_BASE,
332 .end = OMAP2_MCSPI2_BASE + 0xff,
333 .flags = IORESOURCE_MEM,
334 },
335};
336
646e3ed1 337static struct platform_device omap2_mcspi2 = {
ed7eb9d9
JY		 338 .name = "omap2_mcspi",
339 .id = 2,
c40fae95
TL		 340 .num_resources = ARRAY_SIZE(omap2_mcspi2_resources),
341 .resource = omap2_mcspi2_resources,
ed7eb9d9
JY		 342 .dev = {
343 .platform_data = &omap2_mcspi2_config,
344 },
345};
346
7869c0b9
SR		 347#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
348 defined(CONFIG_ARCH_OMAP4)
646e3ed1
TL		 349static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
350 .num_cs = 2,
351};
352
353static struct resource omap2_mcspi3_resources[] = {
354 {
355 .start = OMAP2_MCSPI3_BASE,
356 .end = OMAP2_MCSPI3_BASE + 0xff,
357 .flags = IORESOURCE_MEM,
358 },
359};
360
361static struct platform_device omap2_mcspi3 = {
362 .name = "omap2_mcspi",
363 .id = 3,
364 .num_resources = ARRAY_SIZE(omap2_mcspi3_resources),
365 .resource = omap2_mcspi3_resources,
366 .dev = {
367 .platform_data = &omap2_mcspi3_config,
368 },
369};
370#endif
371
7869c0b9 372#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
646e3ed1
TL		 373static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
374 .num_cs = 1,
375};
376
377static struct resource omap2_mcspi4_resources[] = {
378 {
379 .start = OMAP2_MCSPI4_BASE,
380 .end = OMAP2_MCSPI4_BASE + 0xff,
381 .flags = IORESOURCE_MEM,
382 },
383};
384
385static struct platform_device omap2_mcspi4 = {
386 .name = "omap2_mcspi",
387 .id = 4,
388 .num_resources = ARRAY_SIZE(omap2_mcspi4_resources),
389 .resource = omap2_mcspi4_resources,
390 .dev = {
391 .platform_data = &omap2_mcspi4_config,
392 },
393};
394#endif
395
af41a12f
TL		 396#ifdef CONFIG_ARCH_OMAP4
397static inline void omap4_mcspi_fixup(void)
ed7eb9d9 398{
af41a12f
TL		 399 omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
400 omap2_mcspi1_resources[0].end = OMAP4_MCSPI1_BASE + 0xff;
401 omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
402 omap2_mcspi2_resources[0].end = OMAP4_MCSPI2_BASE + 0xff;
403 omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
404 omap2_mcspi3_resources[0].end = OMAP4_MCSPI3_BASE + 0xff;
405 omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
406 omap2_mcspi4_resources[0].end = OMAP4_MCSPI4_BASE + 0xff;
407}
408#else
409static inline void omap4_mcspi_fixup(void)
410{
411}
412#endif
413
7869c0b9
SR		 414#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
415 defined(CONFIG_ARCH_OMAP4)
af41a12f
TL		 416static inline void omap2_mcspi3_init(void)
417{
418 platform_device_register(&omap2_mcspi3);
419}
420#else
421static inline void omap2_mcspi3_init(void)
422{
423}
646e3ed1 424#endif
af41a12f 425
7869c0b9 426#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
af41a12f
TL		 427static inline void omap2_mcspi4_init(void)
428{
429 platform_device_register(&omap2_mcspi4);
430}
431#else
432static inline void omap2_mcspi4_init(void)
433{
434}
646e3ed1 435#endif
af41a12f
TL		 436
437static void omap_init_mcspi(void)
438{
439 if (cpu_is_omap44xx())
440 omap4_mcspi_fixup();
441
442 platform_device_register(&omap2_mcspi1);
443 platform_device_register(&omap2_mcspi2);
444
445 if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
446 omap2_mcspi3_init();
447
448 if (cpu_is_omap343x() || cpu_is_omap44xx())
449 omap2_mcspi4_init();
ed7eb9d9
JY		 450}
451
452#else
453static inline void omap_init_mcspi(void) {}
454#endif
455
646e3ed1
TL		 456#ifdef CONFIG_OMAP_SHA1_MD5
457static struct resource sha1_md5_resources[] = {
458 {
459 .start = OMAP24XX_SEC_SHA1MD5_BASE,
460 .end = OMAP24XX_SEC_SHA1MD5_BASE + 0x64,
461 .flags = IORESOURCE_MEM,
462 },
463 {
464 .start = INT_24XX_SHA1MD5,
465 .flags = IORESOURCE_IRQ,
466 }
467};
468
469static struct platform_device sha1_md5_device = {
470 .name = "OMAP SHA1/MD5",
471 .id = -1,
472 .num_resources = ARRAY_SIZE(sha1_md5_resources),
473 .resource = sha1_md5_resources,
474};
475
476static void omap_init_sha1_md5(void)
477{
478 platform_device_register(&sha1_md5_device);
479}
480#else
481static inline void omap_init_sha1_md5(void) { }
482#endif
483
d8874665
TL		 484/*-------------------------------------------------------------------------*/
485
82cf818d 486#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
917fa280
KH		 487
488#define MMCHS_SYSCONFIG 0x0010
489#define MMCHS_SYSCONFIG_SWRESET (1 << 1)
490#define MMCHS_SYSSTATUS 0x0014
491#define MMCHS_SYSSTATUS_RESETDONE (1 << 0)
492
493static struct platform_device dummy_pdev = {
494 .dev = {
495 .bus = &platform_bus_type,
496 },
497};
498
499/**
500 * omap_hsmmc_reset() - Full reset of each HS-MMC controller
501 *
502 * Ensure that each MMC controller is fully reset. Controllers
503 * left in an unknown state (by bootloader) may prevent retention
504 * or OFF-mode. This is especially important in cases where the
505 * MMC driver is not enabled, _or_ built as a module.
506 *
507 * In order for reset to work, interface, functional and debounce
508 * clocks must be enabled. The debounce clock comes from func_32k_clk
509 * and is not under SW control, so we only enable i- and f-clocks.
510 **/
511static void __init omap_hsmmc_reset(void)
512{
4323e9f7
TL		 513 u32 i, nr_controllers;
514
515 if (cpu_is_omap242x())
516 return;
517
518 nr_controllers = cpu_is_omap44xx() ? OMAP44XX_NR_MMC :
82cf818d 519 (cpu_is_omap34xx() ? OMAP34XX_NR_MMC : OMAP24XX_NR_MMC);
917fa280
KH		 520
521 for (i = 0; i < nr_controllers; i++) {
522 u32 v, base = 0;
523 struct clk *iclk, *fclk;
524 struct device *dev = &dummy_pdev.dev;
525
526 switch (i) {
527 case 0:
528 base = OMAP2_MMC1_BASE;
529 break;
530 case 1:
531 base = OMAP2_MMC2_BASE;
532 break;
533 case 2:
534 base = OMAP3_MMC3_BASE;
535 break;
82cf818d 536 case 3:
537 if (!cpu_is_omap44xx())
538 return;
539 base = OMAP4_MMC4_BASE;
540 break;
541 case 4:
542 if (!cpu_is_omap44xx())
543 return;
544 base = OMAP4_MMC5_BASE;
545 break;
917fa280
KH		 546 }
547
82cf818d 548 if (cpu_is_omap44xx())
549 base += OMAP4_MMC_REG_OFFSET;
550
917fa280 551 dummy_pdev.id = i;
1e98ffa8 552 dev_set_name(&dummy_pdev.dev, "mmci-omap-hs.%d", i);
6f7607cc 553 iclk = clk_get(dev, "ick");
917fa280
KH		 554 if (iclk && clk_enable(iclk))
555 iclk = NULL;
556
6f7607cc 557 fclk = clk_get(dev, "fck");
917fa280
KH		 558 if (fclk && clk_enable(fclk))
559 fclk = NULL;
560
561 if (!iclk || !fclk) {
562 printk(KERN_WARNING
563 "%s: Unable to enable clocks for MMC%d, "
564 "cannot reset.\n", __func__, i);
565 break;
566 }
567
568 omap_writel(MMCHS_SYSCONFIG_SWRESET, base + MMCHS_SYSCONFIG);
569 v = omap_readl(base + MMCHS_SYSSTATUS);
570 while (!(omap_readl(base + MMCHS_SYSSTATUS) &
571 MMCHS_SYSSTATUS_RESETDONE))
572 cpu_relax();
573
574 if (fclk) {
575 clk_disable(fclk);
576 clk_put(fclk);
577 }
578 if (iclk) {
579 clk_disable(iclk);
580 clk_put(iclk);
581 }
582 }
583}
584#else
585static inline void omap_hsmmc_reset(void) {}
586#endif
587
d8874665
TL		 588#if defined(CONFIG_MMC_OMAP) || defined(CONFIG_MMC_OMAP_MODULE) || \
589 defined(CONFIG_MMC_OMAP_HS) || defined(CONFIG_MMC_OMAP_HS_MODULE)
590
591static inline void omap2_mmc_mux(struct omap_mmc_platform_data *mmc_controller,
592 int controller_nr)
593{
ed8303fc 594 if ((mmc_controller->slots[0].switch_pin > 0) && \
595 (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
596 omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
597 OMAP_PIN_INPUT_PULLUP);
598 if ((mmc_controller->slots[0].gpio_wp > 0) && \
599 (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
600 omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
601 OMAP_PIN_INPUT_PULLUP);
602
d8874665
TL		 603 if (cpu_is_omap2420() && controller_nr == 0) {
604 omap_cfg_reg(H18_24XX_MMC_CMD);
605 omap_cfg_reg(H15_24XX_MMC_CLKI);
606 omap_cfg_reg(G19_24XX_MMC_CLKO);
607 omap_cfg_reg(F20_24XX_MMC_DAT0);
608 omap_cfg_reg(F19_24XX_MMC_DAT_DIR0);
609 omap_cfg_reg(G18_24XX_MMC_CMD_DIR);
90c62bf0 610 if (mmc_controller->slots[0].wires == 4) {
d8874665
TL		 611 omap_cfg_reg(H14_24XX_MMC_DAT1);
612 omap_cfg_reg(E19_24XX_MMC_DAT2);
613 omap_cfg_reg(D19_24XX_MMC_DAT3);
614 omap_cfg_reg(E20_24XX_MMC_DAT_DIR1);
615 omap_cfg_reg(F18_24XX_MMC_DAT_DIR2);
616 omap_cfg_reg(E18_24XX_MMC_DAT_DIR3);
617 }
618
619 /*
620 * Use internal loop-back in MMC/SDIO Module Input Clock
621 * selection
622 */
623 if (mmc_controller->slots[0].internal_clock) {
624 u32 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
625 v |= (1 << 24);
626 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
627 }
628 }
57b9daa0 629
4596d14a 630 if (cpu_is_omap34xx()) {
57b9daa0 631 if (controller_nr == 0) {
4896e394
TL		 632 omap_mux_init_signal("sdmmc1_clk",
633 OMAP_PIN_INPUT_PULLUP);
634 omap_mux_init_signal("sdmmc1_cmd",
635 OMAP_PIN_INPUT_PULLUP);
636 omap_mux_init_signal("sdmmc1_dat0",
637 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 638 if (mmc_controller->slots[0].wires == 4 ||
639 mmc_controller->slots[0].wires == 8) {
4896e394
TL		 640 omap_mux_init_signal("sdmmc1_dat1",
641 OMAP_PIN_INPUT_PULLUP);
642 omap_mux_init_signal("sdmmc1_dat2",
643 OMAP_PIN_INPUT_PULLUP);
644 omap_mux_init_signal("sdmmc1_dat3",
645 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 646 }
647 if (mmc_controller->slots[0].wires == 8) {
4896e394
TL		 648 omap_mux_init_signal("sdmmc1_dat4",
649 OMAP_PIN_INPUT_PULLUP);
650 omap_mux_init_signal("sdmmc1_dat5",
651 OMAP_PIN_INPUT_PULLUP);
652 omap_mux_init_signal("sdmmc1_dat6",
653 OMAP_PIN_INPUT_PULLUP);
654 omap_mux_init_signal("sdmmc1_dat7",
655 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 656 }
657 }
658 if (controller_nr == 1) {
659 /* MMC2 */
4896e394
TL		 660 omap_mux_init_signal("sdmmc2_clk",
661 OMAP_PIN_INPUT_PULLUP);
662 omap_mux_init_signal("sdmmc2_cmd",
663 OMAP_PIN_INPUT_PULLUP);
664 omap_mux_init_signal("sdmmc2_dat0",
665 OMAP_PIN_INPUT_PULLUP);
57b9daa0
VP		 666
667 /*
668 * For 8 wire configurations, Lines DAT4, 5, 6 and 7 need to be muxed
669 * in the board-*.c files
670 */
671 if (mmc_controller->slots[0].wires == 4 ||
672 mmc_controller->slots[0].wires == 8) {
4896e394
TL		 673 omap_mux_init_signal("sdmmc2_dat1",
674 OMAP_PIN_INPUT_PULLUP);
675 omap_mux_init_signal("sdmmc2_dat2",
676 OMAP_PIN_INPUT_PULLUP);
677 omap_mux_init_signal("sdmmc2_dat3",
678 OMAP_PIN_INPUT_PULLUP);
57b9daa0 679 }
4679232d 680 if (mmc_controller->slots[0].wires == 8) {
4896e394
TL		 681 omap_mux_init_signal("sdmmc2_dat4.sdmmc2_dat4",
682 OMAP_PIN_INPUT_PULLUP);
683 omap_mux_init_signal("sdmmc2_dat5.sdmmc2_dat5",
684 OMAP_PIN_INPUT_PULLUP);
685 omap_mux_init_signal("sdmmc2_dat6.sdmmc2_dat6",
686 OMAP_PIN_INPUT_PULLUP);
687 omap_mux_init_signal("sdmmc2_dat7.sdmmc2_dat7",
688 OMAP_PIN_INPUT_PULLUP);
4679232d 689 }
57b9daa0
VP		 690 }
691
692 /*
693 * For MMC3 the pins need to be muxed in the board-*.c files
694 */
695 }
d8874665
TL		 696}
697
698void __init omap2_init_mmc(struct omap_mmc_platform_data **mmc_data,
699 int nr_controllers)
700{
701 int i;
0dffb5c5 702 char *name;
d8874665
TL		 703
704 for (i = 0; i < nr_controllers; i++) {
705 unsigned long base, size;
706 unsigned int irq = 0;
707
708 if (!mmc_data[i])
709 continue;
710
711 omap2_mmc_mux(mmc_data[i], i);
712
713 switch (i) {
714 case 0:
715 base = OMAP2_MMC1_BASE;
716 irq = INT_24XX_MMC_IRQ;
717 break;
718 case 1:
719 base = OMAP2_MMC2_BASE;
720 irq = INT_24XX_MMC2_IRQ;
721 break;
722 case 2:
82cf818d 723 if (!cpu_is_omap44xx() && !cpu_is_omap34xx())
d8874665
TL		 724 return;
725 base = OMAP3_MMC3_BASE;
726 irq = INT_34XX_MMC3_IRQ;
727 break;
82cf818d 728 case 3:
729 if (!cpu_is_omap44xx())
730 return;
731 base = OMAP4_MMC4_BASE + OMAP4_MMC_REG_OFFSET;
5772ca7d 732 irq = OMAP44XX_IRQ_MMC4;
82cf818d 733 break;
734 case 4:
735 if (!cpu_is_omap44xx())
736 return;
737 base = OMAP4_MMC5_BASE + OMAP4_MMC_REG_OFFSET;
9df76b7f 738 irq = OMAP44XX_IRQ_MMC5;
82cf818d 739 break;
d8874665
TL		 740 default:
741 continue;
742 }
743
0dffb5c5 744 if (cpu_is_omap2420()) {
d8874665 745 size = OMAP2420_MMC_SIZE;
0dffb5c5 746 name = "mmci-omap";
82cf818d 747 } else if (cpu_is_omap44xx()) {
748 if (i < 3) {
749 base += OMAP4_MMC_REG_OFFSET;
5772ca7d 750 irq += OMAP44XX_IRQ_GIC_START;
82cf818d 751 }
752 size = OMAP4_HSMMC_SIZE;
753 name = "mmci-omap-hs";
0dffb5c5 754 } else {
82cf818d 755 size = OMAP3_HSMMC_SIZE;
0dffb5c5
TL		 756 name = "mmci-omap-hs";
757 }
758 omap_mmc_add(name, i, base, size, irq, mmc_data[i]);
d8874665
TL		 759 };
760}
761
762#endif
763
764/*-------------------------------------------------------------------------*/
765
646e3ed1
TL		 766#if defined(CONFIG_HDQ_MASTER_OMAP) || defined(CONFIG_HDQ_MASTER_OMAP_MODULE)
767#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
768#define OMAP_HDQ_BASE 0x480B2000
769#endif
770static struct resource omap_hdq_resources[] = {
771 {
772 .start = OMAP_HDQ_BASE,
773 .end = OMAP_HDQ_BASE + 0x1C,
774 .flags = IORESOURCE_MEM,
775 },
776 {
777 .start = INT_24XX_HDQ_IRQ,
778 .flags = IORESOURCE_IRQ,
779 },
780};
781static struct platform_device omap_hdq_dev = {
782 .name = "omap_hdq",
783 .id = 0,
784 .dev = {
785 .platform_data = NULL,
786 },
787 .num_resources = ARRAY_SIZE(omap_hdq_resources),
788 .resource = omap_hdq_resources,
789};
790static inline void omap_hdq_init(void)
791{
792 (void) platform_device_register(&omap_hdq_dev);
793}
794#else
795static inline void omap_hdq_init(void) {}
796#endif
797
b227358d
VH		 798/*---------------------------------------------------------------------------*/
799
800#if defined(CONFIG_VIDEO_OMAP2_VOUT) || \
801 defined(CONFIG_VIDEO_OMAP2_VOUT_MODULE)
802#if defined(CONFIG_FB_OMAP2) || defined(CONFIG_FB_OMAP2_MODULE)
803static struct resource omap_vout_resource[3 - CONFIG_FB_OMAP2_NUM_FBS] = {
804};
805#else
806static struct resource omap_vout_resource[2] = {
807};
808#endif
809
810static struct platform_device omap_vout_device = {
811 .name = "omap_vout",
812 .num_resources = ARRAY_SIZE(omap_vout_resource),
813 .resource = &omap_vout_resource[0],
814 .id = -1,
815};
816static void omap_init_vout(void)
817{
818 if (platform_device_register(&omap_vout_device) < 0)
819 printk(KERN_ERR "Unable to register OMAP-VOUT device\n");
820}
821#else
822static inline void omap_init_vout(void) {}
823#endif
824
1dbae815
TL		 825/*-------------------------------------------------------------------------*/
826
827static int __init omap2_init_devices(void)
828{
829 /* please keep these calls, and their implementations above,
830 * in alphabetical order so they're easier to sort through.
831 */
917fa280 832 omap_hsmmc_reset();
828c707e 833 omap_init_camera();
c40fae95 834 omap_init_mbox();
ed7eb9d9 835 omap_init_mcspi();
646e3ed1 836 omap_hdq_init();
9b6553cd 837 omap_init_sti();
646e3ed1 838 omap_init_sha1_md5();
b227358d 839 omap_init_vout();
1dbae815
TL		 840
841 return 0;
842}
843arch_initcall(omap2_init_devices);
Linux 6.x block layer and io_uring tree(s)