[linux-2.6-block.git] / arch / arm / mach-omap2 / cpuidle34xx.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>
#include <linux/cpu_pm.h>
#include <asm/cpuidle.h>

#include "powerdomain.h"
#include "clockdomain.h"

#include "pm.h"
#include "control.h"
#include "common.h"
#include "soc.h"

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u8 mpu_state;
	u8 core_state;
	u8 per_min_state;
	u8 flags;
};

static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

/*
 * Possible flag bits for struct omap3_idle_statedata.flags:
 *
 * OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
 *    inactive.  This in turn prevents the MPU DPLL from entering autoidle
 *    mode, so wakeup latency is greatly reduced, at the cost of additional
 *    energy consumption.  This also prevents the CORE clockdomain from
 *    entering idle.
 */
#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE		BIT(0)

/*
 * Prevent PER OFF if CORE is not in RETention or OFF as this would
 * disable PER wakeups completely.
 */
static struct omap3_idle_statedata omap3_idle_data[] = {
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
		/* In C1 do not allow PER state lower than CORE state */
		.per_min_state = PWRDM_POWER_ON,
		.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
	},
	{
		.mpu_state = PWRDM_POWER_ON,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_ON,
		.per_min_state = PWRDM_POWER_RET,
	},
	{
		.mpu_state = PWRDM_POWER_RET,
		.core_state = PWRDM_POWER_RET,
		.per_min_state = PWRDM_POWER_OFF,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_RET,
		.per_min_state = PWRDM_POWER_OFF,
	},
	{
		.mpu_state = PWRDM_POWER_OFF,
		.core_state = PWRDM_POWER_OFF,
		.per_min_state = PWRDM_POWER_OFF,
	},
};

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv,
			    int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	int error;

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
		clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
	} else {
		pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
		pwrdm_set_next_pwrst(core_pd, cx->core_state);
	}

	/*
	 * Call idle CPU PM enter notifier chain so that
	 * VFP context is saved.
	 */
	if (cx->mpu_state == PWRDM_POWER_OFF) {
		error = cpu_pm_enter();
		if (error)
			goto out_clkdm_set;
	}

	/* Execute ARM wfi */
	omap_sram_idle(true);

	/*
	 * Call idle CPU PM enter notifier chain to restore
	 * VFP context.
	 */
	if (cx->mpu_state == PWRDM_POWER_OFF &&
	    pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
		cpu_pm_exit();

out_clkdm_set:
	/* Re-allow idle for C1 */
	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
		clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);

return_sleep_time:

	return index;
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			    struct cpuidle_driver *drv, int index)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int idx;
	int next_index = 0; /* C1 is the default value */

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state))
		return index;

	/*
	 * Drop to next valid state.
	 * Start search from the next (lower) state.
	 */
	for (idx = index - 1; idx >= 0; idx--) {
		cx = &omap3_idle_data[idx];
		if ((cx->mpu_state >= mpu_deepest_state) &&
		    (cx->core_state >= core_deepest_state)) {
			next_index = idx;
			break;
		}
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
			       struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx, ret;
	u8 per_next_state, per_saved_state;
	struct omap3_idle_statedata *cx;

	/*
	 * Use only C1 if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
		new_state_idx = drv->safe_state_index;
	else
		new_state_idx = next_valid_state(dev, drv, index);

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/* Program PER state */
	cx = &omap3_idle_data[new_state_idx];

	per_next_state = pwrdm_read_next_pwrst(per_pd);
	per_saved_state = per_next_state;
	if (per_next_state < cx->per_min_state) {
		per_next_state = cx->per_min_state;
		pwrdm_set_next_pwrst(per_pd, per_next_state);
	}

	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

static struct cpuidle_driver omap3_idle_driver = {
	.name             = "omap3_idle",
	.owner            = THIS_MODULE,
	.states = {
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2 + 2,
			.target_residency = 5,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10 + 10,
			.target_residency = 30,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 50 + 50,
			.target_residency = 300,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 1500 + 1800,
			.target_residency = 4000,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 2500 + 7500,
			.target_residency = 12000,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 3000 + 8500,
			.target_residency = 15000,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 10000 + 30000,
			.target_residency = 30000,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/*
 * Numbers based on measurements made in October 2009 for PM optimized kernel
 * with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
 * and worst case latencies).
 */
static struct cpuidle_driver omap3430_idle_driver = {
	.name             = "omap3430_idle",
	.owner            = THIS_MODULE,
	.states = {
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 110 + 162,
			.target_residency = 5,
			.name		  = "C1",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 106 + 180,
			.target_residency = 309,
			.name		  = "C2",
			.desc		  = "MPU ON + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 107 + 410,
			.target_residency = 46057,
			.name		  = "C3",
			.desc		  = "MPU RET + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 121 + 3374,
			.target_residency = 46057,
			.name		  = "C4",
			.desc		  = "MPU OFF + CORE ON",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 855 + 1146,
			.target_residency = 46057,
			.name		  = "C5",
			.desc		  = "MPU RET + CORE RET",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 7580 + 4134,
			.target_residency = 484329,
			.name		  = "C6",
			.desc		  = "MPU OFF + CORE RET",
		},
		{
			.flags		  = CPUIDLE_FLAG_RCU_IDLE,
			.enter		  = omap3_enter_idle_bm,
			.exit_latency	  = 7505 + 15274,
			.target_residency = 484329,
			.name		  = "C7",
			.desc		  = "MPU OFF + CORE OFF",
		},
	},
	.state_count = ARRAY_SIZE(omap3_idle_data),
	.safe_state_index = 0,
};

/* Public functions */

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");

	if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
		return -ENODEV;

	if (cpu_is_omap3430())
		return cpuidle_register(&omap3430_idle_driver, NULL);
	else
		return cpuidle_register(&omap3_idle_driver, NULL);
}
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
99e6a4d2 RN	2	/*
	3	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	4	*
	5	* OMAP3 CPU IDLE Routines
	6	*
	7	* Copyright (C) 2008 Texas Instruments, Inc.
	8	* Rajendra Nayak <rnayak@ti.com>
	9	*
	10	* Copyright (C) 2007 Texas Instruments, Inc.
	11	* Karthik Dasu <karthik-dp@ti.com>
	12	*
	13	* Copyright (C) 2006 Nokia Corporation
	14	* Tony Lindgren <tony@atomide.com>
	15	*
	16	* Copyright (C) 2005 Texas Instruments, Inc.
	17	* Richard Woodruff <r-woodruff2@ti.com>
	18	*
	19	* Based on pm.c for omap2
99e6a4d2 RN	20	*/
99e6a4d2 RN	21
cf22854c	22	#include <linux/sched.h>
99e6a4d2	23	#include <linux/cpuidle.h>
5698eb4e	24	#include <linux/export.h>
ff819da4	25	#include <linux/cpu_pm.h>
472a85f7	26	#include <asm/cpuidle.h>
99e6a4d2	27
72e06d08	28	#include "powerdomain.h"
1540f214	29	#include "clockdomain.h"
99e6a4d2	30
c98e2230	31	#include "pm.h"
4814ced5	32	#include "control.h"
ba8bb18a	33	#include "common.h"
98f42221	34	#include "soc.h"
c98e2230	35
badc303a JP	36	/* Mach specific information to be recorded in the C-state driver_data */
badc303a JP	37	struct omap3_idle_statedata {
fd6b42a5 PW	38	u8 mpu_state;
	39	u8 core_state;
	40	u8 per_min_state;
1cd96478	41	u8 flags;
badc303a	42	};
0c2487f6	43
9db316b6 PW	44	static struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
9db316b6 PW	45
1cd96478 PW	46	/*
	47	* Possible flag bits for struct omap3_idle_statedata.flags:
	48	*
	49	* OMAP_CPUIDLE_CX_NO_CLKDM_IDLE: don't allow the MPU clockdomain to go
	50	* inactive. This in turn prevents the MPU DPLL from entering autoidle
	51	* mode, so wakeup latency is greatly reduced, at the cost of additional
	52	* energy consumption. This also prevents the CORE clockdomain from
	53	* entering idle.
	54	*/
	55	#define OMAP_CPUIDLE_CX_NO_CLKDM_IDLE BIT(0)
	56
fd6b42a5 PW	57	/*
	58	* Prevent PER OFF if CORE is not in RETention or OFF as this would
	59	* disable PER wakeups completely.
	60	*/
97abc496	61	static struct omap3_idle_statedata omap3_idle_data[] = {
88c377dd DL	62	{
	63	.mpu_state = PWRDM_POWER_ON,
	64	.core_state = PWRDM_POWER_ON,
fd6b42a5 PW	65	/* In C1 do not allow PER state lower than CORE state */
fd6b42a5 PW	66	.per_min_state = PWRDM_POWER_ON,
1cd96478	67	.flags = OMAP_CPUIDLE_CX_NO_CLKDM_IDLE,
88c377dd DL	68	},
	69	{
	70	.mpu_state = PWRDM_POWER_ON,
	71	.core_state = PWRDM_POWER_ON,
fd6b42a5	72	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	73	},
	74	{
	75	.mpu_state = PWRDM_POWER_RET,
	76	.core_state = PWRDM_POWER_ON,
fd6b42a5	77	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	78	},
	79	{
	80	.mpu_state = PWRDM_POWER_OFF,
	81	.core_state = PWRDM_POWER_ON,
fd6b42a5	82	.per_min_state = PWRDM_POWER_RET,
88c377dd DL	83	},
	84	{
	85	.mpu_state = PWRDM_POWER_RET,
	86	.core_state = PWRDM_POWER_RET,
fd6b42a5	87	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	88	},
	89	{
	90	.mpu_state = PWRDM_POWER_OFF,
	91	.core_state = PWRDM_POWER_RET,
fd6b42a5	92	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	93	},
	94	{
	95	.mpu_state = PWRDM_POWER_OFF,
	96	.core_state = PWRDM_POWER_OFF,
fd6b42a5	97	.per_min_state = PWRDM_POWER_OFF,
88c377dd DL	98	},
88c377dd DL	99	};
badc303a	100
3dcb9f1b DL	101	/**
	102	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	103	* @dev: cpuidle device
	104	* @drv: cpuidle driver
	105	* @index: the index of state to be entered
	106	*/
	107	static int omap3_enter_idle(struct cpuidle_device *dev,
	108	struct cpuidle_driver *drv,
	109	int index)
99e6a4d2	110	{
6622ac55	111	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
55be2f50	112	int error;
99e6a4d2	113
cf22854c	114	if (omap_irq_pending() \|\| need_resched())
20b01669	115	goto return_sleep_time;
99e6a4d2	116
badc303a	117	/* Deny idle for C1 */
1cd96478	118	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE) {
05011f71	119	clkdm_deny_idle(mpu_pd->pwrdm_clkdms[0]);
1cd96478 PW	120	} else {
	121	pwrdm_set_next_pwrst(mpu_pd, cx->mpu_state);
	122	pwrdm_set_next_pwrst(core_pd, cx->core_state);
06d8f065 PDS	123	}
06d8f065 PDS	124
ff819da4 SS	125	/*
	126	* Call idle CPU PM enter notifier chain so that
	127	* VFP context is saved.
	128	*/
55be2f50 TL	129	if (cx->mpu_state == PWRDM_POWER_OFF) {
	130	error = cpu_pm_enter();
	131	if (error)
	132	goto out_clkdm_set;
	133	}
ff819da4	134
99e6a4d2	135	/* Execute ARM wfi */
8c0956aa	136	omap_sram_idle(true);
99e6a4d2	137
ff819da4 SS	138	/*
	139	* Call idle CPU PM enter notifier chain to restore
	140	* VFP context.
	141	*/
1cd96478 PW	142	if (cx->mpu_state == PWRDM_POWER_OFF &&
1cd96478 PW	143	pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
ff819da4 SS	144	cpu_pm_exit();
ff819da4 SS	145
55be2f50	146	out_clkdm_set:
badc303a	147	/* Re-allow idle for C1 */
1cd96478	148	if (cx->flags & OMAP_CPUIDLE_CX_NO_CLKDM_IDLE)
05011f71	149	clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
06d8f065	150
20b01669	151	return_sleep_time:
99e6a4d2	152
e978aa7d	153	return index;
99e6a4d2 RN	154	}
99e6a4d2 RN	155
6af83b38	156	/**
04908918	157	* next_valid_state - Find next valid C-state
6af83b38	158	* @dev: cpuidle device
46bcfad7	159	* @drv: cpuidle driver
e978aa7d	160	* @index: Index of currently selected c-state
6af83b38	161	*
e978aa7d DD	162	* If the state corresponding to index is valid, index is returned back
	163	* to the caller. Else, this function searches for a lower c-state which is
	164	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	165	*
	166	* A state is valid if the 'valid' field is enabled and
	167	* if it satisfies the enable_off_mode condition.
6af83b38	168	*/
e978aa7d	169	static int next_valid_state(struct cpuidle_device *dev,
e92a4586	170	struct cpuidle_driver *drv, int index)
6af83b38	171	{
6622ac55	172	struct omap3_idle_statedata *cx = &omap3_idle_data[index];
04908918 JP	173	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	174	u32 core_deepest_state = PWRDM_POWER_RET;
e92a4586	175	int idx;
063a5d01	176	int next_index = 0; /* C1 is the default value */
04908918 JP	177
	178	if (enable_off_mode) {
	179	mpu_deepest_state = PWRDM_POWER_OFF;
	180	/*
	181	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	182	* CORE OFF mode is not supported in a stable form, restrict
	183	* instead the CORE state to RET.
	184	*/
	185	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	186	core_deepest_state = PWRDM_POWER_OFF;
	187	}
6af83b38 SP	188
6af83b38 SP	189	/* Check if current state is valid */
f79b5d8a	190	if ((cx->mpu_state >= mpu_deepest_state) &&
e92a4586	191	(cx->core_state >= core_deepest_state))
e978aa7d	192	return index;
6af83b38	193
e92a4586 DL	194	/*
	195	* Drop to next valid state.
	196	* Start search from the next (lower) state.
	197	*/
	198	for (idx = index - 1; idx >= 0; idx--) {
1cd96478	199	cx = &omap3_idle_data[idx];
e92a4586 DL	200	if ((cx->mpu_state >= mpu_deepest_state) &&
	201	(cx->core_state >= core_deepest_state)) {
	202	next_index = idx;
	203	break;
6af83b38	204	}
6af83b38 SP	205	}
6af83b38 SP	206
e978aa7d	207	return next_index;
6af83b38 SP	208	}
6af83b38 SP	209
99e6a4d2 RN	210	/**
	211	* omap3_enter_idle_bm - Checks for any bus activity
	212	* @dev: cpuidle device
46bcfad7	213	* @drv: cpuidle driver
e978aa7d	214	* @index: array index of target state to be programmed
99e6a4d2	215	*
badc303a JP	216	* This function checks for any pending activity and then programs
badc303a JP	217	* the device to the specified or a safer state.
99e6a4d2 RN	218	*/
99e6a4d2 RN	219	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
13d65c89	220	struct cpuidle_driver *drv,
e978aa7d	221	int index)
99e6a4d2	222	{
fd6b42a5 PW	223	int new_state_idx, ret;
fd6b42a5 PW	224	u8 per_next_state, per_saved_state;
badc303a	225	struct omap3_idle_statedata *cx;
0f724ed9	226
e7410cf7	227	/*
13d65c89	228	* Use only C1 if CAM is active.
e7410cf7 KH	229	* CAM does not have wakeup capability in OMAP3.
e7410cf7 KH	230	*/
13d65c89	231	if (pwrdm_read_pwrst(cam_pd) == PWRDM_POWER_ON)
46bcfad7	232	new_state_idx = drv->safe_state_index;
13d65c89 JP	233	else
13d65c89 JP	234	new_state_idx = next_valid_state(dev, drv, index);
e7410cf7	235
c6cd91de JP	236	/*
	237	* FIXME: we currently manage device-specific idle states
	238	* for PER and CORE in combination with CPU-specific
	239	* idle states. This is wrong, and device-specific
	240	* idle management needs to be separated out into
	241	* its own code.
	242	*/
	243
13d65c89 JP	244	/* Program PER state */
13d65c89 JP	245	cx = &omap3_idle_data[new_state_idx];
0f724ed9	246
fd6b42a5 PW	247	per_next_state = pwrdm_read_next_pwrst(per_pd);
	248	per_saved_state = per_next_state;
	249	if (per_next_state < cx->per_min_state) {
	250	per_next_state = cx->per_min_state;
e7410cf7	251	pwrdm_set_next_pwrst(per_pd, per_next_state);
fd6b42a5	252	}
e7410cf7	253
46bcfad7	254	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	255
	256	/* Restore original PER state if it was modified */
	257	if (per_next_state != per_saved_state)
	258	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	259
	260	return ret;
99e6a4d2 RN	261	}
99e6a4d2 RN	262
9db316b6	263	static struct cpuidle_driver omap3_idle_driver = {
0d975589 DL	264	.name = "omap3_idle",
0d975589 DL	265	.owner = THIS_MODULE,
200dd520 DL	266	.states = {
200dd520 DL	267	{
4d1be9e7	268	.flags = CPUIDLE_FLAG_RCU_IDLE,
13d65c89	269	.enter = omap3_enter_idle_bm,
200dd520 DL	270	.exit_latency = 2 + 2,
200dd520 DL	271	.target_residency = 5,
200dd520 DL	272	.name = "C1",
	273	.desc = "MPU ON + CORE ON",
	274	},
	275	{
4d1be9e7	276	.flags = CPUIDLE_FLAG_RCU_IDLE,
200dd520 DL	277	.enter = omap3_enter_idle_bm,
	278	.exit_latency = 10 + 10,
	279	.target_residency = 30,
200dd520 DL	280	.name = "C2",
	281	.desc = "MPU ON + CORE ON",
	282	},
	283	{
4d1be9e7	284	.flags = CPUIDLE_FLAG_RCU_IDLE,
200dd520 DL	285	.enter = omap3_enter_idle_bm,
	286	.exit_latency = 50 + 50,
	287	.target_residency = 300,
200dd520 DL	288	.name = "C3",
	289	.desc = "MPU RET + CORE ON",
	290	},
	291	{
4d1be9e7	292	.flags = CPUIDLE_FLAG_RCU_IDLE,
200dd520 DL	293	.enter = omap3_enter_idle_bm,
	294	.exit_latency = 1500 + 1800,
	295	.target_residency = 4000,
200dd520 DL	296	.name = "C4",
	297	.desc = "MPU OFF + CORE ON",
	298	},
	299	{
4d1be9e7	300	.flags = CPUIDLE_FLAG_RCU_IDLE,
200dd520 DL	301	.enter = omap3_enter_idle_bm,
	302	.exit_latency = 2500 + 7500,
	303	.target_residency = 12000,
200dd520 DL	304	.name = "C5",
	305	.desc = "MPU RET + CORE RET",
	306	},
	307	{
4d1be9e7	308	.flags = CPUIDLE_FLAG_RCU_IDLE,
200dd520 DL	309	.enter = omap3_enter_idle_bm,
	310	.exit_latency = 3000 + 8500,
	311	.target_residency = 15000,
200dd520 DL	312	.name = "C6",
	313	.desc = "MPU OFF + CORE RET",
	314	},
	315	{
4d1be9e7	316	.flags = CPUIDLE_FLAG_RCU_IDLE,
200dd520 DL	317	.enter = omap3_enter_idle_bm,
	318	.exit_latency = 10000 + 30000,
	319	.target_residency = 30000,
200dd520 DL	320	.name = "C7",
	321	.desc = "MPU OFF + CORE OFF",
	322	},
	323	},
88c377dd	324	.state_count = ARRAY_SIZE(omap3_idle_data),
200dd520	325	.safe_state_index = 0,
99e6a4d2 RN	326	};
99e6a4d2 RN	327
98f42221 PR	328	/*
	329	* Numbers based on measurements made in October 2009 for PM optimized kernel
	330	* with CPU freq enabled on device Nokia N900. Assumes OPP2 (main idle OPP,
	331	* and worst case latencies).
	332	*/
	333	static struct cpuidle_driver omap3430_idle_driver = {
	334	.name = "omap3430_idle",
	335	.owner = THIS_MODULE,
	336	.states = {
	337	{
4d1be9e7	338	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	339	.enter = omap3_enter_idle_bm,
	340	.exit_latency = 110 + 162,
	341	.target_residency = 5,
	342	.name = "C1",
	343	.desc = "MPU ON + CORE ON",
	344	},
	345	{
4d1be9e7	346	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	347	.enter = omap3_enter_idle_bm,
	348	.exit_latency = 106 + 180,
	349	.target_residency = 309,
	350	.name = "C2",
	351	.desc = "MPU ON + CORE ON",
	352	},
	353	{
4d1be9e7	354	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	355	.enter = omap3_enter_idle_bm,
	356	.exit_latency = 107 + 410,
	357	.target_residency = 46057,
	358	.name = "C3",
	359	.desc = "MPU RET + CORE ON",
	360	},
	361	{
4d1be9e7	362	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	363	.enter = omap3_enter_idle_bm,
	364	.exit_latency = 121 + 3374,
	365	.target_residency = 46057,
	366	.name = "C4",
	367	.desc = "MPU OFF + CORE ON",
	368	},
	369	{
4d1be9e7	370	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	371	.enter = omap3_enter_idle_bm,
	372	.exit_latency = 855 + 1146,
	373	.target_residency = 46057,
	374	.name = "C5",
	375	.desc = "MPU RET + CORE RET",
	376	},
	377	{
4d1be9e7	378	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	379	.enter = omap3_enter_idle_bm,
	380	.exit_latency = 7580 + 4134,
	381	.target_residency = 484329,
	382	.name = "C6",
	383	.desc = "MPU OFF + CORE RET",
	384	},
	385	{
4d1be9e7	386	.flags = CPUIDLE_FLAG_RCU_IDLE,
98f42221 PR	387	.enter = omap3_enter_idle_bm,
	388	.exit_latency = 7505 + 15274,
	389	.target_residency = 484329,
	390	.name = "C7",
	391	.desc = "MPU OFF + CORE OFF",
	392	},
	393	},
	394	.state_count = ARRAY_SIZE(omap3_idle_data),
	395	.safe_state_index = 0,
	396	};
	397
9db316b6 PW	398	/* Public functions */
9db316b6 PW	399
99e6a4d2 RN	400	/**
	401	* omap3_idle_init - Init routine for OMAP3 idle
	402	*
badc303a	403	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	404	* framework with the valid set of states.
99e6a4d2 RN	405	*/
0343371e	406	int __init omap3_idle_init(void)
99e6a4d2	407	{
99e6a4d2	408	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	409	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	410	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	411	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	412
daa37cee DL	413	if (!mpu_pd \|\| !core_pd \|\| !per_pd \|\| !cam_pd)
	414	return -ENODEV;
	415
98f42221 PR	416	if (cpu_is_omap3430())
	417	return cpuidle_register(&omap3430_idle_driver, NULL);
	418	else
	419	return cpuidle_register(&omap3_idle_driver, NULL);
99e6a4d2	420	}