[linux-2.6-block.git] / arch / arm / mach-omap2 / cpuidle34xx.c

/*
 * linux/arch/arm/mach-omap2/cpuidle34xx.c
 *
 * OMAP3 CPU IDLE Routines
 *
 * Copyright (C) 2008 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
 * Copyright (C) 2007 Texas Instruments, Inc.
 * Karthik Dasu <karthik-dp@ti.com>
 *
 * Copyright (C) 2006 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 *
 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap2
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/sched.h>
#include <linux/cpuidle.h>
#include <linux/export.h>

#include <plat/prcm.h>
#include <plat/irqs.h>
#include "powerdomain.h"
#include "clockdomain.h"
#include <plat/serial.h>

#include "pm.h"
#include "control.h"

#ifdef CONFIG_CPU_IDLE

/*
 * The latencies/thresholds for various C states have
 * to be configured from the respective board files.
 * These are some default values (which might not provide
 * the best power savings) used on boards which do not
 * pass these details from the board file.
 */
static struct cpuidle_params cpuidle_params_table[] = {
	/* C1 */
	{2 + 2, 5, 1},
	/* C2 */
	{10 + 10, 30, 1},
	/* C3 */
	{50 + 50, 300, 1},
	/* C4 */
	{1500 + 1800, 4000, 1},
	/* C5 */
	{2500 + 7500, 12000, 1},
	/* C6 */
	{3000 + 8500, 15000, 1},
	/* C7 */
	{10000 + 30000, 300000, 1},
};
#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)

/* Mach specific information to be recorded in the C-state driver_data */
struct omap3_idle_statedata {
	u32 mpu_state;
	u32 core_state;
	u8 valid;
};
struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];

struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;

static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_allow_idle(clkdm);
	return 0;
}

static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
				struct clockdomain *clkdm)
{
	clkdm_deny_idle(clkdm);
	return 0;
}

/**
 * omap3_enter_idle - Programs OMAP3 to enter the specified state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: the index of state to be entered
 *
 * Called from the CPUidle framework to program the device to the
 * specified target state selected by the governor.
 */
static int omap3_enter_idle(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
				int index)
{
	struct omap3_idle_statedata *cx =
			cpuidle_get_statedata(&dev->states_usage[index]);
	struct timespec ts_preidle, ts_postidle, ts_idle;
	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
	int idle_time;

	/* Used to keep track of the total time in idle */
	getnstimeofday(&ts_preidle);

	local_irq_disable();
	local_fiq_disable();

	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
	pwrdm_set_next_pwrst(core_pd, core_state);

	if (omap_irq_pending() || need_resched())
		goto return_sleep_time;

	/* Deny idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	}

	/* Execute ARM wfi */
	omap_sram_idle();

	/* Re-allow idle for C1 */
	if (index == 0) {
		pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
		pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	}

return_sleep_time:
	getnstimeofday(&ts_postidle);
	ts_idle = timespec_sub(ts_postidle, ts_preidle);

	local_irq_enable();
	local_fiq_enable();

	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
								USEC_PER_SEC;

	/* Update cpuidle counters */
	dev->last_residency = idle_time;

	return index;
}

/**
 * next_valid_state - Find next valid C-state
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: Index of currently selected c-state
 *
 * If the state corresponding to index is valid, index is returned back
 * to the caller. Else, this function searches for a lower c-state which is
 * still valid (as defined in omap3_power_states[]) and returns its index.
 *
 * A state is valid if the 'valid' field is enabled and
 * if it satisfies the enable_off_mode condition.
 */
static int next_valid_state(struct cpuidle_device *dev,
			struct cpuidle_driver *drv,
				int index)
{
	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
	struct cpuidle_state *curr = &drv->states[index];
	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
	u32 mpu_deepest_state = PWRDM_POWER_RET;
	u32 core_deepest_state = PWRDM_POWER_RET;
	int next_index = -1;

	if (enable_off_mode) {
		mpu_deepest_state = PWRDM_POWER_OFF;
		/*
		 * Erratum i583: valable for ES rev < Es1.2 on 3630.
		 * CORE OFF mode is not supported in a stable form, restrict
		 * instead the CORE state to RET.
		 */
		if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
			core_deepest_state = PWRDM_POWER_OFF;
	}

	/* Check if current state is valid */
	if ((cx->valid) &&
	    (cx->mpu_state >= mpu_deepest_state) &&
	    (cx->core_state >= core_deepest_state)) {
		return index;
	} else {
		int idx = OMAP3_NUM_STATES - 1;

		/* Reach the current state starting at highest C-state */
		for (; idx >= 0; idx--) {
			if (&drv->states[idx] == curr) {
				next_index = idx;
				break;
			}
		}

		/* Should never hit this condition */
		WARN_ON(next_index == -1);

		/*
		 * Drop to next valid state.
		 * Start search from the next (lower) state.
		 */
		idx--;
		for (; idx >= 0; idx--) {
			cx = cpuidle_get_statedata(&dev->states_usage[idx]);
			if ((cx->valid) &&
			    (cx->mpu_state >= mpu_deepest_state) &&
			    (cx->core_state >= core_deepest_state)) {
				next_index = idx;
				break;
			}
		}
		/*
		 * C1 is always valid.
		 * So, no need to check for 'next_index == -1' outside
		 * this loop.
		 */
	}

	return next_index;
}

/**
 * omap3_enter_idle_bm - Checks for any bus activity
 * @dev: cpuidle device
 * @drv: cpuidle driver
 * @index: array index of target state to be programmed
 *
 * This function checks for any pending activity and then programs
 * the device to the specified or a safer state.
 */
static int omap3_enter_idle_bm(struct cpuidle_device *dev,
				struct cpuidle_driver *drv,
			       int index)
{
	int new_state_idx;
	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
	struct omap3_idle_statedata *cx;
	int ret;

	if (!omap3_can_sleep()) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * Prevent idle completely if CAM is active.
	 * CAM does not have wakeup capability in OMAP3.
	 */
	cam_state = pwrdm_read_pwrst(cam_pd);
	if (cam_state == PWRDM_POWER_ON) {
		new_state_idx = drv->safe_state_index;
		goto select_state;
	}

	/*
	 * FIXME: we currently manage device-specific idle states
	 *        for PER and CORE in combination with CPU-specific
	 *        idle states.  This is wrong, and device-specific
	 *        idle management needs to be separated out into
	 *        its own code.
	 */

	/*
	 * Prevent PER off if CORE is not in retention or off as this
	 * would disable PER wakeups completely.
	 */
	cx = cpuidle_get_statedata(&dev->states_usage[index]);
	core_next_state = cx->core_state;
	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
	if ((per_next_state == PWRDM_POWER_OFF) &&
	    (core_next_state > PWRDM_POWER_RET))
		per_next_state = PWRDM_POWER_RET;

	/* Are we changing PER target state? */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_next_state);

	new_state_idx = next_valid_state(dev, drv, index);

select_state:
	ret = omap3_enter_idle(dev, drv, new_state_idx);

	/* Restore original PER state if it was modified */
	if (per_next_state != per_saved_state)
		pwrdm_set_next_pwrst(per_pd, per_saved_state);

	return ret;
}

DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);

void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
{
	int i;

	if (!cpuidle_board_params)
		return;

	for (i = 0; i < OMAP3_NUM_STATES; i++) {
		cpuidle_params_table[i].valid =	cpuidle_board_params[i].valid;
		cpuidle_params_table[i].exit_latency =
			cpuidle_board_params[i].exit_latency;
		cpuidle_params_table[i].target_residency =
			cpuidle_board_params[i].target_residency;
	}
	return;
}

struct cpuidle_driver omap3_idle_driver = {
	.name = 	"omap3_idle",
	.owner = 	THIS_MODULE,
};

/* Helper to fill the C-state common data*/
static inline void _fill_cstate(struct cpuidle_driver *drv,
					int idx, const char *descr)
{
	struct cpuidle_state *state = &drv->states[idx];

	state->exit_latency	= cpuidle_params_table[idx].exit_latency;
	state->target_residency	= cpuidle_params_table[idx].target_residency;
	state->flags		= CPUIDLE_FLAG_TIME_VALID;
	state->enter		= omap3_enter_idle_bm;
	sprintf(state->name, "C%d", idx + 1);
	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);

}

/* Helper to register the driver_data */
static inline struct omap3_idle_statedata *_fill_cstate_usage(
					struct cpuidle_device *dev,
					int idx)
{
	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];

	cx->valid		= cpuidle_params_table[idx].valid;
	cpuidle_set_statedata(state_usage, cx);

	return cx;
}

/**
 * omap3_idle_init - Init routine for OMAP3 idle
 *
 * Registers the OMAP3 specific cpuidle driver to the cpuidle
 * framework with the valid set of states.
 */
int __init omap3_idle_init(void)
{
	struct cpuidle_device *dev;
	struct cpuidle_driver *drv = &omap3_idle_driver;
	struct omap3_idle_statedata *cx;

	mpu_pd = pwrdm_lookup("mpu_pwrdm");
	core_pd = pwrdm_lookup("core_pwrdm");
	per_pd = pwrdm_lookup("per_pwrdm");
	cam_pd = pwrdm_lookup("cam_pwrdm");


	drv->safe_state_index = -1;
	dev = &per_cpu(omap3_idle_dev, smp_processor_id());

	/* C1 . MPU WFI + Core active */
	_fill_cstate(drv, 0, "MPU ON + CORE ON");
	(&drv->states[0])->enter = omap3_enter_idle;
	drv->safe_state_index = 0;
	cx = _fill_cstate_usage(dev, 0);
	cx->valid = 1;	/* C1 is always valid */
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C2 . MPU WFI + Core inactive */
	_fill_cstate(drv, 1, "MPU ON + CORE ON");
	cx = _fill_cstate_usage(dev, 1);
	cx->mpu_state = PWRDM_POWER_ON;
	cx->core_state = PWRDM_POWER_ON;

	/* C3 . MPU CSWR + Core inactive */
	_fill_cstate(drv, 2, "MPU RET + CORE ON");
	cx = _fill_cstate_usage(dev, 2);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_ON;

	/* C4 . MPU OFF + Core inactive */
	_fill_cstate(drv, 3, "MPU OFF + CORE ON");
	cx = _fill_cstate_usage(dev, 3);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_ON;

	/* C5 . MPU RET + Core RET */
	_fill_cstate(drv, 4, "MPU RET + CORE RET");
	cx = _fill_cstate_usage(dev, 4);
	cx->mpu_state = PWRDM_POWER_RET;
	cx->core_state = PWRDM_POWER_RET;

	/* C6 . MPU OFF + Core RET */
	_fill_cstate(drv, 5, "MPU OFF + CORE RET");
	cx = _fill_cstate_usage(dev, 5);
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_RET;

	/* C7 . MPU OFF + Core OFF */
	_fill_cstate(drv, 6, "MPU OFF + CORE OFF");
	cx = _fill_cstate_usage(dev, 6);
	/*
	 * Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	 * enable OFF mode in a stable form for previous revisions.
	 * We disable C7 state as a result.
	 */
	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
		cx->valid = 0;
		pr_warn("%s: core off state C7 disabled due to i583\n",
			__func__);
	}
	cx->mpu_state = PWRDM_POWER_OFF;
	cx->core_state = PWRDM_POWER_OFF;

	drv->state_count = OMAP3_NUM_STATES;
	cpuidle_register_driver(&omap3_idle_driver);

	dev->state_count = OMAP3_NUM_STATES;
	if (cpuidle_register_device(dev)) {
		printk(KERN_ERR "%s: CPUidle register device failed\n",
		       __func__);
		return -EIO;
	}

	return 0;
}
#else
int __init omap3_idle_init(void)
{
	return 0;
}
#endif /* CONFIG_CPU_IDLE */
Commit	Line	Data
99e6a4d2 RN	1	/*
	2	* linux/arch/arm/mach-omap2/cpuidle34xx.c
	3	*
	4	* OMAP3 CPU IDLE Routines
	5	*
	6	* Copyright (C) 2008 Texas Instruments, Inc.
	7	* Rajendra Nayak <rnayak@ti.com>
	8	*
	9	* Copyright (C) 2007 Texas Instruments, Inc.
	10	* Karthik Dasu <karthik-dp@ti.com>
	11	*
	12	* Copyright (C) 2006 Nokia Corporation
	13	* Tony Lindgren <tony@atomide.com>
	14	*
	15	* Copyright (C) 2005 Texas Instruments, Inc.
	16	* Richard Woodruff <r-woodruff2@ti.com>
	17	*
	18	* Based on pm.c for omap2
	19	*
	20	* This program is free software; you can redistribute it and/or modify
	21	* it under the terms of the GNU General Public License version 2 as
	22	* published by the Free Software Foundation.
	23	*/
	24
cf22854c	25	#include <linux/sched.h>
99e6a4d2	26	#include <linux/cpuidle.h>
5698eb4e	27	#include <linux/export.h>
99e6a4d2 RN	28
99e6a4d2 RN	29	#include <plat/prcm.h>
20b01669	30	#include <plat/irqs.h>
72e06d08	31	#include "powerdomain.h"
1540f214	32	#include "clockdomain.h"
0f724ed9	33	#include <plat/serial.h>
99e6a4d2	34
c98e2230	35	#include "pm.h"
4814ced5	36	#include "control.h"
c98e2230	37
99e6a4d2 RN	38	#ifdef CONFIG_CPU_IDLE
99e6a4d2 RN	39
bb4de3df KH	40	/*
	41	* The latencies/thresholds for various C states have
	42	* to be configured from the respective board files.
	43	* These are some default values (which might not provide
	44	* the best power savings) used on boards which do not
	45	* pass these details from the board file.
	46	*/
	47	static struct cpuidle_params cpuidle_params_table[] = {
	48	/* C1 */
866ba0ef	49	{2 + 2, 5, 1},
bb4de3df	50	/* C2 */
866ba0ef	51	{10 + 10, 30, 1},
bb4de3df	52	/* C3 */
866ba0ef	53	{50 + 50, 300, 1},
bb4de3df	54	/* C4 */
866ba0ef	55	{1500 + 1800, 4000, 1},
bb4de3df	56	/* C5 */
866ba0ef	57	{2500 + 7500, 12000, 1},
bb4de3df	58	/* C6 */
866ba0ef	59	{3000 + 8500, 15000, 1},
bb4de3df	60	/* C7 */
866ba0ef	61	{10000 + 30000, 300000, 1},
bb4de3df	62	};
badc303a JP	63	#define OMAP3_NUM_STATES ARRAY_SIZE(cpuidle_params_table)
	64
	65	/* Mach specific information to be recorded in the C-state driver_data */
	66	struct omap3_idle_statedata {
	67	u32 mpu_state;
	68	u32 core_state;
	69	u8 valid;
	70	};
	71	struct omap3_idle_statedata omap3_idle_data[OMAP3_NUM_STATES];
	72
	73	struct powerdomain mpu_pd, core_pd, per_pd, cam_pd;
bb4de3df	74
06d8f065 PDS	75	static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
	76	struct clockdomain *clkdm)
	77	{
5cd1937b	78	clkdm_allow_idle(clkdm);
06d8f065 PDS	79	return 0;
	80	}
	81
	82	static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
	83	struct clockdomain *clkdm)
	84	{
5cd1937b	85	clkdm_deny_idle(clkdm);
06d8f065 PDS	86	return 0;
	87	}
	88
99e6a4d2 RN	89	/**
	90	* omap3_enter_idle - Programs OMAP3 to enter the specified state
	91	* @dev: cpuidle device
46bcfad7	92	* @drv: cpuidle driver
e978aa7d	93	* @index: the index of state to be entered
99e6a4d2 RN	94	*
	95	* Called from the CPUidle framework to program the device to the
	96	* specified target state selected by the governor.
	97	*/
	98	static int omap3_enter_idle(struct cpuidle_device *dev,
46bcfad7	99	struct cpuidle_driver *drv,
e978aa7d	100	int index)
99e6a4d2	101	{
e978aa7d	102	struct omap3_idle_statedata *cx =
4202735e	103	cpuidle_get_statedata(&dev->states_usage[index]);
99e6a4d2	104	struct timespec ts_preidle, ts_postidle, ts_idle;
c98e2230	105	u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
e978aa7d	106	int idle_time;
99e6a4d2	107
99e6a4d2 RN	108	/* Used to keep track of the total time in idle */
	109	getnstimeofday(&ts_preidle);
	110
	111	local_irq_disable();
	112	local_fiq_disable();
	113
7139178e JH	114	pwrdm_set_next_pwrst(mpu_pd, mpu_state);
7139178e JH	115	pwrdm_set_next_pwrst(core_pd, core_state);
20b01669	116
cf22854c	117	if (omap_irq_pending() \|\| need_resched())
20b01669	118	goto return_sleep_time;
99e6a4d2	119
badc303a	120	/* Deny idle for C1 */
e978aa7d	121	if (index == 0) {
06d8f065 PDS	122	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
	123	pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
	124	}
	125
99e6a4d2 RN	126	/* Execute ARM wfi */
	127	omap_sram_idle();
	128
badc303a	129	/* Re-allow idle for C1 */
e978aa7d	130	if (index == 0) {
06d8f065 PDS	131	pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
	132	pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
	133	}
	134
20b01669	135	return_sleep_time:
99e6a4d2 RN	136	getnstimeofday(&ts_postidle);
	137	ts_idle = timespec_sub(ts_postidle, ts_preidle);
	138
	139	local_irq_enable();
	140	local_fiq_enable();
	141
e978aa7d DD	142	idle_time = ts_idle.tv_nsec / NSEC_PER_USEC + ts_idle.tv_sec * \
	143	USEC_PER_SEC;
	144
	145	/* Update cpuidle counters */
	146	dev->last_residency = idle_time;
	147
	148	return index;
99e6a4d2 RN	149	}
99e6a4d2 RN	150
6af83b38	151	/**
04908918	152	* next_valid_state - Find next valid C-state
6af83b38	153	* @dev: cpuidle device
46bcfad7	154	* @drv: cpuidle driver
e978aa7d	155	* @index: Index of currently selected c-state
6af83b38	156	*
e978aa7d DD	157	* If the state corresponding to index is valid, index is returned back
	158	* to the caller. Else, this function searches for a lower c-state which is
	159	* still valid (as defined in omap3_power_states[]) and returns its index.
04908918 JP	160	*
	161	* A state is valid if the 'valid' field is enabled and
	162	* if it satisfies the enable_off_mode condition.
6af83b38	163	*/
e978aa7d	164	static int next_valid_state(struct cpuidle_device *dev,
46bcfad7	165	struct cpuidle_driver *drv,
e978aa7d	166	int index)
6af83b38	167	{
4202735e	168	struct cpuidle_state_usage *curr_usage = &dev->states_usage[index];
46bcfad7	169	struct cpuidle_state *curr = &drv->states[index];
4202735e	170	struct omap3_idle_statedata *cx = cpuidle_get_statedata(curr_usage);
04908918 JP	171	u32 mpu_deepest_state = PWRDM_POWER_RET;
04908918 JP	172	u32 core_deepest_state = PWRDM_POWER_RET;
e978aa7d	173	int next_index = -1;
04908918 JP	174
	175	if (enable_off_mode) {
	176	mpu_deepest_state = PWRDM_POWER_OFF;
	177	/*
	178	* Erratum i583: valable for ES rev < Es1.2 on 3630.
	179	* CORE OFF mode is not supported in a stable form, restrict
	180	* instead the CORE state to RET.
	181	*/
	182	if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
	183	core_deepest_state = PWRDM_POWER_OFF;
	184	}
6af83b38 SP	185
6af83b38 SP	186	/* Check if current state is valid */
04908918 JP	187	if ((cx->valid) &&
	188	(cx->mpu_state >= mpu_deepest_state) &&
	189	(cx->core_state >= core_deepest_state)) {
e978aa7d	190	return index;
6af83b38	191	} else {
badc303a	192	int idx = OMAP3_NUM_STATES - 1;
6af83b38	193
c6cd91de	194	/* Reach the current state starting at highest C-state */
badc303a	195	for (; idx >= 0; idx--) {
46bcfad7	196	if (&drv->states[idx] == curr) {
e978aa7d	197	next_index = idx;
6af83b38 SP	198	break;
	199	}
	200	}
	201
c6cd91de	202	/* Should never hit this condition */
e978aa7d	203	WARN_ON(next_index == -1);
6af83b38 SP	204
	205	/*
	206	* Drop to next valid state.
	207	* Start search from the next (lower) state.
	208	*/
	209	idx--;
badc303a	210	for (; idx >= 0; idx--) {
4202735e	211	cx = cpuidle_get_statedata(&dev->states_usage[idx]);
04908918 JP	212	if ((cx->valid) &&
	213	(cx->mpu_state >= mpu_deepest_state) &&
	214	(cx->core_state >= core_deepest_state)) {
e978aa7d	215	next_index = idx;
6af83b38 SP	216	break;
	217	}
	218	}
	219	/*
badc303a	220	* C1 is always valid.
e978aa7d DD	221	* So, no need to check for 'next_index == -1' outside
e978aa7d DD	222	* this loop.
6af83b38 SP	223	*/
	224	}
	225
e978aa7d	226	return next_index;
6af83b38 SP	227	}
6af83b38 SP	228
99e6a4d2 RN	229	/**
	230	* omap3_enter_idle_bm - Checks for any bus activity
	231	* @dev: cpuidle device
46bcfad7	232	* @drv: cpuidle driver
e978aa7d	233	* @index: array index of target state to be programmed
99e6a4d2	234	*
badc303a JP	235	* This function checks for any pending activity and then programs
badc303a JP	236	* the device to the specified or a safer state.
99e6a4d2 RN	237	*/
99e6a4d2 RN	238	static int omap3_enter_idle_bm(struct cpuidle_device *dev,
46bcfad7	239	struct cpuidle_driver *drv,
e978aa7d	240	int index)
99e6a4d2	241	{
e978aa7d	242	int new_state_idx;
c6cd91de	243	u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
badc303a	244	struct omap3_idle_statedata *cx;
e7410cf7	245	int ret;
0f724ed9	246
c6cd91de	247	if (!omap3_can_sleep()) {
46bcfad7	248	new_state_idx = drv->safe_state_index;
e7410cf7 KH	249	goto select_state;
	250	}
	251
e7410cf7 KH	252	/*
	253	* Prevent idle completely if CAM is active.
	254	* CAM does not have wakeup capability in OMAP3.
	255	*/
	256	cam_state = pwrdm_read_pwrst(cam_pd);
	257	if (cam_state == PWRDM_POWER_ON) {
46bcfad7	258	new_state_idx = drv->safe_state_index;
e7410cf7 KH	259	goto select_state;
	260	}
	261
c6cd91de JP	262	/*
	263	* FIXME: we currently manage device-specific idle states
	264	* for PER and CORE in combination with CPU-specific
	265	* idle states. This is wrong, and device-specific
	266	* idle management needs to be separated out into
	267	* its own code.
	268	*/
	269
e7410cf7 KH	270	/*
	271	* Prevent PER off if CORE is not in retention or off as this
	272	* would disable PER wakeups completely.
	273	*/
4202735e	274	cx = cpuidle_get_statedata(&dev->states_usage[index]);
c6cd91de	275	core_next_state = cx->core_state;
e7410cf7 KH	276	per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
e7410cf7 KH	277	if ((per_next_state == PWRDM_POWER_OFF) &&
65707fb3	278	(core_next_state > PWRDM_POWER_RET))
e7410cf7	279	per_next_state = PWRDM_POWER_RET;
0f724ed9	280
e7410cf7 KH	281	/* Are we changing PER target state? */
	282	if (per_next_state != per_saved_state)
	283	pwrdm_set_next_pwrst(per_pd, per_next_state);
	284
46bcfad7	285	new_state_idx = next_valid_state(dev, drv, index);
c6cd91de	286
e7410cf7	287	select_state:
46bcfad7	288	ret = omap3_enter_idle(dev, drv, new_state_idx);
e7410cf7 KH	289
	290	/* Restore original PER state if it was modified */
	291	if (per_next_state != per_saved_state)
	292	pwrdm_set_next_pwrst(per_pd, per_saved_state);
	293
	294	return ret;
99e6a4d2 RN	295	}
	296
	297	DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
	298
bb4de3df KH	299	void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
	300	{
	301	int i;
	302
	303	if (!cpuidle_board_params)
	304	return;
	305
badc303a JP	306	for (i = 0; i < OMAP3_NUM_STATES; i++) {
badc303a JP	307	cpuidle_params_table[i].valid = cpuidle_board_params[i].valid;
866ba0ef JP	308	cpuidle_params_table[i].exit_latency =
	309	cpuidle_board_params[i].exit_latency;
	310	cpuidle_params_table[i].target_residency =
	311	cpuidle_board_params[i].target_residency;
bb4de3df KH	312	}
	313	return;
	314	}
	315
99e6a4d2 RN	316	struct cpuidle_driver omap3_idle_driver = {
	317	.name = "omap3_idle",
	318	.owner = THIS_MODULE,
	319	};
	320
46bcfad7 DD	321	/* Helper to fill the C-state common data*/
46bcfad7 DD	322	static inline void _fill_cstate(struct cpuidle_driver *drv,
badc303a JP	323	int idx, const char *descr)
badc303a JP	324	{
46bcfad7	325	struct cpuidle_state *state = &drv->states[idx];
badc303a JP	326
	327	state->exit_latency = cpuidle_params_table[idx].exit_latency;
	328	state->target_residency = cpuidle_params_table[idx].target_residency;
	329	state->flags = CPUIDLE_FLAG_TIME_VALID;
	330	state->enter = omap3_enter_idle_bm;
badc303a JP	331	sprintf(state->name, "C%d", idx + 1);
badc303a JP	332	strncpy(state->desc, descr, CPUIDLE_DESC_LEN);
46bcfad7 DD	333
	334	}
	335
	336	/* Helper to register the driver_data */
	337	static inline struct omap3_idle_statedata *_fill_cstate_usage(
	338	struct cpuidle_device *dev,
	339	int idx)
	340	{
	341	struct omap3_idle_statedata *cx = &omap3_idle_data[idx];
	342	struct cpuidle_state_usage *state_usage = &dev->states_usage[idx];
	343
	344	cx->valid = cpuidle_params_table[idx].valid;
4202735e	345	cpuidle_set_statedata(state_usage, cx);
badc303a JP	346
	347	return cx;
	348	}
	349
99e6a4d2 RN	350	/**
	351	* omap3_idle_init - Init routine for OMAP3 idle
	352	*
badc303a	353	* Registers the OMAP3 specific cpuidle driver to the cpuidle
99e6a4d2 RN	354	* framework with the valid set of states.
99e6a4d2 RN	355	*/
0343371e	356	int __init omap3_idle_init(void)
99e6a4d2	357	{
99e6a4d2	358	struct cpuidle_device *dev;
46bcfad7	359	struct cpuidle_driver *drv = &omap3_idle_driver;
badc303a	360	struct omap3_idle_statedata *cx;
99e6a4d2 RN	361
99e6a4d2 RN	362	mpu_pd = pwrdm_lookup("mpu_pwrdm");
20b01669	363	core_pd = pwrdm_lookup("core_pwrdm");
e7410cf7 KH	364	per_pd = pwrdm_lookup("per_pwrdm");
e7410cf7 KH	365	cam_pd = pwrdm_lookup("cam_pwrdm");
99e6a4d2	366
46bcfad7 DD	367
46bcfad7 DD	368	drv->safe_state_index = -1;
99e6a4d2 RN	369	dev = &per_cpu(omap3_idle_dev, smp_processor_id());
99e6a4d2 RN	370
badc303a	371	/* C1 . MPU WFI + Core active */
46bcfad7 DD	372	_fill_cstate(drv, 0, "MPU ON + CORE ON");
	373	(&drv->states[0])->enter = omap3_enter_idle;
	374	drv->safe_state_index = 0;
	375	cx = _fill_cstate_usage(dev, 0);
badc303a JP	376	cx->valid = 1; /* C1 is always valid */
	377	cx->mpu_state = PWRDM_POWER_ON;
	378	cx->core_state = PWRDM_POWER_ON;
	379
	380	/* C2 . MPU WFI + Core inactive */
46bcfad7 DD	381	_fill_cstate(drv, 1, "MPU ON + CORE ON");
46bcfad7 DD	382	cx = _fill_cstate_usage(dev, 1);
badc303a JP	383	cx->mpu_state = PWRDM_POWER_ON;
	384	cx->core_state = PWRDM_POWER_ON;
	385
	386	/* C3 . MPU CSWR + Core inactive */
46bcfad7 DD	387	_fill_cstate(drv, 2, "MPU RET + CORE ON");
46bcfad7 DD	388	cx = _fill_cstate_usage(dev, 2);
badc303a JP	389	cx->mpu_state = PWRDM_POWER_RET;
	390	cx->core_state = PWRDM_POWER_ON;
	391
	392	/* C4 . MPU OFF + Core inactive */
46bcfad7 DD	393	_fill_cstate(drv, 3, "MPU OFF + CORE ON");
46bcfad7 DD	394	cx = _fill_cstate_usage(dev, 3);
badc303a JP	395	cx->mpu_state = PWRDM_POWER_OFF;
	396	cx->core_state = PWRDM_POWER_ON;
	397
	398	/* C5 . MPU RET + Core RET */
46bcfad7 DD	399	_fill_cstate(drv, 4, "MPU RET + CORE RET");
46bcfad7 DD	400	cx = _fill_cstate_usage(dev, 4);
badc303a JP	401	cx->mpu_state = PWRDM_POWER_RET;
badc303a JP	402	cx->core_state = PWRDM_POWER_RET;
99e6a4d2	403
badc303a	404	/* C6 . MPU OFF + Core RET */
46bcfad7 DD	405	_fill_cstate(drv, 5, "MPU OFF + CORE RET");
46bcfad7 DD	406	cx = _fill_cstate_usage(dev, 5);
badc303a JP	407	cx->mpu_state = PWRDM_POWER_OFF;
	408	cx->core_state = PWRDM_POWER_RET;
	409
	410	/* C7 . MPU OFF + Core OFF */
46bcfad7 DD	411	_fill_cstate(drv, 6, "MPU OFF + CORE OFF");
46bcfad7 DD	412	cx = _fill_cstate_usage(dev, 6);
badc303a JP	413	/*
	414	* Erratum i583: implementation for ES rev < Es1.2 on 3630. We cannot
	415	* enable OFF mode in a stable form for previous revisions.
	416	* We disable C7 state as a result.
	417	*/
	418	if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583)) {
	419	cx->valid = 0;
	420	pr_warn("%s: core off state C7 disabled due to i583\n",
	421	__func__);
	422	}
	423	cx->mpu_state = PWRDM_POWER_OFF;
	424	cx->core_state = PWRDM_POWER_OFF;
99e6a4d2	425
46bcfad7 DD	426	drv->state_count = OMAP3_NUM_STATES;
	427	cpuidle_register_driver(&omap3_idle_driver);
	428
badc303a	429	dev->state_count = OMAP3_NUM_STATES;
99e6a4d2 RN	430	if (cpuidle_register_device(dev)) {
	431	printk(KERN_ERR "%s: CPUidle register device failed\n",
	432	__func__);
	433	return -EIO;
	434	}
	435
	436	return 0;
	437	}
0343371e KJ	438	#else
	439	int __init omap3_idle_init(void)
	440	{
	441	return 0;
	442	}
99e6a4d2	443	#endif /* CONFIG_CPU_IDLE */