ARM: OMAP2+: Simplify system timer clock definitions
[linux-block.git] / arch / arm / mach-omap2 / common.h
CommitLineData
4e65331c
TL
1/*
2 * Header for code common to all OMAP2+ machines.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
12 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
13 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
14 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
15 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
16 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
17 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
18 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
19 *
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25#ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
26#define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H
b2b9762f 27#ifndef __ASSEMBLER__
4e65331c 28
ec2c0825 29#include <linux/irq.h>
4e65331c 30#include <linux/delay.h>
3a8761c0 31#include <linux/i2c.h>
1ee47b0a 32#include <linux/i2c/twl.h>
3a8761c0 33#include <linux/i2c-omap.h>
dbc04161 34
b2b9762f 35#include <asm/proc-fns.h>
4e65331c 36
3a8761c0 37#include "i2c.h"
3d82cbbb 38#include "serial.h"
3a8761c0 39
54db6eee 40#include "usb.h"
dbc04161 41
ec2c0825 42#define OMAP_INTC_START NR_IRQS
7d7e1eba 43
bbd707ac
SG
44#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2)
45int omap2_pm_init(void);
46#else
47static inline int omap2_pm_init(void)
48{
49 return 0;
50}
51#endif
52
53#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3)
54int omap3_pm_init(void);
55#else
56static inline int omap3_pm_init(void)
57{
58 return 0;
59}
60#endif
61
62#if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4)
63int omap4_pm_init(void);
64#else
65static inline int omap4_pm_init(void)
66{
67 return 0;
68}
69#endif
70
71#ifdef CONFIG_OMAP_MUX
72int omap_mux_late_init(void);
73#else
74static inline int omap_mux_late_init(void)
75{
76 return 0;
77}
78#endif
79
4e65331c
TL
80extern void omap2_init_common_infrastructure(void);
81
6bb27d73
SW
82extern void omap2_sync32k_timer_init(void);
83extern void omap3_sync32k_timer_init(void);
84extern void omap3_secure_sync32k_timer_init(void);
85extern void omap3_gp_gptimer_timer_init(void);
86extern void omap3_am33xx_gptimer_timer_init(void);
87extern void omap4_local_timer_init(void);
88extern void omap5_realtime_timer_init(void);
4e65331c
TL
89
90void omap2420_init_early(void);
91void omap2430_init_early(void);
92void omap3430_init_early(void);
93void omap35xx_init_early(void);
94void omap3630_init_early(void);
95void omap3_init_early(void); /* Do not use this one */
ce3fc89a 96void am33xx_init_early(void);
4e65331c 97void am35xx_init_early(void);
a920360f 98void ti81xx_init_early(void);
08f30989 99void am33xx_init_early(void);
4e65331c 100void omap4430_init_early(void);
05e152c7 101void omap5_init_early(void);
bbd707ac
SG
102void omap3_init_late(void); /* Do not use this one */
103void omap4430_init_late(void);
104void omap2420_init_late(void);
105void omap2430_init_late(void);
106void omap3430_init_late(void);
107void omap35xx_init_late(void);
108void omap3630_init_late(void);
109void am35xx_init_late(void);
110void ti81xx_init_late(void);
111void omap4430_init_late(void);
112int omap2_common_pm_late_init(void);
4e65331c 113
2f334a38
PW
114#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
115void omap2xxx_restart(char mode, const char *cmd);
ecc46cfd 116#else
2f334a38
PW
117static inline void omap2xxx_restart(char mode, const char *cmd)
118{
119}
ecc46cfd 120#endif
2f334a38
PW
121
122#ifdef CONFIG_ARCH_OMAP3
123void omap3xxx_restart(char mode, const char *cmd);
124#else
125static inline void omap3xxx_restart(char mode, const char *cmd)
126{
127}
128#endif
129
130#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
131void omap44xx_restart(char mode, const char *cmd);
132#else
133static inline void omap44xx_restart(char mode, const char *cmd)
134{
135}
136#endif
137
b6a4226c
PW
138/* This gets called from mach-omap2/io.c, do not call this */
139void __init omap2_set_globals_tap(u32 class, void __iomem *tap);
140
141void __init omap242x_map_io(void);
142void __init omap243x_map_io(void);
143void __init omap3_map_io(void);
144void __init am33xx_map_io(void);
145void __init omap4_map_io(void);
146void __init omap5_map_io(void);
147void __init ti81xx_map_io(void);
148
149/* omap_barriers_init() is OMAP4 only */
2ec1fc4e 150void omap_barriers_init(void);
4e65331c
TL
151
152/**
153 * omap_test_timeout - busy-loop, testing a condition
154 * @cond: condition to test until it evaluates to true
155 * @timeout: maximum number of microseconds in the timeout
156 * @index: loop index (integer)
157 *
158 * Loop waiting for @cond to become true or until at least @timeout
159 * microseconds have passed. To use, define some integer @index in the
160 * calling code. After running, if @index == @timeout, then the loop has
161 * timed out.
162 */
163#define omap_test_timeout(cond, timeout, index) \
164({ \
165 for (index = 0; index < timeout; index++) { \
166 if (cond) \
167 break; \
168 udelay(1); \
169 } \
170})
171
172extern struct device *omap2_get_mpuss_device(void);
173extern struct device *omap2_get_iva_device(void);
174extern struct device *omap2_get_l3_device(void);
175extern struct device *omap4_get_dsp_device(void);
176
177void omap2_init_irq(void);
178void omap3_init_irq(void);
a920360f 179void ti81xx_init_irq(void);
4e65331c
TL
180extern int omap_irq_pending(void);
181void omap_intc_save_context(void);
182void omap_intc_restore_context(void);
183void omap3_intc_suspend(void);
184void omap3_intc_prepare_idle(void);
185void omap3_intc_resume_idle(void);
f88f4dd8
SS
186void omap2_intc_handle_irq(struct pt_regs *regs);
187void omap3_intc_handle_irq(struct pt_regs *regs);
c4082d49
S
188void omap_intc_of_init(void);
189void omap_gic_of_init(void);
4e65331c 190
4e65331c 191#ifdef CONFIG_CACHE_L2X0
02afe8a7 192extern void __iomem *omap4_get_l2cache_base(void);
4e65331c
TL
193#endif
194
52fa2120
BC
195struct device_node;
196#ifdef CONFIG_OF
c4082d49 197int __init intc_of_init(struct device_node *node,
52fa2120
BC
198 struct device_node *parent);
199#else
c4082d49 200int __init intc_of_init(struct device_node *node,
52fa2120
BC
201 struct device_node *parent)
202{
203 return 0;
204}
205#endif
206
02afe8a7
SS
207#ifdef CONFIG_SMP
208extern void __iomem *omap4_get_scu_base(void);
209#else
210static inline void __iomem *omap4_get_scu_base(void)
211{
212 return NULL;
213}
4e65331c
TL
214#endif
215
4e65331c 216extern void __init gic_init_irq(void);
ff999b8a 217extern void gic_dist_disable(void);
cd8ce159
CC
218extern bool gic_dist_disabled(void);
219extern void gic_timer_retrigger(void);
4e65331c 220extern void omap_smc1(u32 fn, u32 arg);
501f0c75 221extern void __iomem *omap4_get_sar_ram_base(void);
b2b9762f 222extern void omap_do_wfi(void);
4e65331c
TL
223
224#ifdef CONFIG_SMP
225/* Needed for secondary core boot */
226extern void omap_secondary_startup(void);
ff999b8a 227extern void omap_secondary_startup_4460(void);
4e65331c
TL
228extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
229extern void omap_auxcoreboot_addr(u32 cpu_addr);
230extern u32 omap_read_auxcoreboot0(void);
06915321
MZ
231
232extern void omap4_cpu_die(unsigned int cpu);
233
234extern struct smp_operations omap4_smp_ops;
235
283f708c 236extern void omap5_secondary_startup(void);
4e65331c
TL
237#endif
238
b2b9762f
SS
239#if defined(CONFIG_SMP) && defined(CONFIG_PM)
240extern int omap4_mpuss_init(void);
241extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state);
242extern int omap4_finish_suspend(unsigned long cpu_state);
243extern void omap4_cpu_resume(void);
b5b4f288 244extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state);
3ba2a739 245extern u32 omap4_mpuss_read_prev_context_state(void);
b2b9762f
SS
246#else
247static inline int omap4_enter_lowpower(unsigned int cpu,
248 unsigned int power_state)
249{
250 cpu_do_idle();
251 return 0;
252}
253
b5b4f288
SS
254static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state)
255{
256 cpu_do_idle();
257 return 0;
258}
259
b2b9762f
SS
260static inline int omap4_mpuss_init(void)
261{
262 return 0;
263}
264
265static inline int omap4_finish_suspend(unsigned long cpu_state)
266{
267 return 0;
268}
269
270static inline void omap4_cpu_resume(void)
271{}
3ba2a739
SS
272
273static inline u32 omap4_mpuss_read_prev_context_state(void)
274{
275 return 0;
276}
b2b9762f 277#endif
258ee922
TL
278
279struct omap_sdrc_params;
280extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
281 struct omap_sdrc_params *sdrc_cs1);
1ee47b0a
B
282struct omap2_hsmmc_info;
283extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers);
f583f0f2 284extern void omap_reserve(void);
258ee922 285
5c2e8852
TL
286struct omap_hwmod;
287extern int omap_dss_reset(struct omap_hwmod *);
258ee922 288
b2b9762f 289#endif /* __ASSEMBLER__ */
4e65331c 290#endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */