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4e65331c TL |
1 | /* |
2 | * Header for code common to all OMAP2+ machines. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License as published by the | |
6 | * Free Software Foundation; either version 2 of the License, or (at your | |
7 | * option) any later version. | |
8 | * | |
9 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
10 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
11 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
12 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
13 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
14 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
15 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
16 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
17 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
18 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License along | |
21 | * with this program; if not, write to the Free Software Foundation, Inc., | |
22 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
23 | */ | |
24 | ||
25 | #ifndef __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
26 | #define __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H | |
b2b9762f | 27 | #ifndef __ASSEMBLER__ |
4e65331c | 28 | |
ec2c0825 | 29 | #include <linux/irq.h> |
4e65331c | 30 | #include <linux/delay.h> |
3a8761c0 | 31 | #include <linux/i2c.h> |
1ee47b0a | 32 | #include <linux/i2c/twl.h> |
3a8761c0 | 33 | #include <linux/i2c-omap.h> |
dbc04161 | 34 | |
b2b9762f | 35 | #include <asm/proc-fns.h> |
4e65331c | 36 | |
e6a6e5ad | 37 | #include "../plat-omap/common.h" |
dbc04161 | 38 | |
3a8761c0 | 39 | #include "i2c.h" |
3d82cbbb | 40 | #include "serial.h" |
3a8761c0 | 41 | |
ec2c0825 | 42 | #define OMAP_INTC_START NR_IRQS |
7d7e1eba | 43 | |
4e65331c TL |
44 | #ifdef CONFIG_SOC_OMAP2420 |
45 | extern void omap242x_map_common_io(void); | |
46 | #else | |
47 | static inline void omap242x_map_common_io(void) | |
48 | { | |
49 | } | |
50 | #endif | |
51 | ||
52 | #ifdef CONFIG_SOC_OMAP2430 | |
53 | extern void omap243x_map_common_io(void); | |
54 | #else | |
55 | static inline void omap243x_map_common_io(void) | |
56 | { | |
57 | } | |
58 | #endif | |
59 | ||
60 | #ifdef CONFIG_ARCH_OMAP3 | |
61 | extern void omap34xx_map_common_io(void); | |
62 | #else | |
63 | static inline void omap34xx_map_common_io(void) | |
64 | { | |
65 | } | |
66 | #endif | |
67 | ||
33959553 | 68 | #ifdef CONFIG_SOC_TI81XX |
a920360f | 69 | extern void omapti81xx_map_common_io(void); |
4e65331c | 70 | #else |
a920360f | 71 | static inline void omapti81xx_map_common_io(void) |
4e65331c TL |
72 | { |
73 | } | |
74 | #endif | |
75 | ||
bb6abcf4 | 76 | #ifdef CONFIG_SOC_AM33XX |
1e6cb146 AM |
77 | extern void omapam33xx_map_common_io(void); |
78 | #else | |
79 | static inline void omapam33xx_map_common_io(void) | |
80 | { | |
81 | } | |
82 | #endif | |
83 | ||
4e65331c TL |
84 | #ifdef CONFIG_ARCH_OMAP4 |
85 | extern void omap44xx_map_common_io(void); | |
86 | #else | |
87 | static inline void omap44xx_map_common_io(void) | |
88 | { | |
89 | } | |
90 | #endif | |
91 | ||
bbd707ac SG |
92 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP2) |
93 | int omap2_pm_init(void); | |
94 | #else | |
95 | static inline int omap2_pm_init(void) | |
96 | { | |
97 | return 0; | |
98 | } | |
99 | #endif | |
100 | ||
101 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP3) | |
102 | int omap3_pm_init(void); | |
103 | #else | |
104 | static inline int omap3_pm_init(void) | |
105 | { | |
106 | return 0; | |
107 | } | |
108 | #endif | |
109 | ||
110 | #if defined(CONFIG_PM) && defined(CONFIG_ARCH_OMAP4) | |
111 | int omap4_pm_init(void); | |
112 | #else | |
113 | static inline int omap4_pm_init(void) | |
114 | { | |
115 | return 0; | |
116 | } | |
117 | #endif | |
118 | ||
119 | #ifdef CONFIG_OMAP_MUX | |
120 | int omap_mux_late_init(void); | |
121 | #else | |
122 | static inline int omap_mux_late_init(void) | |
123 | { | |
124 | return 0; | |
125 | } | |
126 | #endif | |
127 | ||
05e152c7 S |
128 | #ifdef CONFIG_SOC_OMAP5 |
129 | extern void omap5_map_common_io(void); | |
130 | #else | |
131 | static inline void omap5_map_common_io(void) | |
132 | { | |
133 | } | |
134 | #endif | |
135 | ||
4e65331c TL |
136 | extern void omap2_init_common_infrastructure(void); |
137 | ||
138 | extern struct sys_timer omap2_timer; | |
139 | extern struct sys_timer omap3_timer; | |
140 | extern struct sys_timer omap3_secure_timer; | |
08f30989 | 141 | extern struct sys_timer omap3_am33xx_timer; |
4e65331c | 142 | extern struct sys_timer omap4_timer; |
37b3280d | 143 | extern struct sys_timer omap5_timer; |
4e65331c TL |
144 | |
145 | void omap2420_init_early(void); | |
146 | void omap2430_init_early(void); | |
147 | void omap3430_init_early(void); | |
148 | void omap35xx_init_early(void); | |
149 | void omap3630_init_early(void); | |
150 | void omap3_init_early(void); /* Do not use this one */ | |
ce3fc89a | 151 | void am33xx_init_early(void); |
4e65331c | 152 | void am35xx_init_early(void); |
a920360f | 153 | void ti81xx_init_early(void); |
08f30989 | 154 | void am33xx_init_early(void); |
4e65331c | 155 | void omap4430_init_early(void); |
05e152c7 | 156 | void omap5_init_early(void); |
bbd707ac SG |
157 | void omap3_init_late(void); /* Do not use this one */ |
158 | void omap4430_init_late(void); | |
159 | void omap2420_init_late(void); | |
160 | void omap2430_init_late(void); | |
161 | void omap3430_init_late(void); | |
162 | void omap35xx_init_late(void); | |
163 | void omap3630_init_late(void); | |
164 | void am35xx_init_late(void); | |
165 | void ti81xx_init_late(void); | |
166 | void omap4430_init_late(void); | |
167 | int omap2_common_pm_late_init(void); | |
baa95883 | 168 | void omap_prcm_restart(char, const char *); |
4e65331c TL |
169 | |
170 | /* | |
171 | * IO bases for various OMAP processors | |
172 | * Except the tap base, rest all the io bases | |
173 | * listed are physical addresses. | |
174 | */ | |
175 | struct omap_globals { | |
176 | u32 class; /* OMAP class to detect */ | |
177 | void __iomem *tap; /* Control module ID code */ | |
178 | void __iomem *sdrc; /* SDRAM Controller */ | |
179 | void __iomem *sms; /* SDRAM Memory Scheduler */ | |
180 | void __iomem *ctrl; /* System Control Module */ | |
181 | void __iomem *ctrl_pad; /* PAD Control Module */ | |
182 | void __iomem *prm; /* Power and Reset Management */ | |
183 | void __iomem *cm; /* Clock Management */ | |
184 | void __iomem *cm2; | |
610eb8c2 | 185 | void __iomem *prcm_mpu; |
4e65331c TL |
186 | }; |
187 | ||
188 | void omap2_set_globals_242x(void); | |
189 | void omap2_set_globals_243x(void); | |
190 | void omap2_set_globals_3xxx(void); | |
191 | void omap2_set_globals_443x(void); | |
05e152c7 | 192 | void omap2_set_globals_5xxx(void); |
a920360f | 193 | void omap2_set_globals_ti81xx(void); |
1e6cb146 | 194 | void omap2_set_globals_am33xx(void); |
4e65331c TL |
195 | |
196 | /* These get called from omap2_set_globals_xxxx(), do not call these */ | |
197 | void omap2_set_globals_tap(struct omap_globals *); | |
ecc46cfd | 198 | #if defined(CONFIG_SOC_HAS_OMAP2_SDRC) |
4e65331c | 199 | void omap2_set_globals_sdrc(struct omap_globals *); |
ecc46cfd VH |
200 | #else |
201 | static inline void omap2_set_globals_sdrc(struct omap_globals *omap2_globals) | |
202 | { } | |
203 | #endif | |
4e65331c TL |
204 | void omap2_set_globals_control(struct omap_globals *); |
205 | void omap2_set_globals_prcm(struct omap_globals *); | |
206 | ||
207 | void omap242x_map_io(void); | |
208 | void omap243x_map_io(void); | |
209 | void omap3_map_io(void); | |
1e6cb146 | 210 | void am33xx_map_io(void); |
4e65331c | 211 | void omap4_map_io(void); |
05e152c7 | 212 | void omap5_map_io(void); |
a920360f | 213 | void ti81xx_map_io(void); |
2ec1fc4e | 214 | void omap_barriers_init(void); |
4e65331c TL |
215 | |
216 | /** | |
217 | * omap_test_timeout - busy-loop, testing a condition | |
218 | * @cond: condition to test until it evaluates to true | |
219 | * @timeout: maximum number of microseconds in the timeout | |
220 | * @index: loop index (integer) | |
221 | * | |
222 | * Loop waiting for @cond to become true or until at least @timeout | |
223 | * microseconds have passed. To use, define some integer @index in the | |
224 | * calling code. After running, if @index == @timeout, then the loop has | |
225 | * timed out. | |
226 | */ | |
227 | #define omap_test_timeout(cond, timeout, index) \ | |
228 | ({ \ | |
229 | for (index = 0; index < timeout; index++) { \ | |
230 | if (cond) \ | |
231 | break; \ | |
232 | udelay(1); \ | |
233 | } \ | |
234 | }) | |
235 | ||
236 | extern struct device *omap2_get_mpuss_device(void); | |
237 | extern struct device *omap2_get_iva_device(void); | |
238 | extern struct device *omap2_get_l3_device(void); | |
239 | extern struct device *omap4_get_dsp_device(void); | |
240 | ||
241 | void omap2_init_irq(void); | |
242 | void omap3_init_irq(void); | |
a920360f | 243 | void ti81xx_init_irq(void); |
4e65331c TL |
244 | extern int omap_irq_pending(void); |
245 | void omap_intc_save_context(void); | |
246 | void omap_intc_restore_context(void); | |
247 | void omap3_intc_suspend(void); | |
248 | void omap3_intc_prepare_idle(void); | |
249 | void omap3_intc_resume_idle(void); | |
f88f4dd8 SS |
250 | void omap2_intc_handle_irq(struct pt_regs *regs); |
251 | void omap3_intc_handle_irq(struct pt_regs *regs); | |
c4082d49 S |
252 | void omap_intc_of_init(void); |
253 | void omap_gic_of_init(void); | |
4e65331c | 254 | |
4e65331c | 255 | #ifdef CONFIG_CACHE_L2X0 |
02afe8a7 | 256 | extern void __iomem *omap4_get_l2cache_base(void); |
4e65331c TL |
257 | #endif |
258 | ||
52fa2120 BC |
259 | struct device_node; |
260 | #ifdef CONFIG_OF | |
c4082d49 | 261 | int __init intc_of_init(struct device_node *node, |
52fa2120 BC |
262 | struct device_node *parent); |
263 | #else | |
c4082d49 | 264 | int __init intc_of_init(struct device_node *node, |
52fa2120 BC |
265 | struct device_node *parent) |
266 | { | |
267 | return 0; | |
268 | } | |
269 | #endif | |
270 | ||
02afe8a7 SS |
271 | #ifdef CONFIG_SMP |
272 | extern void __iomem *omap4_get_scu_base(void); | |
273 | #else | |
274 | static inline void __iomem *omap4_get_scu_base(void) | |
275 | { | |
276 | return NULL; | |
277 | } | |
4e65331c TL |
278 | #endif |
279 | ||
4e65331c TL |
280 | extern void __init gic_init_irq(void); |
281 | extern void omap_smc1(u32 fn, u32 arg); | |
501f0c75 | 282 | extern void __iomem *omap4_get_sar_ram_base(void); |
b2b9762f | 283 | extern void omap_do_wfi(void); |
4e65331c TL |
284 | |
285 | #ifdef CONFIG_SMP | |
286 | /* Needed for secondary core boot */ | |
287 | extern void omap_secondary_startup(void); | |
288 | extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask); | |
289 | extern void omap_auxcoreboot_addr(u32 cpu_addr); | |
290 | extern u32 omap_read_auxcoreboot0(void); | |
06915321 MZ |
291 | |
292 | extern void omap4_cpu_die(unsigned int cpu); | |
293 | ||
294 | extern struct smp_operations omap4_smp_ops; | |
295 | ||
283f708c | 296 | extern void omap5_secondary_startup(void); |
4e65331c TL |
297 | #endif |
298 | ||
b2b9762f SS |
299 | #if defined(CONFIG_SMP) && defined(CONFIG_PM) |
300 | extern int omap4_mpuss_init(void); | |
301 | extern int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state); | |
302 | extern int omap4_finish_suspend(unsigned long cpu_state); | |
303 | extern void omap4_cpu_resume(void); | |
b5b4f288 | 304 | extern int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state); |
3ba2a739 | 305 | extern u32 omap4_mpuss_read_prev_context_state(void); |
b2b9762f SS |
306 | #else |
307 | static inline int omap4_enter_lowpower(unsigned int cpu, | |
308 | unsigned int power_state) | |
309 | { | |
310 | cpu_do_idle(); | |
311 | return 0; | |
312 | } | |
313 | ||
b5b4f288 SS |
314 | static inline int omap4_hotplug_cpu(unsigned int cpu, unsigned int power_state) |
315 | { | |
316 | cpu_do_idle(); | |
317 | return 0; | |
318 | } | |
319 | ||
b2b9762f SS |
320 | static inline int omap4_mpuss_init(void) |
321 | { | |
322 | return 0; | |
323 | } | |
324 | ||
325 | static inline int omap4_finish_suspend(unsigned long cpu_state) | |
326 | { | |
327 | return 0; | |
328 | } | |
329 | ||
330 | static inline void omap4_cpu_resume(void) | |
331 | {} | |
3ba2a739 SS |
332 | |
333 | static inline u32 omap4_mpuss_read_prev_context_state(void) | |
334 | { | |
335 | return 0; | |
336 | } | |
b2b9762f | 337 | #endif |
258ee922 TL |
338 | |
339 | struct omap_sdrc_params; | |
340 | extern void omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0, | |
341 | struct omap_sdrc_params *sdrc_cs1); | |
1ee47b0a B |
342 | struct omap2_hsmmc_info; |
343 | extern int omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers); | |
f583f0f2 | 344 | extern void omap_reserve(void); |
258ee922 | 345 | |
b2b9762f | 346 | #endif /* __ASSEMBLER__ */ |
4e65331c | 347 | #endif /* __ARCH_ARM_MACH_OMAP2PLUS_COMMON_H */ |