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21325b25 PW |
1 | /* |
2 | * OMAP2+ common Clock Management (CM) IP block functions | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments, Inc. | |
d9a16f9a | 5 | * Paul Walmsley |
21325b25 PW |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * XXX This code should eventually be moved to a CM driver. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
15 | #include <linux/init.h> | |
cc4b1e24 | 16 | #include <linux/errno.h> |
4794208c | 17 | #include <linux/bug.h> |
fe87414f TK |
18 | #include <linux/of.h> |
19 | #include <linux/of_address.h> | |
21325b25 PW |
20 | |
21 | #include "cm2xxx.h" | |
22 | #include "cm3xxx.h" | |
425dc8b2 | 23 | #include "cm33xx.h" |
21325b25 | 24 | #include "cm44xx.h" |
fe87414f | 25 | #include "clock.h" |
21325b25 PW |
26 | |
27 | /* | |
28 | * cm_ll_data: function pointers to SoC-specific implementations of | |
29 | * common CM functions | |
30 | */ | |
31 | static struct cm_ll_data null_cm_ll_data; | |
32 | static struct cm_ll_data *cm_ll_data = &null_cm_ll_data; | |
33 | ||
d9a16f9a | 34 | /* cm_base: base virtual address of the CM IP block */ |
90129336 | 35 | struct omap_domain_base cm_base; |
d9a16f9a PW |
36 | |
37 | /* cm2_base: base virtual address of the CM2 IP block (OMAP44xx only) */ | |
90129336 | 38 | struct omap_domain_base cm2_base; |
d9a16f9a | 39 | |
5970ca2d | 40 | #define CM_NO_CLOCKS 0x1 |
425dc8b2 | 41 | #define CM_SINGLE_INSTANCE 0x2 |
5970ca2d | 42 | |
d9a16f9a PW |
43 | /** |
44 | * omap2_set_globals_cm - set the CM/CM2 base addresses (for early use) | |
45 | * @cm: CM base virtual address | |
46 | * @cm2: CM2 base virtual address (if present on the booted SoC) | |
47 | * | |
48 | * XXX Will be replaced when the PRM/CM drivers are completed. | |
49 | */ | |
50 | void __init omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2) | |
51 | { | |
90129336 TK |
52 | cm_base.va = cm; |
53 | cm2_base.va = cm2; | |
d9a16f9a PW |
54 | } |
55 | ||
c4ceedcb PW |
56 | /** |
57 | * cm_split_idlest_reg - split CM_IDLEST reg addr into its components | |
58 | * @idlest_reg: CM_IDLEST* virtual address | |
59 | * @prcm_inst: pointer to an s16 to return the PRCM instance offset | |
60 | * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID | |
61 | * | |
62 | * Given an absolute CM_IDLEST register address @idlest_reg, passes | |
63 | * the PRCM instance offset and IDLEST register ID back to the caller | |
64 | * via the @prcm_inst and @idlest_reg_id. Returns -EINVAL upon error, | |
65 | * or 0 upon success. XXX This function is only needed until absolute | |
66 | * register addresses are removed from the OMAP struct clk records. | |
67 | */ | |
6c0afb50 | 68 | int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, |
c4ceedcb PW |
69 | u8 *idlest_reg_id) |
70 | { | |
6301d584 | 71 | int ret; |
c4ceedcb PW |
72 | if (!cm_ll_data->split_idlest_reg) { |
73 | WARN_ONCE(1, "cm: %s: no low-level function defined\n", | |
74 | __func__); | |
75 | return -EINVAL; | |
76 | } | |
77 | ||
6301d584 | 78 | ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, |
c4ceedcb | 79 | idlest_reg_id); |
6301d584 TK |
80 | *prcm_inst -= cm_base.offset; |
81 | return ret; | |
c4ceedcb PW |
82 | } |
83 | ||
84 | /** | |
021b6ff0 TK |
85 | * omap_cm_wait_module_ready - wait for a module to leave idle or standby |
86 | * @part: PRCM partition | |
c4ceedcb | 87 | * @prcm_mod: PRCM module offset |
021b6ff0 | 88 | * @idlest_reg: CM_IDLESTx register |
c4ceedcb PW |
89 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check |
90 | * | |
91 | * Wait for the PRCM to indicate that the module identified by | |
92 | * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon | |
93 | * success, -EBUSY if the module doesn't enable in time, or -EINVAL if | |
94 | * no per-SoC wait_module_ready() function pointer has been registered | |
95 | * or if the idlest register is unknown on the SoC. | |
96 | */ | |
021b6ff0 TK |
97 | int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg, |
98 | u8 idlest_shift) | |
c4ceedcb PW |
99 | { |
100 | if (!cm_ll_data->wait_module_ready) { | |
101 | WARN_ONCE(1, "cm: %s: no low-level function defined\n", | |
102 | __func__); | |
103 | return -EINVAL; | |
104 | } | |
105 | ||
021b6ff0 TK |
106 | return cm_ll_data->wait_module_ready(part, prcm_mod, idlest_reg, |
107 | idlest_shift); | |
c4ceedcb PW |
108 | } |
109 | ||
a8ae5afa TK |
110 | /** |
111 | * omap_cm_wait_module_idle - wait for a module to enter idle or standby | |
112 | * @part: PRCM partition | |
113 | * @prcm_mod: PRCM module offset | |
114 | * @idlest_reg: CM_IDLESTx register | |
115 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check | |
116 | * | |
117 | * Wait for the PRCM to indicate that the module identified by | |
118 | * (@prcm_mod, @idlest_id, @idlest_shift) is no longer clocked. Return | |
119 | * 0 upon success, -EBUSY if the module doesn't enable in time, or | |
120 | * -EINVAL if no per-SoC wait_module_idle() function pointer has been | |
121 | * registered or if the idlest register is unknown on the SoC. | |
122 | */ | |
123 | int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg, | |
124 | u8 idlest_shift) | |
125 | { | |
126 | if (!cm_ll_data->wait_module_idle) { | |
127 | WARN_ONCE(1, "cm: %s: no low-level function defined\n", | |
128 | __func__); | |
129 | return -EINVAL; | |
130 | } | |
131 | ||
132 | return cm_ll_data->wait_module_idle(part, prcm_mod, idlest_reg, | |
133 | idlest_shift); | |
134 | } | |
135 | ||
128603f0 TK |
136 | /** |
137 | * omap_cm_module_enable - enable a module | |
138 | * @mode: target mode for the module | |
139 | * @part: PRCM partition | |
140 | * @inst: PRCM instance | |
141 | * @clkctrl_offs: CM_CLKCTRL register offset for the module | |
142 | * | |
143 | * Enables clocks for a module identified by (@part, @inst, @clkctrl_offs) | |
144 | * making its IO space accessible. Return 0 upon success, -EINVAL if no | |
145 | * per-SoC module_enable() function pointer has been registered. | |
146 | */ | |
147 | int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs) | |
148 | { | |
149 | if (!cm_ll_data->module_enable) { | |
150 | WARN_ONCE(1, "cm: %s: no low-level function defined\n", | |
151 | __func__); | |
152 | return -EINVAL; | |
153 | } | |
154 | ||
155 | cm_ll_data->module_enable(mode, part, inst, clkctrl_offs); | |
156 | return 0; | |
157 | } | |
158 | ||
159 | /** | |
160 | * omap_cm_module_disable - disable a module | |
161 | * @part: PRCM partition | |
162 | * @inst: PRCM instance | |
163 | * @clkctrl_offs: CM_CLKCTRL register offset for the module | |
164 | * | |
165 | * Disables clocks for a module identified by (@part, @inst, @clkctrl_offs) | |
166 | * makings its IO space inaccessible. Return 0 upon success, -EINVAL if | |
167 | * no per-SoC module_disable() function pointer has been registered. | |
168 | */ | |
169 | int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs) | |
170 | { | |
171 | if (!cm_ll_data->module_disable) { | |
172 | WARN_ONCE(1, "cm: %s: no low-level function defined\n", | |
173 | __func__); | |
174 | return -EINVAL; | |
175 | } | |
176 | ||
177 | cm_ll_data->module_disable(part, inst, clkctrl_offs); | |
178 | return 0; | |
179 | } | |
180 | ||
21325b25 PW |
181 | /** |
182 | * cm_register - register per-SoC low-level data with the CM | |
183 | * @cld: low-level per-SoC OMAP CM data & function pointers to register | |
184 | * | |
185 | * Register per-SoC low-level OMAP CM data and function pointers with | |
186 | * the OMAP CM common interface. The caller must keep the data | |
187 | * pointed to by @cld valid until it calls cm_unregister() and | |
188 | * it returns successfully. Returns 0 upon success, -EINVAL if @cld | |
189 | * is NULL, or -EEXIST if cm_register() has already been called | |
190 | * without an intervening cm_unregister(). | |
191 | */ | |
192 | int cm_register(struct cm_ll_data *cld) | |
193 | { | |
194 | if (!cld) | |
195 | return -EINVAL; | |
196 | ||
197 | if (cm_ll_data != &null_cm_ll_data) | |
198 | return -EEXIST; | |
199 | ||
200 | cm_ll_data = cld; | |
201 | ||
202 | return 0; | |
203 | } | |
204 | ||
205 | /** | |
206 | * cm_unregister - unregister per-SoC low-level data & function pointers | |
207 | * @cld: low-level per-SoC OMAP CM data & function pointers to unregister | |
208 | * | |
209 | * Unregister per-SoC low-level OMAP CM data and function pointers | |
210 | * that were previously registered with cm_register(). The | |
211 | * caller may not destroy any of the data pointed to by @cld until | |
212 | * this function returns successfully. Returns 0 upon success, or | |
213 | * -EINVAL if @cld is NULL or if @cld does not match the struct | |
214 | * cm_ll_data * previously registered by cm_register(). | |
215 | */ | |
216 | int cm_unregister(struct cm_ll_data *cld) | |
217 | { | |
218 | if (!cld || cm_ll_data != cld) | |
219 | return -EINVAL; | |
220 | ||
221 | cm_ll_data = &null_cm_ll_data; | |
222 | ||
223 | return 0; | |
224 | } | |
fe87414f | 225 | |
425dc8b2 TK |
226 | #if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5) || \ |
227 | defined(CONFIG_SOC_DRA7XX) | |
228 | static struct omap_prcm_init_data cm_data __initdata = { | |
fe87414f | 229 | .index = TI_CLKM_CM, |
425dc8b2 | 230 | .init = omap4_cm_init, |
fe87414f TK |
231 | }; |
232 | ||
425dc8b2 | 233 | static struct omap_prcm_init_data cm2_data __initdata = { |
fe87414f | 234 | .index = TI_CLKM_CM2, |
425dc8b2 | 235 | .init = omap4_cm_init, |
fe87414f | 236 | }; |
425dc8b2 | 237 | #endif |
fe87414f | 238 | |
425dc8b2 TK |
239 | #ifdef CONFIG_ARCH_OMAP2 |
240 | static struct omap_prcm_init_data omap2_prcm_data __initdata = { | |
5970ca2d | 241 | .index = TI_CLKM_CM, |
425dc8b2 TK |
242 | .init = omap2xxx_cm_init, |
243 | .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, | |
5970ca2d | 244 | }; |
425dc8b2 | 245 | #endif |
5970ca2d | 246 | |
425dc8b2 TK |
247 | #ifdef CONFIG_ARCH_OMAP3 |
248 | static struct omap_prcm_init_data omap3_cm_data __initdata = { | |
5970ca2d | 249 | .index = TI_CLKM_CM, |
425dc8b2 TK |
250 | .init = omap3xxx_cm_init, |
251 | .flags = CM_SINGLE_INSTANCE, | |
5970ca2d TK |
252 | |
253 | /* | |
254 | * IVA2 offset is a negative value, must offset the cm_base address | |
255 | * by this to get it to positive side on the iomap | |
256 | */ | |
257 | .offset = -OMAP3430_IVA2_MOD, | |
258 | }; | |
425dc8b2 | 259 | #endif |
5970ca2d | 260 | |
425dc8b2 TK |
261 | #if defined(CONFIG_SOC_AM33XX) || defined(CONFIG_SOC_TI81XX) |
262 | static struct omap_prcm_init_data am3_prcm_data __initdata = { | |
5970ca2d | 263 | .index = TI_CLKM_CM, |
425dc8b2 TK |
264 | .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, |
265 | .init = am33xx_cm_init, | |
5970ca2d | 266 | }; |
425dc8b2 | 267 | #endif |
5970ca2d | 268 | |
425dc8b2 TK |
269 | #ifdef CONFIG_SOC_AM43XX |
270 | static struct omap_prcm_init_data am4_prcm_data __initdata = { | |
5970ca2d | 271 | .index = TI_CLKM_CM, |
425dc8b2 TK |
272 | .flags = CM_NO_CLOCKS | CM_SINGLE_INSTANCE, |
273 | .init = omap4_cm_init, | |
5970ca2d | 274 | }; |
425dc8b2 | 275 | #endif |
5970ca2d | 276 | |
425dc8b2 TK |
277 | static const struct of_device_id omap_cm_dt_match_table[] __initconst = { |
278 | #ifdef CONFIG_ARCH_OMAP2 | |
5970ca2d | 279 | { .compatible = "ti,omap2-prcm", .data = &omap2_prcm_data }, |
425dc8b2 TK |
280 | #endif |
281 | #ifdef CONFIG_ARCH_OMAP3 | |
5970ca2d | 282 | { .compatible = "ti,omap3-cm", .data = &omap3_cm_data }, |
425dc8b2 TK |
283 | #endif |
284 | #ifdef CONFIG_ARCH_OMAP4 | |
fe87414f TK |
285 | { .compatible = "ti,omap4-cm1", .data = &cm_data }, |
286 | { .compatible = "ti,omap4-cm2", .data = &cm2_data }, | |
425dc8b2 TK |
287 | #endif |
288 | #ifdef CONFIG_SOC_OMAP5 | |
fe87414f TK |
289 | { .compatible = "ti,omap5-cm-core-aon", .data = &cm_data }, |
290 | { .compatible = "ti,omap5-cm-core", .data = &cm2_data }, | |
425dc8b2 TK |
291 | #endif |
292 | #ifdef CONFIG_SOC_DRA7XX | |
fe87414f TK |
293 | { .compatible = "ti,dra7-cm-core-aon", .data = &cm_data }, |
294 | { .compatible = "ti,dra7-cm-core", .data = &cm2_data }, | |
425dc8b2 TK |
295 | #endif |
296 | #ifdef CONFIG_SOC_AM33XX | |
5970ca2d | 297 | { .compatible = "ti,am3-prcm", .data = &am3_prcm_data }, |
425dc8b2 TK |
298 | #endif |
299 | #ifdef CONFIG_SOC_AM43XX | |
5970ca2d | 300 | { .compatible = "ti,am4-prcm", .data = &am4_prcm_data }, |
425dc8b2 TK |
301 | #endif |
302 | #ifdef CONFIG_SOC_TI81XX | |
303 | { .compatible = "ti,dm814-prcm", .data = &am3_prcm_data }, | |
304 | { .compatible = "ti,dm816-prcm", .data = &am3_prcm_data }, | |
305 | #endif | |
fe87414f TK |
306 | { } |
307 | }; | |
308 | ||
5970ca2d TK |
309 | /** |
310 | * omap2_cm_base_init - initialize iomappings for the CM drivers | |
311 | * | |
312 | * Detects and initializes the iomappings for the CM driver, based | |
313 | * on the DT data. Returns 0 in success, negative error value | |
314 | * otherwise. | |
315 | */ | |
316 | int __init omap2_cm_base_init(void) | |
317 | { | |
318 | struct device_node *np; | |
319 | const struct of_device_id *match; | |
320 | struct omap_prcm_init_data *data; | |
90129336 TK |
321 | struct resource res; |
322 | int ret; | |
323 | struct omap_domain_base *mem = NULL; | |
5970ca2d TK |
324 | |
325 | for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { | |
326 | data = (struct omap_prcm_init_data *)match->data; | |
327 | ||
90129336 TK |
328 | ret = of_address_to_resource(np, 0, &res); |
329 | if (ret) | |
330 | return ret; | |
5970ca2d TK |
331 | |
332 | if (data->index == TI_CLKM_CM) | |
90129336 | 333 | mem = &cm_base; |
5970ca2d TK |
334 | |
335 | if (data->index == TI_CLKM_CM2) | |
90129336 TK |
336 | mem = &cm2_base; |
337 | ||
338 | data->mem = ioremap(res.start, resource_size(&res)); | |
5970ca2d | 339 | |
90129336 TK |
340 | if (mem) { |
341 | mem->pa = res.start + data->offset; | |
342 | mem->va = data->mem + data->offset; | |
6301d584 | 343 | mem->offset = data->offset; |
90129336 | 344 | } |
425dc8b2 TK |
345 | |
346 | data->np = np; | |
347 | ||
348 | if (data->init && (data->flags & CM_SINGLE_INSTANCE || | |
90129336 | 349 | (cm_base.va && cm2_base.va))) |
425dc8b2 | 350 | data->init(data); |
5970ca2d TK |
351 | } |
352 | ||
353 | return 0; | |
354 | } | |
355 | ||
fe87414f TK |
356 | /** |
357 | * omap_cm_init - low level init for the CM drivers | |
358 | * | |
359 | * Initializes the low level clock infrastructure for CM drivers. | |
360 | * Returns 0 in success, negative error value in failure. | |
361 | */ | |
362 | int __init omap_cm_init(void) | |
363 | { | |
364 | struct device_node *np; | |
fe87414f TK |
365 | const struct of_device_id *match; |
366 | const struct omap_prcm_init_data *data; | |
367 | int ret; | |
368 | ||
369 | for_each_matching_node_and_match(np, omap_cm_dt_match_table, &match) { | |
370 | data = match->data; | |
371 | ||
5970ca2d TK |
372 | if (data->flags & CM_NO_CLOCKS) |
373 | continue; | |
fe87414f | 374 | |
80cbb224 | 375 | ret = omap2_clk_provider_init(np, data->index, NULL, data->mem); |
fe87414f TK |
376 | if (ret) |
377 | return ret; | |
378 | } | |
379 | ||
380 | return 0; | |
381 | } |