Commit | Line | Data |
---|---|---|
71348bca | 1 | /* |
4bd5259e | 2 | * OMAP3xxx CM module functions |
71348bca PW |
3 | * |
4 | * Copyright (C) 2009 Nokia Corporation | |
4bd5259e | 5 | * Copyright (C) 2008-2010, 2012 Texas Instruments, Inc. |
71348bca | 6 | * Paul Walmsley |
4bd5259e | 7 | * Rajendra Nayak <rnayak@ti.com> |
71348bca PW |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #include <linux/kernel.h> | |
71348bca PW |
15 | #include <linux/types.h> |
16 | #include <linux/delay.h> | |
71348bca PW |
17 | #include <linux/errno.h> |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | ||
4bd5259e | 21 | #include "prm2xxx_3xxx.h" |
71348bca | 22 | #include "cm.h" |
ff4ae5d9 | 23 | #include "cm3xxx.h" |
71348bca | 24 | #include "cm-regbits-34xx.h" |
4bd5259e | 25 | #include "clockdomain.h" |
71348bca | 26 | |
ff4ae5d9 PW |
27 | static const u8 omap3xxx_cm_idlest_offs[] = { |
28 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 | |
71348bca PW |
29 | }; |
30 | ||
55ae3507 PW |
31 | /* |
32 | * | |
33 | */ | |
34 | ||
35 | static void _write_clktrctrl(u8 c, s16 module, u32 mask) | |
36 | { | |
37 | u32 v; | |
38 | ||
39 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); | |
40 | v &= ~mask; | |
41 | v |= c << __ffs(mask); | |
42 | omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); | |
43 | } | |
44 | ||
f2650d6e | 45 | static bool omap3xxx_cm_is_clkdm_in_hwsup(s16 module, u32 mask) |
55ae3507 PW |
46 | { |
47 | u32 v; | |
55ae3507 PW |
48 | |
49 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); | |
50 | v &= mask; | |
51 | v >>= __ffs(mask); | |
52 | ||
ff4ae5d9 | 53 | return (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; |
55ae3507 PW |
54 | } |
55 | ||
f2650d6e | 56 | static void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) |
55ae3507 PW |
57 | { |
58 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); | |
59 | } | |
60 | ||
f2650d6e | 61 | static void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) |
55ae3507 PW |
62 | { |
63 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); | |
64 | } | |
65 | ||
f2650d6e | 66 | static void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) |
55ae3507 PW |
67 | { |
68 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); | |
69 | } | |
70 | ||
f2650d6e | 71 | static void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) |
55ae3507 PW |
72 | { |
73 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); | |
74 | } | |
75 | ||
55ae3507 PW |
76 | /* |
77 | * | |
78 | */ | |
79 | ||
71348bca | 80 | /** |
ff4ae5d9 | 81 | * omap3xxx_cm_wait_module_ready - wait for a module to leave idle or standby |
021b6ff0 | 82 | * @part: PRCM partition, ignored for OMAP3 |
71348bca PW |
83 | * @prcm_mod: PRCM module offset |
84 | * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) | |
85 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check | |
86 | * | |
ff4ae5d9 PW |
87 | * Wait for the PRCM to indicate that the module identified by |
88 | * (@prcm_mod, @idlest_id, @idlest_shift) is clocked. Return 0 upon | |
89 | * success or -EBUSY if the module doesn't enable in time. | |
71348bca | 90 | */ |
021b6ff0 TK |
91 | static int omap3xxx_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_id, |
92 | u8 idlest_shift) | |
71348bca PW |
93 | { |
94 | int ena = 0, i = 0; | |
95 | u8 cm_idlest_reg; | |
96 | u32 mask; | |
97 | ||
ff4ae5d9 | 98 | if (!idlest_id || (idlest_id > ARRAY_SIZE(omap3xxx_cm_idlest_offs))) |
71348bca PW |
99 | return -EINVAL; |
100 | ||
ff4ae5d9 | 101 | cm_idlest_reg = omap3xxx_cm_idlest_offs[idlest_id - 1]; |
71348bca | 102 | |
64056167 | 103 | mask = 1 << idlest_shift; |
ff4ae5d9 | 104 | ena = 0; |
64056167 | 105 | |
ff4ae5d9 PW |
106 | omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & |
107 | mask) == ena), MAX_MODULE_READY_TIME, i); | |
71348bca PW |
108 | |
109 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | |
110 | } | |
111 | ||
c4ceedcb PW |
112 | /** |
113 | * omap3xxx_cm_split_idlest_reg - split CM_IDLEST reg addr into its components | |
114 | * @idlest_reg: CM_IDLEST* virtual address | |
115 | * @prcm_inst: pointer to an s16 to return the PRCM instance offset | |
116 | * @idlest_reg_id: pointer to a u8 to return the CM_IDLESTx register ID | |
117 | * | |
118 | * XXX This function is only needed until absolute register addresses are | |
119 | * removed from the OMAP struct clk records. | |
120 | */ | |
6c0afb50 | 121 | static int omap3xxx_cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, |
2196a9b8 TK |
122 | s16 *prcm_inst, |
123 | u8 *idlest_reg_id) | |
c4ceedcb PW |
124 | { |
125 | unsigned long offs; | |
126 | u8 idlest_offs; | |
127 | int i; | |
128 | ||
6c0afb50 | 129 | idlest_offs = idlest_reg->offset & 0xff; |
c4ceedcb PW |
130 | for (i = 0; i < ARRAY_SIZE(omap3xxx_cm_idlest_offs); i++) { |
131 | if (idlest_offs == omap3xxx_cm_idlest_offs[i]) { | |
132 | *idlest_reg_id = i + 1; | |
133 | break; | |
134 | } | |
135 | } | |
136 | ||
137 | if (i == ARRAY_SIZE(omap3xxx_cm_idlest_offs)) | |
138 | return -EINVAL; | |
139 | ||
6c0afb50 | 140 | offs = idlest_reg->offset; |
c4ceedcb PW |
141 | offs &= 0xff00; |
142 | *prcm_inst = offs; | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
4bd5259e PW |
147 | /* Clockdomain low-level operations */ |
148 | ||
149 | static int omap3xxx_clkdm_add_sleepdep(struct clockdomain *clkdm1, | |
150 | struct clockdomain *clkdm2) | |
151 | { | |
152 | omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), | |
153 | clkdm1->pwrdm.ptr->prcm_offs, | |
154 | OMAP3430_CM_SLEEPDEP); | |
155 | return 0; | |
156 | } | |
157 | ||
158 | static int omap3xxx_clkdm_del_sleepdep(struct clockdomain *clkdm1, | |
159 | struct clockdomain *clkdm2) | |
160 | { | |
161 | omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), | |
162 | clkdm1->pwrdm.ptr->prcm_offs, | |
163 | OMAP3430_CM_SLEEPDEP); | |
164 | return 0; | |
165 | } | |
166 | ||
167 | static int omap3xxx_clkdm_read_sleepdep(struct clockdomain *clkdm1, | |
168 | struct clockdomain *clkdm2) | |
169 | { | |
170 | return omap2_cm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, | |
171 | OMAP3430_CM_SLEEPDEP, | |
172 | (1 << clkdm2->dep_bit)); | |
173 | } | |
174 | ||
175 | static int omap3xxx_clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) | |
176 | { | |
177 | struct clkdm_dep *cd; | |
178 | u32 mask = 0; | |
179 | ||
180 | for (cd = clkdm->sleepdep_srcs; cd && cd->clkdm_name; cd++) { | |
181 | if (!cd->clkdm) | |
182 | continue; /* only happens if data is erroneous */ | |
183 | ||
184 | mask |= 1 << cd->clkdm->dep_bit; | |
92493870 | 185 | cd->sleepdep_usecount = 0; |
4bd5259e PW |
186 | } |
187 | omap2_cm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, | |
188 | OMAP3430_CM_SLEEPDEP); | |
189 | return 0; | |
190 | } | |
191 | ||
192 | static int omap3xxx_clkdm_sleep(struct clockdomain *clkdm) | |
193 | { | |
194 | omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs, | |
195 | clkdm->clktrctrl_mask); | |
196 | return 0; | |
197 | } | |
198 | ||
199 | static int omap3xxx_clkdm_wakeup(struct clockdomain *clkdm) | |
200 | { | |
201 | omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs, | |
202 | clkdm->clktrctrl_mask); | |
203 | return 0; | |
204 | } | |
205 | ||
206 | static void omap3xxx_clkdm_allow_idle(struct clockdomain *clkdm) | |
207 | { | |
92493870 | 208 | if (clkdm->usecount > 0) |
65958fb6 | 209 | clkdm_add_autodeps(clkdm); |
4bd5259e PW |
210 | |
211 | omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
212 | clkdm->clktrctrl_mask); | |
213 | } | |
214 | ||
215 | static void omap3xxx_clkdm_deny_idle(struct clockdomain *clkdm) | |
216 | { | |
217 | omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
218 | clkdm->clktrctrl_mask); | |
219 | ||
92493870 | 220 | if (clkdm->usecount > 0) |
65958fb6 | 221 | clkdm_del_autodeps(clkdm); |
4bd5259e PW |
222 | } |
223 | ||
224 | static int omap3xxx_clkdm_clk_enable(struct clockdomain *clkdm) | |
225 | { | |
226 | bool hwsup = false; | |
227 | ||
228 | if (!clkdm->clktrctrl_mask) | |
229 | return 0; | |
230 | ||
231 | /* | |
232 | * The CLKDM_MISSING_IDLE_REPORTING flag documentation has | |
233 | * more details on the unpleasant problem this is working | |
234 | * around | |
235 | */ | |
236 | if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) && | |
237 | (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) { | |
238 | omap3xxx_clkdm_wakeup(clkdm); | |
239 | return 0; | |
240 | } | |
241 | ||
242 | hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
243 | clkdm->clktrctrl_mask); | |
244 | ||
245 | if (hwsup) { | |
246 | /* Disable HW transitions when we are changing deps */ | |
247 | omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
248 | clkdm->clktrctrl_mask); | |
65958fb6 | 249 | clkdm_add_autodeps(clkdm); |
4bd5259e PW |
250 | omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, |
251 | clkdm->clktrctrl_mask); | |
252 | } else { | |
253 | if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP) | |
254 | omap3xxx_clkdm_wakeup(clkdm); | |
255 | } | |
256 | ||
257 | return 0; | |
258 | } | |
259 | ||
260 | static int omap3xxx_clkdm_clk_disable(struct clockdomain *clkdm) | |
261 | { | |
262 | bool hwsup = false; | |
263 | ||
264 | if (!clkdm->clktrctrl_mask) | |
265 | return 0; | |
266 | ||
267 | /* | |
268 | * The CLKDM_MISSING_IDLE_REPORTING flag documentation has | |
269 | * more details on the unpleasant problem this is working | |
270 | * around | |
271 | */ | |
272 | if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING && | |
273 | !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) { | |
274 | omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
275 | clkdm->clktrctrl_mask); | |
276 | return 0; | |
277 | } | |
278 | ||
279 | hwsup = omap3xxx_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
280 | clkdm->clktrctrl_mask); | |
281 | ||
282 | if (hwsup) { | |
283 | /* Disable HW transitions when we are changing deps */ | |
284 | omap3xxx_cm_clkdm_disable_hwsup(clkdm->pwrdm.ptr->prcm_offs, | |
285 | clkdm->clktrctrl_mask); | |
65958fb6 | 286 | clkdm_del_autodeps(clkdm); |
4bd5259e PW |
287 | omap3xxx_cm_clkdm_enable_hwsup(clkdm->pwrdm.ptr->prcm_offs, |
288 | clkdm->clktrctrl_mask); | |
289 | } else { | |
290 | if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP) | |
291 | omap3xxx_clkdm_sleep(clkdm); | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
297 | struct clkdm_ops omap3_clkdm_operations = { | |
298 | .clkdm_add_wkdep = omap2_clkdm_add_wkdep, | |
299 | .clkdm_del_wkdep = omap2_clkdm_del_wkdep, | |
300 | .clkdm_read_wkdep = omap2_clkdm_read_wkdep, | |
301 | .clkdm_clear_all_wkdeps = omap2_clkdm_clear_all_wkdeps, | |
302 | .clkdm_add_sleepdep = omap3xxx_clkdm_add_sleepdep, | |
303 | .clkdm_del_sleepdep = omap3xxx_clkdm_del_sleepdep, | |
304 | .clkdm_read_sleepdep = omap3xxx_clkdm_read_sleepdep, | |
305 | .clkdm_clear_all_sleepdeps = omap3xxx_clkdm_clear_all_sleepdeps, | |
306 | .clkdm_sleep = omap3xxx_clkdm_sleep, | |
307 | .clkdm_wakeup = omap3xxx_clkdm_wakeup, | |
308 | .clkdm_allow_idle = omap3xxx_clkdm_allow_idle, | |
309 | .clkdm_deny_idle = omap3xxx_clkdm_deny_idle, | |
310 | .clkdm_clk_enable = omap3xxx_clkdm_clk_enable, | |
311 | .clkdm_clk_disable = omap3xxx_clkdm_clk_disable, | |
312 | }; | |
313 | ||
f0611a5c PW |
314 | /* |
315 | * Context save/restore code - OMAP3 only | |
316 | */ | |
f0611a5c PW |
317 | struct omap3_cm_regs { |
318 | u32 iva2_cm_clksel1; | |
319 | u32 iva2_cm_clksel2; | |
320 | u32 cm_sysconfig; | |
321 | u32 sgx_cm_clksel; | |
322 | u32 dss_cm_clksel; | |
323 | u32 cam_cm_clksel; | |
324 | u32 per_cm_clksel; | |
325 | u32 emu_cm_clksel; | |
326 | u32 emu_cm_clkstctrl; | |
a8ae645c | 327 | u32 pll_cm_autoidle; |
f0611a5c PW |
328 | u32 pll_cm_autoidle2; |
329 | u32 pll_cm_clksel4; | |
330 | u32 pll_cm_clksel5; | |
331 | u32 pll_cm_clken2; | |
332 | u32 cm_polctrl; | |
333 | u32 iva2_cm_fclken; | |
334 | u32 iva2_cm_clken_pll; | |
335 | u32 core_cm_fclken1; | |
336 | u32 core_cm_fclken3; | |
337 | u32 sgx_cm_fclken; | |
338 | u32 wkup_cm_fclken; | |
339 | u32 dss_cm_fclken; | |
340 | u32 cam_cm_fclken; | |
341 | u32 per_cm_fclken; | |
342 | u32 usbhost_cm_fclken; | |
343 | u32 core_cm_iclken1; | |
344 | u32 core_cm_iclken2; | |
345 | u32 core_cm_iclken3; | |
346 | u32 sgx_cm_iclken; | |
347 | u32 wkup_cm_iclken; | |
348 | u32 dss_cm_iclken; | |
349 | u32 cam_cm_iclken; | |
350 | u32 per_cm_iclken; | |
351 | u32 usbhost_cm_iclken; | |
352 | u32 iva2_cm_autoidle2; | |
353 | u32 mpu_cm_autoidle2; | |
354 | u32 iva2_cm_clkstctrl; | |
355 | u32 mpu_cm_clkstctrl; | |
356 | u32 core_cm_clkstctrl; | |
357 | u32 sgx_cm_clkstctrl; | |
358 | u32 dss_cm_clkstctrl; | |
359 | u32 cam_cm_clkstctrl; | |
360 | u32 per_cm_clkstctrl; | |
361 | u32 neon_cm_clkstctrl; | |
362 | u32 usbhost_cm_clkstctrl; | |
363 | u32 core_cm_autoidle1; | |
364 | u32 core_cm_autoidle2; | |
365 | u32 core_cm_autoidle3; | |
366 | u32 wkup_cm_autoidle; | |
367 | u32 dss_cm_autoidle; | |
368 | u32 cam_cm_autoidle; | |
369 | u32 per_cm_autoidle; | |
370 | u32 usbhost_cm_autoidle; | |
371 | u32 sgx_cm_sleepdep; | |
372 | u32 dss_cm_sleepdep; | |
373 | u32 cam_cm_sleepdep; | |
374 | u32 per_cm_sleepdep; | |
375 | u32 usbhost_cm_sleepdep; | |
376 | u32 cm_clkout_ctrl; | |
377 | }; | |
378 | ||
379 | static struct omap3_cm_regs cm_context; | |
380 | ||
381 | void omap3_cm_save_context(void) | |
382 | { | |
383 | cm_context.iva2_cm_clksel1 = | |
c4d7e58f | 384 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); |
f0611a5c | 385 | cm_context.iva2_cm_clksel2 = |
c4d7e58f | 386 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); |
b21be7bc TK |
387 | cm_context.cm_sysconfig = |
388 | omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_SYSCONFIG); | |
f0611a5c | 389 | cm_context.sgx_cm_clksel = |
c4d7e58f | 390 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); |
f0611a5c | 391 | cm_context.dss_cm_clksel = |
c4d7e58f | 392 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); |
f0611a5c | 393 | cm_context.cam_cm_clksel = |
c4d7e58f | 394 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); |
f0611a5c | 395 | cm_context.per_cm_clksel = |
c4d7e58f | 396 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); |
f0611a5c | 397 | cm_context.emu_cm_clksel = |
c4d7e58f | 398 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); |
f0611a5c | 399 | cm_context.emu_cm_clkstctrl = |
c4d7e58f | 400 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); |
a8ae645c EV |
401 | /* |
402 | * As per erratum i671, ROM code does not respect the PER DPLL | |
403 | * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. | |
404 | * In this case, even though this register has been saved in | |
405 | * scratchpad contents, we need to restore AUTO_PERIPH_DPLL | |
406 | * by ourselves. So, we need to save it anyway. | |
407 | */ | |
408 | cm_context.pll_cm_autoidle = | |
409 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); | |
f0611a5c | 410 | cm_context.pll_cm_autoidle2 = |
c4d7e58f | 411 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); |
f0611a5c | 412 | cm_context.pll_cm_clksel4 = |
c4d7e58f | 413 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); |
f0611a5c | 414 | cm_context.pll_cm_clksel5 = |
c4d7e58f | 415 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); |
f0611a5c | 416 | cm_context.pll_cm_clken2 = |
c4d7e58f | 417 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); |
b21be7bc TK |
418 | cm_context.cm_polctrl = |
419 | omap2_cm_read_mod_reg(OCP_MOD, OMAP3430_CM_POLCTRL); | |
f0611a5c | 420 | cm_context.iva2_cm_fclken = |
c4d7e58f PW |
421 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); |
422 | cm_context.iva2_cm_clken_pll = | |
423 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); | |
f0611a5c | 424 | cm_context.core_cm_fclken1 = |
c4d7e58f | 425 | omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
f0611a5c | 426 | cm_context.core_cm_fclken3 = |
c4d7e58f | 427 | omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); |
f0611a5c | 428 | cm_context.sgx_cm_fclken = |
c4d7e58f | 429 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); |
f0611a5c | 430 | cm_context.wkup_cm_fclken = |
c4d7e58f | 431 | omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); |
f0611a5c | 432 | cm_context.dss_cm_fclken = |
c4d7e58f | 433 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); |
f0611a5c | 434 | cm_context.cam_cm_fclken = |
c4d7e58f | 435 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); |
f0611a5c | 436 | cm_context.per_cm_fclken = |
c4d7e58f | 437 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); |
f0611a5c | 438 | cm_context.usbhost_cm_fclken = |
c4d7e58f | 439 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); |
f0611a5c | 440 | cm_context.core_cm_iclken1 = |
c4d7e58f | 441 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); |
f0611a5c | 442 | cm_context.core_cm_iclken2 = |
c4d7e58f | 443 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); |
f0611a5c | 444 | cm_context.core_cm_iclken3 = |
c4d7e58f | 445 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); |
f0611a5c | 446 | cm_context.sgx_cm_iclken = |
c4d7e58f | 447 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); |
f0611a5c | 448 | cm_context.wkup_cm_iclken = |
c4d7e58f | 449 | omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); |
f0611a5c | 450 | cm_context.dss_cm_iclken = |
c4d7e58f | 451 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); |
f0611a5c | 452 | cm_context.cam_cm_iclken = |
c4d7e58f | 453 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); |
f0611a5c | 454 | cm_context.per_cm_iclken = |
c4d7e58f | 455 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); |
f0611a5c | 456 | cm_context.usbhost_cm_iclken = |
c4d7e58f | 457 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); |
f0611a5c | 458 | cm_context.iva2_cm_autoidle2 = |
c4d7e58f | 459 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); |
f0611a5c | 460 | cm_context.mpu_cm_autoidle2 = |
c4d7e58f | 461 | omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); |
f0611a5c | 462 | cm_context.iva2_cm_clkstctrl = |
c4d7e58f | 463 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 464 | cm_context.mpu_cm_clkstctrl = |
c4d7e58f | 465 | omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 466 | cm_context.core_cm_clkstctrl = |
c4d7e58f | 467 | omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 468 | cm_context.sgx_cm_clkstctrl = |
c4d7e58f | 469 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 470 | cm_context.dss_cm_clkstctrl = |
c4d7e58f | 471 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 472 | cm_context.cam_cm_clkstctrl = |
c4d7e58f | 473 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 474 | cm_context.per_cm_clkstctrl = |
c4d7e58f | 475 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 476 | cm_context.neon_cm_clkstctrl = |
c4d7e58f | 477 | omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 478 | cm_context.usbhost_cm_clkstctrl = |
c4d7e58f PW |
479 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
480 | OMAP2_CM_CLKSTCTRL); | |
f0611a5c | 481 | cm_context.core_cm_autoidle1 = |
c4d7e58f | 482 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); |
f0611a5c | 483 | cm_context.core_cm_autoidle2 = |
c4d7e58f | 484 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); |
f0611a5c | 485 | cm_context.core_cm_autoidle3 = |
c4d7e58f | 486 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); |
f0611a5c | 487 | cm_context.wkup_cm_autoidle = |
c4d7e58f | 488 | omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); |
f0611a5c | 489 | cm_context.dss_cm_autoidle = |
c4d7e58f | 490 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); |
f0611a5c | 491 | cm_context.cam_cm_autoidle = |
c4d7e58f | 492 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); |
f0611a5c | 493 | cm_context.per_cm_autoidle = |
c4d7e58f | 494 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); |
f0611a5c | 495 | cm_context.usbhost_cm_autoidle = |
c4d7e58f | 496 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); |
f0611a5c | 497 | cm_context.sgx_cm_sleepdep = |
c4d7e58f PW |
498 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, |
499 | OMAP3430_CM_SLEEPDEP); | |
f0611a5c | 500 | cm_context.dss_cm_sleepdep = |
c4d7e58f | 501 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); |
f0611a5c | 502 | cm_context.cam_cm_sleepdep = |
c4d7e58f | 503 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); |
f0611a5c | 504 | cm_context.per_cm_sleepdep = |
c4d7e58f | 505 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); |
f0611a5c | 506 | cm_context.usbhost_cm_sleepdep = |
c4d7e58f PW |
507 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
508 | OMAP3430_CM_SLEEPDEP); | |
f0611a5c | 509 | cm_context.cm_clkout_ctrl = |
c4d7e58f PW |
510 | omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, |
511 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | |
f0611a5c PW |
512 | } |
513 | ||
514 | void omap3_cm_restore_context(void) | |
515 | { | |
c4d7e58f PW |
516 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, |
517 | CM_CLKSEL1); | |
518 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | |
519 | CM_CLKSEL2); | |
b21be7bc TK |
520 | omap2_cm_write_mod_reg(cm_context.cm_sysconfig, OCP_MOD, |
521 | OMAP3430_CM_SYSCONFIG); | |
c4d7e58f PW |
522 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, |
523 | CM_CLKSEL); | |
524 | omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | |
525 | CM_CLKSEL); | |
526 | omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | |
527 | CM_CLKSEL); | |
528 | omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, | |
529 | CM_CLKSEL); | |
530 | omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | |
531 | CM_CLKSEL1); | |
532 | omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | |
533 | OMAP2_CM_CLKSTCTRL); | |
a8ae645c EV |
534 | /* |
535 | * As per erratum i671, ROM code does not respect the PER DPLL | |
536 | * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. | |
537 | * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves. | |
538 | */ | |
539 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, | |
540 | CM_AUTOIDLE); | |
c4d7e58f PW |
541 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, |
542 | CM_AUTOIDLE2); | |
543 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, | |
544 | OMAP3430ES2_CM_CLKSEL4); | |
545 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, | |
546 | OMAP3430ES2_CM_CLKSEL5); | |
547 | omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, | |
548 | OMAP3430ES2_CM_CLKEN2); | |
b21be7bc TK |
549 | omap2_cm_write_mod_reg(cm_context.cm_polctrl, OCP_MOD, |
550 | OMAP3430_CM_POLCTRL); | |
c4d7e58f PW |
551 | omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, |
552 | CM_FCLKEN); | |
553 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | |
554 | OMAP3430_CM_CLKEN_PLL); | |
555 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, | |
556 | CM_FCLKEN1); | |
557 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, | |
558 | OMAP3430ES2_CM_FCLKEN3); | |
559 | omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | |
560 | CM_FCLKEN); | |
561 | omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | |
562 | omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | |
563 | CM_FCLKEN); | |
564 | omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | |
565 | CM_FCLKEN); | |
566 | omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, | |
567 | CM_FCLKEN); | |
568 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, | |
569 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | |
570 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, | |
571 | CM_ICLKEN1); | |
572 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, | |
573 | CM_ICLKEN2); | |
574 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, | |
575 | CM_ICLKEN3); | |
576 | omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | |
577 | CM_ICLKEN); | |
578 | omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | |
579 | omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | |
580 | CM_ICLKEN); | |
581 | omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | |
582 | CM_ICLKEN); | |
583 | omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, | |
584 | CM_ICLKEN); | |
585 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, | |
586 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | |
587 | omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, | |
588 | CM_AUTOIDLE2); | |
589 | omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, | |
590 | CM_AUTOIDLE2); | |
591 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | |
592 | OMAP2_CM_CLKSTCTRL); | |
593 | omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, | |
594 | OMAP2_CM_CLKSTCTRL); | |
595 | omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, | |
596 | OMAP2_CM_CLKSTCTRL); | |
597 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | |
598 | OMAP2_CM_CLKSTCTRL); | |
599 | omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | |
600 | OMAP2_CM_CLKSTCTRL); | |
601 | omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | |
602 | OMAP2_CM_CLKSTCTRL); | |
603 | omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | |
604 | OMAP2_CM_CLKSTCTRL); | |
605 | omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | |
606 | OMAP2_CM_CLKSTCTRL); | |
607 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, | |
608 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | |
609 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, | |
610 | CM_AUTOIDLE1); | |
611 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, | |
612 | CM_AUTOIDLE2); | |
613 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, | |
614 | CM_AUTOIDLE3); | |
615 | omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, | |
616 | CM_AUTOIDLE); | |
617 | omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | |
618 | CM_AUTOIDLE); | |
619 | omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | |
620 | CM_AUTOIDLE); | |
621 | omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, | |
622 | CM_AUTOIDLE); | |
623 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, | |
624 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | |
625 | omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | |
626 | OMAP3430_CM_SLEEPDEP); | |
627 | omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | |
628 | OMAP3430_CM_SLEEPDEP); | |
629 | omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | |
630 | OMAP3430_CM_SLEEPDEP); | |
631 | omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | |
632 | OMAP3430_CM_SLEEPDEP); | |
633 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, | |
634 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | |
635 | omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | |
636 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | |
f0611a5c | 637 | } |
c4ceedcb | 638 | |
c6a2d839 TK |
639 | void omap3_cm_save_scratchpad_contents(u32 *ptr) |
640 | { | |
641 | *ptr++ = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); | |
642 | *ptr++ = omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); | |
643 | *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); | |
644 | ||
645 | /* | |
646 | * As per erratum i671, ROM code does not respect the PER DPLL | |
647 | * programming scheme if CM_AUTOIDLE_PLL..AUTO_PERIPH_DPLL == 1. | |
3c4d4c20 | 648 | * Then, in any case, clear these bits to avoid extra latencies. |
c6a2d839 TK |
649 | */ |
650 | *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE) & | |
651 | ~OMAP3430_AUTO_PERIPH_DPLL_MASK; | |
652 | *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); | |
653 | *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); | |
654 | *ptr++ = omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); | |
655 | *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); | |
656 | *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); | |
657 | *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); | |
658 | *ptr++ = omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); | |
659 | } | |
660 | ||
c4ceedcb PW |
661 | /* |
662 | * | |
663 | */ | |
664 | ||
60af58cd | 665 | static const struct cm_ll_data omap3xxx_cm_ll_data = { |
c4ceedcb PW |
666 | .split_idlest_reg = &omap3xxx_cm_split_idlest_reg, |
667 | .wait_module_ready = &omap3xxx_cm_wait_module_ready, | |
668 | }; | |
669 | ||
425dc8b2 | 670 | int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data) |
c4ceedcb | 671 | { |
90129336 TK |
672 | omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base.va + |
673 | OMAP3430_IVA2_MOD); | |
c4ceedcb PW |
674 | return cm_register(&omap3xxx_cm_ll_data); |
675 | } | |
676 | ||
677 | static void __exit omap3xxx_cm_exit(void) | |
678 | { | |
7af13637 | 679 | cm_unregister(&omap3xxx_cm_ll_data); |
c4ceedcb PW |
680 | } |
681 | __exitcall(omap3xxx_cm_exit); |