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71348bca PW |
1 | /* |
2 | * OMAP2/3 CM module functions | |
3 | * | |
4 | * Copyright (C) 2009 Nokia Corporation | |
5 | * Paul Walmsley | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
71348bca PW |
13 | #include <linux/types.h> |
14 | #include <linux/delay.h> | |
15 | #include <linux/spinlock.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/errno.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/io.h> | |
20 | ||
dbc04161 | 21 | #include "soc.h" |
ee0839c2 | 22 | #include "iomap.h" |
4e65331c | 23 | #include "common.h" |
71348bca | 24 | #include "cm.h" |
59fb659b | 25 | #include "cm2xxx_3xxx.h" |
71348bca PW |
26 | #include "cm-regbits-24xx.h" |
27 | #include "cm-regbits-34xx.h" | |
28 | ||
92618ff8 | 29 | /* CM_AUTOIDLE_PLL.AUTO_* bit values for DPLLs */ |
0fd0c21b PW |
30 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
31 | #define OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP 0x3 | |
32 | ||
92618ff8 PW |
33 | /* CM_AUTOIDLE_PLL.AUTO_* bit values for APLLs (OMAP2xxx only) */ |
34 | #define OMAP2XXX_APLL_AUTOIDLE_DISABLE 0x0 | |
35 | #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP 0x3 | |
36 | ||
71348bca | 37 | static const u8 cm_idlest_offs[] = { |
e9b0a2fb | 38 | CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4 |
71348bca PW |
39 | }; |
40 | ||
c4d7e58f | 41 | u32 omap2_cm_read_mod_reg(s16 module, u16 idx) |
59fb659b PW |
42 | { |
43 | return __raw_readl(cm_base + module + idx); | |
44 | } | |
45 | ||
c4d7e58f | 46 | void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) |
59fb659b PW |
47 | { |
48 | __raw_writel(val, cm_base + module + idx); | |
49 | } | |
50 | ||
51 | /* Read-modify-write a register in a CM module. Caller must lock */ | |
c4d7e58f | 52 | u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) |
59fb659b PW |
53 | { |
54 | u32 v; | |
55 | ||
c4d7e58f | 56 | v = omap2_cm_read_mod_reg(module, idx); |
59fb659b PW |
57 | v &= ~mask; |
58 | v |= bits; | |
c4d7e58f | 59 | omap2_cm_write_mod_reg(v, module, idx); |
59fb659b PW |
60 | |
61 | return v; | |
62 | } | |
63 | ||
c4d7e58f | 64 | u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) |
59fb659b | 65 | { |
c4d7e58f | 66 | return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); |
59fb659b PW |
67 | } |
68 | ||
c4d7e58f | 69 | u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) |
59fb659b | 70 | { |
c4d7e58f | 71 | return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); |
59fb659b PW |
72 | } |
73 | ||
55ae3507 PW |
74 | /* |
75 | * | |
76 | */ | |
77 | ||
78 | static void _write_clktrctrl(u8 c, s16 module, u32 mask) | |
79 | { | |
80 | u32 v; | |
81 | ||
82 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); | |
83 | v &= ~mask; | |
84 | v |= c << __ffs(mask); | |
85 | omap2_cm_write_mod_reg(v, module, OMAP2_CM_CLKSTCTRL); | |
86 | } | |
87 | ||
88 | bool omap2_cm_is_clkdm_in_hwsup(s16 module, u32 mask) | |
89 | { | |
90 | u32 v; | |
91 | bool ret = 0; | |
92 | ||
93 | BUG_ON(!cpu_is_omap24xx() && !cpu_is_omap34xx()); | |
94 | ||
95 | v = omap2_cm_read_mod_reg(module, OMAP2_CM_CLKSTCTRL); | |
96 | v &= mask; | |
97 | v >>= __ffs(mask); | |
98 | ||
99 | if (cpu_is_omap24xx()) | |
100 | ret = (v == OMAP24XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; | |
101 | else | |
102 | ret = (v == OMAP34XX_CLKSTCTRL_ENABLE_AUTO) ? 1 : 0; | |
103 | ||
104 | return ret; | |
105 | } | |
106 | ||
107 | void omap2xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) | |
108 | { | |
109 | _write_clktrctrl(OMAP24XX_CLKSTCTRL_ENABLE_AUTO, module, mask); | |
110 | } | |
111 | ||
112 | void omap2xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) | |
113 | { | |
114 | _write_clktrctrl(OMAP24XX_CLKSTCTRL_DISABLE_AUTO, module, mask); | |
115 | } | |
116 | ||
117 | void omap3xxx_cm_clkdm_enable_hwsup(s16 module, u32 mask) | |
118 | { | |
119 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_ENABLE_AUTO, module, mask); | |
120 | } | |
121 | ||
122 | void omap3xxx_cm_clkdm_disable_hwsup(s16 module, u32 mask) | |
123 | { | |
124 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_DISABLE_AUTO, module, mask); | |
125 | } | |
126 | ||
127 | void omap3xxx_cm_clkdm_force_sleep(s16 module, u32 mask) | |
128 | { | |
129 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_SLEEP, module, mask); | |
130 | } | |
131 | ||
132 | void omap3xxx_cm_clkdm_force_wakeup(s16 module, u32 mask) | |
133 | { | |
134 | _write_clktrctrl(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP, module, mask); | |
135 | } | |
136 | ||
0fd0c21b PW |
137 | /* |
138 | * DPLL autoidle control | |
139 | */ | |
140 | ||
141 | static void _omap2xxx_set_dpll_autoidle(u8 m) | |
142 | { | |
143 | u32 v; | |
144 | ||
145 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); | |
146 | v &= ~OMAP24XX_AUTO_DPLL_MASK; | |
147 | v |= m << OMAP24XX_AUTO_DPLL_SHIFT; | |
148 | omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); | |
149 | } | |
150 | ||
151 | void omap2xxx_cm_set_dpll_disable_autoidle(void) | |
152 | { | |
153 | _omap2xxx_set_dpll_autoidle(OMAP2XXX_DPLL_AUTOIDLE_LOW_POWER_STOP); | |
154 | } | |
155 | ||
156 | void omap2xxx_cm_set_dpll_auto_low_power_stop(void) | |
157 | { | |
158 | _omap2xxx_set_dpll_autoidle(DPLL_AUTOIDLE_DISABLE); | |
159 | } | |
55ae3507 | 160 | |
92618ff8 PW |
161 | /* |
162 | * APLL autoidle control | |
163 | */ | |
164 | ||
165 | static void _omap2xxx_set_apll_autoidle(u8 m, u32 mask) | |
166 | { | |
167 | u32 v; | |
168 | ||
169 | v = omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); | |
170 | v &= ~mask; | |
171 | v |= m << __ffs(mask); | |
172 | omap2_cm_write_mod_reg(v, PLL_MOD, CM_AUTOIDLE); | |
173 | } | |
174 | ||
175 | void omap2xxx_cm_set_apll54_disable_autoidle(void) | |
176 | { | |
177 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, | |
178 | OMAP24XX_AUTO_54M_MASK); | |
179 | } | |
180 | ||
181 | void omap2xxx_cm_set_apll54_auto_low_power_stop(void) | |
182 | { | |
183 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, | |
184 | OMAP24XX_AUTO_54M_MASK); | |
185 | } | |
186 | ||
187 | void omap2xxx_cm_set_apll96_disable_autoidle(void) | |
188 | { | |
189 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP, | |
190 | OMAP24XX_AUTO_96M_MASK); | |
191 | } | |
192 | ||
193 | void omap2xxx_cm_set_apll96_auto_low_power_stop(void) | |
194 | { | |
195 | _omap2xxx_set_apll_autoidle(OMAP2XXX_APLL_AUTOIDLE_DISABLE, | |
196 | OMAP24XX_AUTO_96M_MASK); | |
197 | } | |
198 | ||
55ae3507 PW |
199 | /* |
200 | * | |
201 | */ | |
202 | ||
71348bca PW |
203 | /** |
204 | * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby | |
205 | * @prcm_mod: PRCM module offset | |
206 | * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) | |
207 | * @idlest_shift: shift of the bit in the CM_IDLEST* register to check | |
208 | * | |
209 | * XXX document | |
210 | */ | |
211 | int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) | |
212 | { | |
213 | int ena = 0, i = 0; | |
214 | u8 cm_idlest_reg; | |
215 | u32 mask; | |
216 | ||
217 | if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) | |
218 | return -EINVAL; | |
219 | ||
220 | cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; | |
221 | ||
64056167 KH |
222 | mask = 1 << idlest_shift; |
223 | ||
71348bca | 224 | if (cpu_is_omap24xx()) |
64056167 | 225 | ena = mask; |
71348bca PW |
226 | else if (cpu_is_omap34xx()) |
227 | ena = 0; | |
228 | else | |
229 | BUG(); | |
230 | ||
c4d7e58f | 231 | omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), |
6f8b7ff5 | 232 | MAX_MODULE_READY_TIME, i); |
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233 | |
234 | return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; | |
235 | } | |
236 | ||
f0611a5c PW |
237 | /* |
238 | * Context save/restore code - OMAP3 only | |
239 | */ | |
240 | #ifdef CONFIG_ARCH_OMAP3 | |
241 | struct omap3_cm_regs { | |
242 | u32 iva2_cm_clksel1; | |
243 | u32 iva2_cm_clksel2; | |
244 | u32 cm_sysconfig; | |
245 | u32 sgx_cm_clksel; | |
246 | u32 dss_cm_clksel; | |
247 | u32 cam_cm_clksel; | |
248 | u32 per_cm_clksel; | |
249 | u32 emu_cm_clksel; | |
250 | u32 emu_cm_clkstctrl; | |
a8ae645c | 251 | u32 pll_cm_autoidle; |
f0611a5c PW |
252 | u32 pll_cm_autoidle2; |
253 | u32 pll_cm_clksel4; | |
254 | u32 pll_cm_clksel5; | |
255 | u32 pll_cm_clken2; | |
256 | u32 cm_polctrl; | |
257 | u32 iva2_cm_fclken; | |
258 | u32 iva2_cm_clken_pll; | |
259 | u32 core_cm_fclken1; | |
260 | u32 core_cm_fclken3; | |
261 | u32 sgx_cm_fclken; | |
262 | u32 wkup_cm_fclken; | |
263 | u32 dss_cm_fclken; | |
264 | u32 cam_cm_fclken; | |
265 | u32 per_cm_fclken; | |
266 | u32 usbhost_cm_fclken; | |
267 | u32 core_cm_iclken1; | |
268 | u32 core_cm_iclken2; | |
269 | u32 core_cm_iclken3; | |
270 | u32 sgx_cm_iclken; | |
271 | u32 wkup_cm_iclken; | |
272 | u32 dss_cm_iclken; | |
273 | u32 cam_cm_iclken; | |
274 | u32 per_cm_iclken; | |
275 | u32 usbhost_cm_iclken; | |
276 | u32 iva2_cm_autoidle2; | |
277 | u32 mpu_cm_autoidle2; | |
278 | u32 iva2_cm_clkstctrl; | |
279 | u32 mpu_cm_clkstctrl; | |
280 | u32 core_cm_clkstctrl; | |
281 | u32 sgx_cm_clkstctrl; | |
282 | u32 dss_cm_clkstctrl; | |
283 | u32 cam_cm_clkstctrl; | |
284 | u32 per_cm_clkstctrl; | |
285 | u32 neon_cm_clkstctrl; | |
286 | u32 usbhost_cm_clkstctrl; | |
287 | u32 core_cm_autoidle1; | |
288 | u32 core_cm_autoidle2; | |
289 | u32 core_cm_autoidle3; | |
290 | u32 wkup_cm_autoidle; | |
291 | u32 dss_cm_autoidle; | |
292 | u32 cam_cm_autoidle; | |
293 | u32 per_cm_autoidle; | |
294 | u32 usbhost_cm_autoidle; | |
295 | u32 sgx_cm_sleepdep; | |
296 | u32 dss_cm_sleepdep; | |
297 | u32 cam_cm_sleepdep; | |
298 | u32 per_cm_sleepdep; | |
299 | u32 usbhost_cm_sleepdep; | |
300 | u32 cm_clkout_ctrl; | |
301 | }; | |
302 | ||
303 | static struct omap3_cm_regs cm_context; | |
304 | ||
305 | void omap3_cm_save_context(void) | |
306 | { | |
307 | cm_context.iva2_cm_clksel1 = | |
c4d7e58f | 308 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); |
f0611a5c | 309 | cm_context.iva2_cm_clksel2 = |
c4d7e58f | 310 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); |
f0611a5c PW |
311 | cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); |
312 | cm_context.sgx_cm_clksel = | |
c4d7e58f | 313 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); |
f0611a5c | 314 | cm_context.dss_cm_clksel = |
c4d7e58f | 315 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); |
f0611a5c | 316 | cm_context.cam_cm_clksel = |
c4d7e58f | 317 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); |
f0611a5c | 318 | cm_context.per_cm_clksel = |
c4d7e58f | 319 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); |
f0611a5c | 320 | cm_context.emu_cm_clksel = |
c4d7e58f | 321 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); |
f0611a5c | 322 | cm_context.emu_cm_clkstctrl = |
c4d7e58f | 323 | omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); |
a8ae645c EV |
324 | /* |
325 | * As per erratum i671, ROM code does not respect the PER DPLL | |
326 | * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. | |
327 | * In this case, even though this register has been saved in | |
328 | * scratchpad contents, we need to restore AUTO_PERIPH_DPLL | |
329 | * by ourselves. So, we need to save it anyway. | |
330 | */ | |
331 | cm_context.pll_cm_autoidle = | |
332 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE); | |
f0611a5c | 333 | cm_context.pll_cm_autoidle2 = |
c4d7e58f | 334 | omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); |
f0611a5c | 335 | cm_context.pll_cm_clksel4 = |
c4d7e58f | 336 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); |
f0611a5c | 337 | cm_context.pll_cm_clksel5 = |
c4d7e58f | 338 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); |
f0611a5c | 339 | cm_context.pll_cm_clken2 = |
c4d7e58f | 340 | omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); |
f0611a5c PW |
341 | cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); |
342 | cm_context.iva2_cm_fclken = | |
c4d7e58f PW |
343 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); |
344 | cm_context.iva2_cm_clken_pll = | |
345 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); | |
f0611a5c | 346 | cm_context.core_cm_fclken1 = |
c4d7e58f | 347 | omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); |
f0611a5c | 348 | cm_context.core_cm_fclken3 = |
c4d7e58f | 349 | omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); |
f0611a5c | 350 | cm_context.sgx_cm_fclken = |
c4d7e58f | 351 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); |
f0611a5c | 352 | cm_context.wkup_cm_fclken = |
c4d7e58f | 353 | omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); |
f0611a5c | 354 | cm_context.dss_cm_fclken = |
c4d7e58f | 355 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); |
f0611a5c | 356 | cm_context.cam_cm_fclken = |
c4d7e58f | 357 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); |
f0611a5c | 358 | cm_context.per_cm_fclken = |
c4d7e58f | 359 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); |
f0611a5c | 360 | cm_context.usbhost_cm_fclken = |
c4d7e58f | 361 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); |
f0611a5c | 362 | cm_context.core_cm_iclken1 = |
c4d7e58f | 363 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); |
f0611a5c | 364 | cm_context.core_cm_iclken2 = |
c4d7e58f | 365 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); |
f0611a5c | 366 | cm_context.core_cm_iclken3 = |
c4d7e58f | 367 | omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); |
f0611a5c | 368 | cm_context.sgx_cm_iclken = |
c4d7e58f | 369 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); |
f0611a5c | 370 | cm_context.wkup_cm_iclken = |
c4d7e58f | 371 | omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); |
f0611a5c | 372 | cm_context.dss_cm_iclken = |
c4d7e58f | 373 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); |
f0611a5c | 374 | cm_context.cam_cm_iclken = |
c4d7e58f | 375 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); |
f0611a5c | 376 | cm_context.per_cm_iclken = |
c4d7e58f | 377 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); |
f0611a5c | 378 | cm_context.usbhost_cm_iclken = |
c4d7e58f | 379 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); |
f0611a5c | 380 | cm_context.iva2_cm_autoidle2 = |
c4d7e58f | 381 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); |
f0611a5c | 382 | cm_context.mpu_cm_autoidle2 = |
c4d7e58f | 383 | omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); |
f0611a5c | 384 | cm_context.iva2_cm_clkstctrl = |
c4d7e58f | 385 | omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 386 | cm_context.mpu_cm_clkstctrl = |
c4d7e58f | 387 | omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 388 | cm_context.core_cm_clkstctrl = |
c4d7e58f | 389 | omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 390 | cm_context.sgx_cm_clkstctrl = |
c4d7e58f | 391 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 392 | cm_context.dss_cm_clkstctrl = |
c4d7e58f | 393 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 394 | cm_context.cam_cm_clkstctrl = |
c4d7e58f | 395 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 396 | cm_context.per_cm_clkstctrl = |
c4d7e58f | 397 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 398 | cm_context.neon_cm_clkstctrl = |
c4d7e58f | 399 | omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); |
f0611a5c | 400 | cm_context.usbhost_cm_clkstctrl = |
c4d7e58f PW |
401 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
402 | OMAP2_CM_CLKSTCTRL); | |
f0611a5c | 403 | cm_context.core_cm_autoidle1 = |
c4d7e58f | 404 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); |
f0611a5c | 405 | cm_context.core_cm_autoidle2 = |
c4d7e58f | 406 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); |
f0611a5c | 407 | cm_context.core_cm_autoidle3 = |
c4d7e58f | 408 | omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); |
f0611a5c | 409 | cm_context.wkup_cm_autoidle = |
c4d7e58f | 410 | omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); |
f0611a5c | 411 | cm_context.dss_cm_autoidle = |
c4d7e58f | 412 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); |
f0611a5c | 413 | cm_context.cam_cm_autoidle = |
c4d7e58f | 414 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); |
f0611a5c | 415 | cm_context.per_cm_autoidle = |
c4d7e58f | 416 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); |
f0611a5c | 417 | cm_context.usbhost_cm_autoidle = |
c4d7e58f | 418 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); |
f0611a5c | 419 | cm_context.sgx_cm_sleepdep = |
c4d7e58f PW |
420 | omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, |
421 | OMAP3430_CM_SLEEPDEP); | |
f0611a5c | 422 | cm_context.dss_cm_sleepdep = |
c4d7e58f | 423 | omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); |
f0611a5c | 424 | cm_context.cam_cm_sleepdep = |
c4d7e58f | 425 | omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); |
f0611a5c | 426 | cm_context.per_cm_sleepdep = |
c4d7e58f | 427 | omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); |
f0611a5c | 428 | cm_context.usbhost_cm_sleepdep = |
c4d7e58f PW |
429 | omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, |
430 | OMAP3430_CM_SLEEPDEP); | |
f0611a5c | 431 | cm_context.cm_clkout_ctrl = |
c4d7e58f PW |
432 | omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, |
433 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | |
f0611a5c PW |
434 | } |
435 | ||
436 | void omap3_cm_restore_context(void) | |
437 | { | |
c4d7e58f PW |
438 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, |
439 | CM_CLKSEL1); | |
440 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, | |
441 | CM_CLKSEL2); | |
f0611a5c | 442 | __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); |
c4d7e58f PW |
443 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, |
444 | CM_CLKSEL); | |
445 | omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, | |
446 | CM_CLKSEL); | |
447 | omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, | |
448 | CM_CLKSEL); | |
449 | omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, | |
450 | CM_CLKSEL); | |
451 | omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, | |
452 | CM_CLKSEL1); | |
453 | omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, | |
454 | OMAP2_CM_CLKSTCTRL); | |
a8ae645c EV |
455 | /* |
456 | * As per erratum i671, ROM code does not respect the PER DPLL | |
457 | * programming scheme if CM_AUTOIDLE_PLL.AUTO_PERIPH_DPLL == 1. | |
458 | * In this case, we need to restore AUTO_PERIPH_DPLL by ourselves. | |
459 | */ | |
460 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle, PLL_MOD, | |
461 | CM_AUTOIDLE); | |
c4d7e58f PW |
462 | omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, |
463 | CM_AUTOIDLE2); | |
464 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, | |
465 | OMAP3430ES2_CM_CLKSEL4); | |
466 | omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, | |
467 | OMAP3430ES2_CM_CLKSEL5); | |
468 | omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, | |
469 | OMAP3430ES2_CM_CLKEN2); | |
f0611a5c | 470 | __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); |
c4d7e58f PW |
471 | omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, |
472 | CM_FCLKEN); | |
473 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, | |
474 | OMAP3430_CM_CLKEN_PLL); | |
475 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, | |
476 | CM_FCLKEN1); | |
477 | omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, | |
478 | OMAP3430ES2_CM_FCLKEN3); | |
479 | omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, | |
480 | CM_FCLKEN); | |
481 | omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); | |
482 | omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, | |
483 | CM_FCLKEN); | |
484 | omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, | |
485 | CM_FCLKEN); | |
486 | omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, | |
487 | CM_FCLKEN); | |
488 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, | |
489 | OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); | |
490 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, | |
491 | CM_ICLKEN1); | |
492 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, | |
493 | CM_ICLKEN2); | |
494 | omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, | |
495 | CM_ICLKEN3); | |
496 | omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, | |
497 | CM_ICLKEN); | |
498 | omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); | |
499 | omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, | |
500 | CM_ICLKEN); | |
501 | omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, | |
502 | CM_ICLKEN); | |
503 | omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, | |
504 | CM_ICLKEN); | |
505 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, | |
506 | OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); | |
507 | omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, | |
508 | CM_AUTOIDLE2); | |
509 | omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, | |
510 | CM_AUTOIDLE2); | |
511 | omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, | |
512 | OMAP2_CM_CLKSTCTRL); | |
513 | omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, | |
514 | OMAP2_CM_CLKSTCTRL); | |
515 | omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, | |
516 | OMAP2_CM_CLKSTCTRL); | |
517 | omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, | |
518 | OMAP2_CM_CLKSTCTRL); | |
519 | omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, | |
520 | OMAP2_CM_CLKSTCTRL); | |
521 | omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, | |
522 | OMAP2_CM_CLKSTCTRL); | |
523 | omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, | |
524 | OMAP2_CM_CLKSTCTRL); | |
525 | omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, | |
526 | OMAP2_CM_CLKSTCTRL); | |
527 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, | |
528 | OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); | |
529 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, | |
530 | CM_AUTOIDLE1); | |
531 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, | |
532 | CM_AUTOIDLE2); | |
533 | omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, | |
534 | CM_AUTOIDLE3); | |
535 | omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, | |
536 | CM_AUTOIDLE); | |
537 | omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, | |
538 | CM_AUTOIDLE); | |
539 | omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, | |
540 | CM_AUTOIDLE); | |
541 | omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, | |
542 | CM_AUTOIDLE); | |
543 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, | |
544 | OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); | |
545 | omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, | |
546 | OMAP3430_CM_SLEEPDEP); | |
547 | omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, | |
548 | OMAP3430_CM_SLEEPDEP); | |
549 | omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, | |
550 | OMAP3430_CM_SLEEPDEP); | |
551 | omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, | |
552 | OMAP3430_CM_SLEEPDEP); | |
553 | omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, | |
554 | OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); | |
555 | omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, | |
556 | OMAP3_CM_CLKOUT_CTRL_OFFSET); | |
f0611a5c PW |
557 | } |
558 | #endif |