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d2912cb1 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
69d88a00 | 2 | /* |
59fb659b | 3 | * OMAP2+ Clock Management prototypes |
69d88a00 | 4 | * |
d9a16f9a | 5 | * Copyright (C) 2007-2009, 2012 Texas Instruments, Inc. |
9b47267f | 6 | * Copyright (C) 2007-2009 Nokia Corporation |
69d88a00 PW |
7 | * |
8 | * Written by Paul Walmsley | |
69d88a00 | 9 | */ |
59fb659b PW |
10 | #ifndef __ARCH_ASM_MACH_OMAP2_CM_H |
11 | #define __ARCH_ASM_MACH_OMAP2_CM_H | |
69d88a00 | 12 | |
d9e6625c BC |
13 | /* |
14 | * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the | |
15 | * PRCM to request that a module exit the inactive state in the case of | |
16 | * OMAP2 & 3. | |
17 | * In the case of OMAP4 this is the max duration in microseconds for the | |
18 | * module to reach the functionnal state from an inactive state. | |
19 | */ | |
20 | #define MAX_MODULE_READY_TIME 2000 | |
21 | ||
d9a16f9a | 22 | # ifndef __ASSEMBLER__ |
6c0afb50 | 23 | #include <linux/clk/ti.h> |
90129336 TK |
24 | |
25 | #include "prcm-common.h" | |
26 | ||
27 | extern struct omap_domain_base cm_base; | |
28 | extern struct omap_domain_base cm2_base; | |
d9a16f9a PW |
29 | extern void omap2_set_globals_cm(void __iomem *cm, void __iomem *cm2); |
30 | # endif | |
31 | ||
b8f15b7e PW |
32 | /* |
33 | * MAX_MODULE_DISABLE_TIME: max duration in microseconds to wait for | |
34 | * the PRCM to request that a module enter the inactive state in the | |
35 | * case of OMAP2 & 3. In the case of OMAP4 this is the max duration | |
36 | * in microseconds for the module to reach the inactive state from | |
37 | * a functional state. | |
38 | * XXX FSUSB on OMAP4430 takes ~4ms to idle after reset during | |
39 | * kernel init. | |
40 | */ | |
41 | #define MAX_MODULE_DISABLE_TIME 5000 | |
42 | ||
21325b25 PW |
43 | # ifndef __ASSEMBLER__ |
44 | ||
45 | /** | |
46 | * struct cm_ll_data - fn ptrs to per-SoC CM function implementations | |
c4ceedcb PW |
47 | * @split_idlest_reg: ptr to the SoC CM-specific split_idlest_reg impl |
48 | * @wait_module_ready: ptr to the SoC CM-specific wait_module_ready impl | |
a8ae5afa | 49 | * @wait_module_idle: ptr to the SoC CM-specific wait_module_idle impl |
128603f0 TK |
50 | * @module_enable: ptr to the SoC CM-specific module_enable impl |
51 | * @module_disable: ptr to the SoC CM-specific module_disable impl | |
5fa4a3cc | 52 | * @xlate_clkctrl: ptr to the SoC CM-specific clkctrl xlate addr impl |
21325b25 | 53 | */ |
c4ceedcb | 54 | struct cm_ll_data { |
6c0afb50 | 55 | int (*split_idlest_reg)(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, |
c4ceedcb | 56 | u8 *idlest_reg_id); |
021b6ff0 TK |
57 | int (*wait_module_ready)(u8 part, s16 prcm_mod, u16 idlest_reg, |
58 | u8 idlest_shift); | |
a8ae5afa TK |
59 | int (*wait_module_idle)(u8 part, s16 prcm_mod, u16 idlest_reg, |
60 | u8 idlest_shift); | |
128603f0 TK |
61 | void (*module_enable)(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); |
62 | void (*module_disable)(u8 part, u16 inst, u16 clkctrl_offs); | |
5fa4a3cc | 63 | u32 (*xlate_clkctrl)(u8 part, u16 inst, u16 clkctrl_offs); |
c4ceedcb PW |
64 | }; |
65 | ||
6c0afb50 | 66 | extern int cm_split_idlest_reg(struct clk_omap_reg *idlest_reg, s16 *prcm_inst, |
c4ceedcb | 67 | u8 *idlest_reg_id); |
021b6ff0 TK |
68 | int omap_cm_wait_module_ready(u8 part, s16 prcm_mod, u16 idlest_reg, |
69 | u8 idlest_shift); | |
a8ae5afa TK |
70 | int omap_cm_wait_module_idle(u8 part, s16 prcm_mod, u16 idlest_reg, |
71 | u8 idlest_shift); | |
128603f0 TK |
72 | int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs); |
73 | int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs); | |
5fa4a3cc | 74 | u32 omap_cm_xlate_clkctrl(u8 part, u16 inst, u16 clkctrl_offs); |
a529f8de BG |
75 | extern int cm_register(const struct cm_ll_data *cld); |
76 | extern int cm_unregister(const struct cm_ll_data *cld); | |
fe87414f | 77 | int omap_cm_init(void); |
5970ca2d | 78 | int omap2_cm_base_init(void); |
21325b25 PW |
79 | |
80 | # endif | |
81 | ||
69d88a00 | 82 | #endif |