[linux-2.6-block.git] / arch / arm / mach-omap2 / clock36xx.c

/*
 * OMAP36xx-specific clkops
 *
 * Copyright (C) 2010 Texas Instruments, Inc.
 * Copyright (C) 2010 Nokia Corporation
 *
 * Mike Turquette
 * Vijaykumar GN
 * Paul Walmsley
 *
 * Parts of this code are based on code written by
 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
 * Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#undef DEBUG

#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>

#include "clock.h"
#include "clock36xx.h"


/**
 * omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
 *         from HSDivider PWRDN problem Implements Errata ID: i556.
 * @clk: DPLL output struct clk
 *
 * 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
 * dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
 * valueafter their respective PWRDN bits are set.  Any dummy write
 * (Any other value different from the Read value) to the
 * corresponding CM_CLKSEL register will refresh the dividers.
 */
int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
{
	struct clk_hw_omap *parent;
	struct clk_hw *parent_hw;
	u32 dummy_v, orig_v, clksel_shift;
	int ret;

	/* Clear PWRDN bit of HSDIVIDER */
	ret = omap2_dflt_clk_enable(clk);

	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
	parent = to_clk_hw_omap(parent_hw);

	/* Restore the dividers */
	if (!ret) {
		clksel_shift = __ffs(parent->clksel_mask);
		orig_v = __raw_readl(parent->clksel_reg);
		dummy_v = orig_v;

		/* Write any other value different from the Read value */
		dummy_v ^= (1 << clksel_shift);
		__raw_writel(dummy_v, parent->clksel_reg);

		/* Write the original divider */
		__raw_writel(orig_v, parent->clksel_reg);
	}

	return ret;
}
Commit	Line	Data
657ebfad PW	1	/*
	2	* OMAP36xx-specific clkops
	3	*
	4	* Copyright (C) 2010 Texas Instruments, Inc.
	5	* Copyright (C) 2010 Nokia Corporation
	6	*
	7	* Mike Turquette
	8	* Vijaykumar GN
	9	* Paul Walmsley
	10	*
	11	* Parts of this code are based on code written by
	12	* Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu,
	13	* Russell King
	14	*
	15	* This program is free software; you can redistribute it and/or modify
	16	* it under the terms of the GNU General Public License version 2 as
	17	* published by the Free Software Foundation.
	18	*/
	19	#undef DEBUG
	20
	21	#include <linux/kernel.h>
	22	#include <linux/clk.h>
	23	#include <linux/io.h>
	24
657ebfad PW	25	#include "clock.h"
	26	#include "clock36xx.h"
	27
	28
	29	/**
	30	* omap36xx_pwrdn_clk_enable_with_hsdiv_restore - enable clocks suffering
	31	* from HSDivider PWRDN problem Implements Errata ID: i556.
	32	* @clk: DPLL output struct clk
	33	*
	34	* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
	35	* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
	36	* valueafter their respective PWRDN bits are set. Any dummy write
	37	* (Any other value different from the Read value) to the
	38	* corresponding CM_CLKSEL register will refresh the dividers.
	39	*/
b4777a21 RN	40	int omap36xx_pwrdn_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
	41	{
	42	struct clk_hw_omap *parent;
	43	struct clk_hw *parent_hw;
657ebfad PW	44	u32 dummy_v, orig_v, clksel_shift;
	45	int ret;
	46
	47	/* Clear PWRDN bit of HSDIVIDER */
	48	ret = omap2_dflt_clk_enable(clk);
	49
b4777a21 RN	50	parent_hw = __clk_get_hw(__clk_get_parent(clk->clk));
b4777a21 RN	51	parent = to_clk_hw_omap(parent_hw);
b4777a21	52
657ebfad PW	53	/* Restore the dividers */
657ebfad PW	54	if (!ret) {
b4777a21 RN	55	clksel_shift = __ffs(parent->clksel_mask);
b4777a21 RN	56	orig_v = __raw_readl(parent->clksel_reg);
657ebfad PW	57	dummy_v = orig_v;
	58
	59	/* Write any other value different from the Read value */
	60	dummy_v ^= (1 << clksel_shift);
b4777a21	61	__raw_writel(dummy_v, parent->clksel_reg);
657ebfad PW	62
657ebfad PW	63	/* Write the original divider */
b4777a21	64	__raw_writel(orig_v, parent->clksel_reg);
657ebfad PW	65	}
	66
	67	return ret;
	68	}