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b045d080 PW |
1 | /* |
2 | * OMAP3 clock framework | |
3 | * | |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2008 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
542313cc PW |
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
9 | * DPLL bypass clock support added by Roman Tereshonkov | |
10 | * | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Virtual clocks are introduced as convenient tools. | |
15 | * They are sources for other clocks and not supposed | |
16 | * to be requested from drivers directly. | |
b045d080 PW |
17 | */ |
18 | ||
19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
21 | ||
22 | #include <asm/arch/control.h> | |
23 | ||
24 | #include "clock.h" | |
25 | #include "cm.h" | |
26 | #include "cm-regbits-34xx.h" | |
27 | #include "prm.h" | |
28 | #include "prm-regbits-34xx.h" | |
29 | ||
30 | static void omap3_dpll_recalc(struct clk *clk); | |
31 | static void omap3_clkoutx2_recalc(struct clk *clk); | |
542313cc PW |
32 | static void omap3_dpll_allow_idle(struct clk *clk); |
33 | static void omap3_dpll_deny_idle(struct clk *clk); | |
34 | static u32 omap3_dpll_autoidle_read(struct clk *clk); | |
35 | static int omap3_noncore_dpll_enable(struct clk *clk); | |
36 | static void omap3_noncore_dpll_disable(struct clk *clk); | |
b045d080 PW |
37 | |
38 | /* | |
39 | * DPLL1 supplies clock to the MPU. | |
40 | * DPLL2 supplies clock to the IVA2. | |
41 | * DPLL3 supplies CORE domain clocks. | |
42 | * DPLL4 supplies peripheral clocks. | |
43 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | |
44 | */ | |
45 | ||
542313cc PW |
46 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
47 | #define DPLL_LOW_POWER_STOP 0x1 | |
48 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
49 | #define DPLL_LOCKED 0x7 | |
50 | ||
b045d080 PW |
51 | /* PRM CLOCKS */ |
52 | ||
53 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | |
54 | static struct clk omap_32k_fck = { | |
55 | .name = "omap_32k_fck", | |
56 | .rate = 32768, | |
57 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
58 | ALWAYS_ENABLED, | |
59 | .recalc = &propagate_rate, | |
60 | }; | |
61 | ||
62 | static struct clk secure_32k_fck = { | |
63 | .name = "secure_32k_fck", | |
64 | .rate = 32768, | |
65 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
66 | ALWAYS_ENABLED, | |
67 | .recalc = &propagate_rate, | |
68 | }; | |
69 | ||
70 | /* Virtual source clocks for osc_sys_ck */ | |
71 | static struct clk virt_12m_ck = { | |
72 | .name = "virt_12m_ck", | |
73 | .rate = 12000000, | |
74 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
75 | ALWAYS_ENABLED, | |
76 | .recalc = &propagate_rate, | |
77 | }; | |
78 | ||
79 | static struct clk virt_13m_ck = { | |
80 | .name = "virt_13m_ck", | |
81 | .rate = 13000000, | |
82 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
83 | ALWAYS_ENABLED, | |
84 | .recalc = &propagate_rate, | |
85 | }; | |
86 | ||
87 | static struct clk virt_16_8m_ck = { | |
88 | .name = "virt_16_8m_ck", | |
89 | .rate = 16800000, | |
90 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_FIXED | RATE_PROPAGATES | | |
91 | ALWAYS_ENABLED, | |
92 | .recalc = &propagate_rate, | |
93 | }; | |
94 | ||
95 | static struct clk virt_19_2m_ck = { | |
96 | .name = "virt_19_2m_ck", | |
97 | .rate = 19200000, | |
98 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
99 | ALWAYS_ENABLED, | |
100 | .recalc = &propagate_rate, | |
101 | }; | |
102 | ||
103 | static struct clk virt_26m_ck = { | |
104 | .name = "virt_26m_ck", | |
105 | .rate = 26000000, | |
106 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
107 | ALWAYS_ENABLED, | |
108 | .recalc = &propagate_rate, | |
109 | }; | |
110 | ||
111 | static struct clk virt_38_4m_ck = { | |
112 | .name = "virt_38_4m_ck", | |
113 | .rate = 38400000, | |
114 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
115 | ALWAYS_ENABLED, | |
116 | .recalc = &propagate_rate, | |
117 | }; | |
118 | ||
119 | static const struct clksel_rate osc_sys_12m_rates[] = { | |
120 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
121 | { .div = 0 } | |
122 | }; | |
123 | ||
124 | static const struct clksel_rate osc_sys_13m_rates[] = { | |
125 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
126 | { .div = 0 } | |
127 | }; | |
128 | ||
129 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | |
130 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | |
131 | { .div = 0 } | |
132 | }; | |
133 | ||
134 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | |
135 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
136 | { .div = 0 } | |
137 | }; | |
138 | ||
139 | static const struct clksel_rate osc_sys_26m_rates[] = { | |
140 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
141 | { .div = 0 } | |
142 | }; | |
143 | ||
144 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | |
145 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
146 | { .div = 0 } | |
147 | }; | |
148 | ||
149 | static const struct clksel osc_sys_clksel[] = { | |
150 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | |
151 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | |
152 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | |
153 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | |
154 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | |
155 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | |
156 | { .parent = NULL }, | |
157 | }; | |
158 | ||
159 | /* Oscillator clock */ | |
160 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | |
161 | static struct clk osc_sys_ck = { | |
162 | .name = "osc_sys_ck", | |
163 | .init = &omap2_init_clksel_parent, | |
164 | .clksel_reg = OMAP3430_PRM_CLKSEL, | |
165 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | |
166 | .clksel = osc_sys_clksel, | |
167 | /* REVISIT: deal with autoextclkmode? */ | |
168 | .flags = CLOCK_IN_OMAP343X | RATE_FIXED | RATE_PROPAGATES | | |
169 | ALWAYS_ENABLED, | |
170 | .recalc = &omap2_clksel_recalc, | |
171 | }; | |
172 | ||
173 | static const struct clksel_rate div2_rates[] = { | |
174 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
175 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
176 | { .div = 0 } | |
177 | }; | |
178 | ||
179 | static const struct clksel sys_clksel[] = { | |
180 | { .parent = &osc_sys_ck, .rates = div2_rates }, | |
181 | { .parent = NULL } | |
182 | }; | |
183 | ||
184 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | |
185 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | |
186 | static struct clk sys_ck = { | |
187 | .name = "sys_ck", | |
188 | .parent = &osc_sys_ck, | |
189 | .init = &omap2_init_clksel_parent, | |
190 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | |
191 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | |
192 | .clksel = sys_clksel, | |
193 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
194 | .recalc = &omap2_clksel_recalc, | |
195 | }; | |
196 | ||
197 | static struct clk sys_altclk = { | |
198 | .name = "sys_altclk", | |
199 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
200 | .recalc = &propagate_rate, | |
201 | }; | |
202 | ||
203 | /* Optional external clock input for some McBSPs */ | |
204 | static struct clk mcbsp_clks = { | |
205 | .name = "mcbsp_clks", | |
206 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
207 | .recalc = &propagate_rate, | |
208 | }; | |
209 | ||
210 | /* PRM EXTERNAL CLOCK OUTPUT */ | |
211 | ||
212 | static struct clk sys_clkout1 = { | |
213 | .name = "sys_clkout1", | |
214 | .parent = &osc_sys_ck, | |
215 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | |
216 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | |
217 | .flags = CLOCK_IN_OMAP343X, | |
218 | .recalc = &followparent_recalc, | |
219 | }; | |
220 | ||
221 | /* DPLLS */ | |
222 | ||
223 | /* CM CLOCKS */ | |
224 | ||
3760d31f RT |
225 | static const struct clksel_rate dpll_bypass_rates[] = { |
226 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
227 | { .div = 0 } | |
228 | }; | |
229 | ||
230 | static const struct clksel_rate dpll_locked_rates[] = { | |
231 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
232 | { .div = 0 } | |
233 | }; | |
234 | ||
235 | static const struct clksel_rate div16_dpll_rates[] = { | |
236 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
237 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
238 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
239 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
240 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | |
241 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
242 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | |
243 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
244 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | |
245 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | |
246 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | |
247 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | |
248 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | |
249 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | |
250 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | |
251 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | |
252 | { .div = 0 } | |
253 | }; | |
254 | ||
b045d080 PW |
255 | /* DPLL1 */ |
256 | /* MPU clock source */ | |
257 | /* Type: DPLL */ | |
258 | static const struct dpll_data dpll1_dd = { | |
259 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
260 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | |
261 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | |
b045d080 PW |
262 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
263 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | |
542313cc | 264 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
b045d080 PW |
265 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
266 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | |
267 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | |
542313cc PW |
268 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
269 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | |
270 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
271 | .idlest_bit = OMAP3430_ST_MPU_CLK_SHIFT, | |
b045d080 PW |
272 | }; |
273 | ||
274 | static struct clk dpll1_ck = { | |
275 | .name = "dpll1_ck", | |
276 | .parent = &sys_ck, | |
277 | .dpll_data = &dpll1_dd, | |
278 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
279 | .recalc = &omap3_dpll_recalc, | |
280 | }; | |
281 | ||
282 | /* | |
3760d31f RT |
283 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
284 | * DPLL isn't bypassed. | |
b045d080 | 285 | */ |
3760d31f RT |
286 | static struct clk dpll1_x2_ck = { |
287 | .name = "dpll1_x2_ck", | |
b045d080 PW |
288 | .parent = &dpll1_ck, |
289 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
290 | PARENT_CONTROLS_CLOCK, | |
3760d31f RT |
291 | .recalc = &omap3_clkoutx2_recalc, |
292 | }; | |
293 | ||
294 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | |
295 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | |
296 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | |
297 | { .parent = NULL } | |
298 | }; | |
299 | ||
300 | /* | |
301 | * Does not exist in the TRM - needed to separate the M2 divider from | |
302 | * bypass selection in mpu_ck | |
303 | */ | |
304 | static struct clk dpll1_x2m2_ck = { | |
305 | .name = "dpll1_x2m2_ck", | |
306 | .parent = &dpll1_x2_ck, | |
307 | .init = &omap2_init_clksel_parent, | |
308 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | |
309 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | |
310 | .clksel = div16_dpll1_x2m2_clksel, | |
311 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
312 | PARENT_CONTROLS_CLOCK, | |
313 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
314 | }; |
315 | ||
316 | /* DPLL2 */ | |
317 | /* IVA2 clock source */ | |
318 | /* Type: DPLL */ | |
319 | ||
320 | static const struct dpll_data dpll2_dd = { | |
321 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
322 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | |
323 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | |
b045d080 PW |
324 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
325 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | |
542313cc PW |
326 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
327 | (1 << DPLL_LOW_POWER_BYPASS), | |
b045d080 PW |
328 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
329 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | |
330 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | |
542313cc PW |
331 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
332 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | |
333 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | |
334 | .idlest_bit = OMAP3430_ST_IVA2_CLK_SHIFT | |
b045d080 PW |
335 | }; |
336 | ||
337 | static struct clk dpll2_ck = { | |
338 | .name = "dpll2_ck", | |
339 | .parent = &sys_ck, | |
340 | .dpll_data = &dpll2_dd, | |
542313cc PW |
341 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
342 | .enable = &omap3_noncore_dpll_enable, | |
343 | .disable = &omap3_noncore_dpll_disable, | |
b045d080 PW |
344 | .recalc = &omap3_dpll_recalc, |
345 | }; | |
346 | ||
3760d31f RT |
347 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
348 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | |
349 | { .parent = NULL } | |
350 | }; | |
351 | ||
352 | /* | |
353 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | |
354 | * or CLKOUTX2. CLKOUT seems most plausible. | |
355 | */ | |
356 | static struct clk dpll2_m2_ck = { | |
357 | .name = "dpll2_m2_ck", | |
358 | .parent = &dpll2_ck, | |
359 | .init = &omap2_init_clksel_parent, | |
360 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | |
361 | OMAP3430_CM_CLKSEL2_PLL), | |
362 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | |
363 | .clksel = div16_dpll2_m2x2_clksel, | |
364 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
365 | PARENT_CONTROLS_CLOCK, | |
366 | .recalc = &omap2_clksel_recalc, | |
367 | }; | |
368 | ||
542313cc PW |
369 | /* |
370 | * DPLL3 | |
371 | * Source clock for all interfaces and for some device fclks | |
372 | * REVISIT: Also supports fast relock bypass - not included below | |
373 | */ | |
b045d080 PW |
374 | static const struct dpll_data dpll3_dd = { |
375 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
376 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | |
377 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | |
b045d080 PW |
378 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
379 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | |
380 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | |
381 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | |
382 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | |
542313cc PW |
383 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
384 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | |
b045d080 PW |
385 | }; |
386 | ||
387 | static struct clk dpll3_ck = { | |
388 | .name = "dpll3_ck", | |
389 | .parent = &sys_ck, | |
390 | .dpll_data = &dpll3_dd, | |
391 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
392 | .recalc = &omap3_dpll_recalc, | |
393 | }; | |
394 | ||
3760d31f RT |
395 | /* |
396 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
397 | * DPLL isn't bypassed | |
398 | */ | |
399 | static struct clk dpll3_x2_ck = { | |
400 | .name = "dpll3_x2_ck", | |
401 | .parent = &dpll3_ck, | |
402 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
403 | PARENT_CONTROLS_CLOCK, | |
404 | .recalc = &omap3_clkoutx2_recalc, | |
b045d080 PW |
405 | }; |
406 | ||
407 | static const struct clksel_rate div31_dpll3_rates[] = { | |
408 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
409 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
410 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | |
411 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | |
412 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | |
413 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | |
414 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | |
415 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | |
416 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | |
417 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | |
418 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | |
419 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | |
420 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | |
421 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | |
422 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | |
423 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | |
424 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | |
425 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | |
426 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | |
427 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | |
428 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | |
429 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | |
430 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | |
431 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | |
432 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | |
433 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | |
434 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | |
435 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | |
436 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | |
437 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | |
438 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | |
439 | { .div = 0 }, | |
440 | }; | |
441 | ||
442 | static const struct clksel div31_dpll3m2_clksel[] = { | |
443 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | |
444 | { .parent = NULL } | |
445 | }; | |
446 | ||
447 | /* | |
3760d31f RT |
448 | * DPLL3 output M2 |
449 | * REVISIT: This DPLL output divider must be changed in SRAM, so until | |
450 | * that code is ready, this should remain a 'read-only' clksel clock. | |
b045d080 PW |
451 | */ |
452 | static struct clk dpll3_m2_ck = { | |
453 | .name = "dpll3_m2_ck", | |
454 | .parent = &dpll3_ck, | |
455 | .init = &omap2_init_clksel_parent, | |
456 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
457 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | |
458 | .clksel = div31_dpll3m2_clksel, | |
459 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
460 | PARENT_CONTROLS_CLOCK, | |
461 | .recalc = &omap2_clksel_recalc, | |
462 | }; | |
463 | ||
3760d31f RT |
464 | static const struct clksel core_ck_clksel[] = { |
465 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
466 | { .parent = &dpll3_m2_ck, .rates = dpll_locked_rates }, | |
467 | { .parent = NULL } | |
468 | }; | |
469 | ||
b045d080 PW |
470 | static struct clk core_ck = { |
471 | .name = "core_ck", | |
3760d31f RT |
472 | .init = &omap2_init_clksel_parent, |
473 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 474 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
3760d31f | 475 | .clksel = core_ck_clksel, |
b045d080 PW |
476 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
477 | PARENT_CONTROLS_CLOCK, | |
3760d31f | 478 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
479 | }; |
480 | ||
3760d31f RT |
481 | static const struct clksel dpll3_m2x2_ck_clksel[] = { |
482 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
483 | { .parent = &dpll3_x2_ck, .rates = dpll_locked_rates }, | |
484 | { .parent = NULL } | |
b045d080 PW |
485 | }; |
486 | ||
487 | static struct clk dpll3_m2x2_ck = { | |
488 | .name = "dpll3_m2x2_ck", | |
3760d31f RT |
489 | .init = &omap2_init_clksel_parent, |
490 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 491 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
3760d31f | 492 | .clksel = dpll3_m2x2_ck_clksel, |
b045d080 PW |
493 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
494 | PARENT_CONTROLS_CLOCK, | |
3760d31f RT |
495 | .recalc = &omap2_clksel_recalc, |
496 | }; | |
497 | ||
498 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
499 | static const struct clksel div16_dpll3_clksel[] = { | |
500 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | |
501 | { .parent = NULL } | |
502 | }; | |
503 | ||
504 | /* This virtual clock is the source for dpll3_m3x2_ck */ | |
505 | static struct clk dpll3_m3_ck = { | |
506 | .name = "dpll3_m3_ck", | |
507 | .parent = &dpll3_ck, | |
508 | .init = &omap2_init_clksel_parent, | |
509 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
510 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | |
511 | .clksel = div16_dpll3_clksel, | |
512 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
513 | PARENT_CONTROLS_CLOCK, | |
514 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
515 | }; |
516 | ||
517 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
518 | static struct clk dpll3_m3x2_ck = { | |
519 | .name = "dpll3_m3x2_ck", | |
3760d31f | 520 | .parent = &dpll3_m3_ck, |
b045d080 PW |
521 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
522 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | |
523 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, | |
3760d31f | 524 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
525 | }; |
526 | ||
3760d31f RT |
527 | static const struct clksel emu_core_alwon_ck_clksel[] = { |
528 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
529 | { .parent = &dpll3_m3x2_ck, .rates = dpll_locked_rates }, | |
b045d080 PW |
530 | { .parent = NULL } |
531 | }; | |
532 | ||
533 | static struct clk emu_core_alwon_ck = { | |
534 | .name = "emu_core_alwon_ck", | |
3760d31f | 535 | .parent = &dpll3_m3x2_ck, |
b045d080 | 536 | .init = &omap2_init_clksel_parent, |
3760d31f | 537 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
542313cc | 538 | .clksel_mask = OMAP3430_ST_CORE_CLK_MASK, |
3760d31f RT |
539 | .clksel = emu_core_alwon_ck_clksel, |
540 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
541 | PARENT_CONTROLS_CLOCK, | |
542 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
543 | }; |
544 | ||
545 | /* DPLL4 */ | |
546 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | |
547 | /* Type: DPLL */ | |
548 | static const struct dpll_data dpll4_dd = { | |
549 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), | |
550 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | |
551 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | |
552 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
553 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | |
542313cc | 554 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
b045d080 PW |
555 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
556 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | |
557 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | |
542313cc PW |
558 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
559 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | |
560 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
561 | .idlest_bit = OMAP3430_ST_PERIPH_CLK_SHIFT, | |
b045d080 PW |
562 | }; |
563 | ||
564 | static struct clk dpll4_ck = { | |
565 | .name = "dpll4_ck", | |
566 | .parent = &sys_ck, | |
567 | .dpll_data = &dpll4_dd, | |
542313cc PW |
568 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
569 | .enable = &omap3_noncore_dpll_enable, | |
570 | .disable = &omap3_noncore_dpll_disable, | |
b045d080 PW |
571 | .recalc = &omap3_dpll_recalc, |
572 | }; | |
573 | ||
574 | /* | |
575 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
3760d31f RT |
576 | * DPLL isn't bypassed -- |
577 | * XXX does this serve any downstream clocks? | |
b045d080 PW |
578 | */ |
579 | static struct clk dpll4_x2_ck = { | |
580 | .name = "dpll4_x2_ck", | |
581 | .parent = &dpll4_ck, | |
582 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
583 | PARENT_CONTROLS_CLOCK, | |
584 | .recalc = &omap3_clkoutx2_recalc, | |
585 | }; | |
586 | ||
587 | static const struct clksel div16_dpll4_clksel[] = { | |
3760d31f | 588 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, |
b045d080 PW |
589 | { .parent = NULL } |
590 | }; | |
591 | ||
3760d31f RT |
592 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
593 | static struct clk dpll4_m2_ck = { | |
594 | .name = "dpll4_m2_ck", | |
595 | .parent = &dpll4_ck, | |
596 | .init = &omap2_init_clksel_parent, | |
597 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | |
598 | .clksel_mask = OMAP3430_DIV_96M_MASK, | |
599 | .clksel = div16_dpll4_clksel, | |
600 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
601 | PARENT_CONTROLS_CLOCK, | |
602 | .recalc = &omap2_clksel_recalc, | |
603 | }; | |
604 | ||
b045d080 PW |
605 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
606 | static struct clk dpll4_m2x2_ck = { | |
607 | .name = "dpll4_m2x2_ck", | |
3760d31f | 608 | .parent = &dpll4_m2_ck, |
b045d080 PW |
609 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
610 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | |
b045d080 | 611 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
612 | .recalc = &omap3_clkoutx2_recalc, |
613 | }; | |
614 | ||
615 | static const struct clksel omap_96m_alwon_fck_clksel[] = { | |
616 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
617 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | |
618 | { .parent = NULL } | |
b045d080 PW |
619 | }; |
620 | ||
621 | static struct clk omap_96m_alwon_fck = { | |
622 | .name = "omap_96m_alwon_fck", | |
623 | .parent = &dpll4_m2x2_ck, | |
3760d31f RT |
624 | .init = &omap2_init_clksel_parent, |
625 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 626 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 627 | .clksel = omap_96m_alwon_fck_clksel, |
b045d080 PW |
628 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
629 | PARENT_CONTROLS_CLOCK, | |
3760d31f | 630 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
631 | }; |
632 | ||
633 | static struct clk omap_96m_fck = { | |
634 | .name = "omap_96m_fck", | |
635 | .parent = &omap_96m_alwon_fck, | |
636 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
637 | PARENT_CONTROLS_CLOCK, | |
638 | .recalc = &followparent_recalc, | |
639 | }; | |
640 | ||
3760d31f RT |
641 | static const struct clksel cm_96m_fck_clksel[] = { |
642 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
643 | { .parent = &dpll4_m2x2_ck, .rates = dpll_locked_rates }, | |
644 | { .parent = NULL } | |
645 | }; | |
646 | ||
b045d080 PW |
647 | static struct clk cm_96m_fck = { |
648 | .name = "cm_96m_fck", | |
649 | .parent = &dpll4_m2x2_ck, | |
3760d31f RT |
650 | .init = &omap2_init_clksel_parent, |
651 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 652 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 653 | .clksel = cm_96m_fck_clksel, |
b045d080 PW |
654 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
655 | PARENT_CONTROLS_CLOCK, | |
3760d31f RT |
656 | .recalc = &omap2_clksel_recalc, |
657 | }; | |
658 | ||
659 | /* This virtual clock is the source for dpll4_m3x2_ck */ | |
660 | static struct clk dpll4_m3_ck = { | |
661 | .name = "dpll4_m3_ck", | |
662 | .parent = &dpll4_ck, | |
663 | .init = &omap2_init_clksel_parent, | |
664 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
665 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | |
666 | .clksel = div16_dpll4_clksel, | |
667 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
668 | PARENT_CONTROLS_CLOCK, | |
669 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
670 | }; |
671 | ||
672 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
673 | static struct clk dpll4_m3x2_ck = { | |
674 | .name = "dpll4_m3x2_ck", | |
3760d31f | 675 | .parent = &dpll4_m3_ck, |
b045d080 PW |
676 | .init = &omap2_init_clksel_parent, |
677 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
678 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | |
b045d080 | 679 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
680 | .recalc = &omap3_clkoutx2_recalc, |
681 | }; | |
682 | ||
683 | static const struct clksel virt_omap_54m_fck_clksel[] = { | |
684 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
685 | { .parent = &dpll4_m3x2_ck, .rates = dpll_locked_rates }, | |
686 | { .parent = NULL } | |
687 | }; | |
688 | ||
689 | static struct clk virt_omap_54m_fck = { | |
690 | .name = "virt_omap_54m_fck", | |
691 | .parent = &dpll4_m3x2_ck, | |
692 | .init = &omap2_init_clksel_parent, | |
693 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 694 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f RT |
695 | .clksel = virt_omap_54m_fck_clksel, |
696 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
697 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
698 | .recalc = &omap2_clksel_recalc, |
699 | }; | |
700 | ||
701 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { | |
702 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
703 | { .div = 0 } | |
704 | }; | |
705 | ||
706 | static const struct clksel_rate omap_54m_alt_rates[] = { | |
707 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
708 | { .div = 0 } | |
709 | }; | |
710 | ||
711 | static const struct clksel omap_54m_clksel[] = { | |
3760d31f | 712 | { .parent = &virt_omap_54m_fck, .rates = omap_54m_d4m3x2_rates }, |
b045d080 PW |
713 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
714 | { .parent = NULL } | |
715 | }; | |
716 | ||
717 | static struct clk omap_54m_fck = { | |
718 | .name = "omap_54m_fck", | |
719 | .init = &omap2_init_clksel_parent, | |
720 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
721 | .clksel_mask = OMAP3430_SOURCE_54M, | |
722 | .clksel = omap_54m_clksel, | |
723 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
724 | PARENT_CONTROLS_CLOCK, | |
725 | .recalc = &omap2_clksel_recalc, | |
726 | }; | |
727 | ||
728 | static const struct clksel_rate omap_48m_96md2_rates[] = { | |
729 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
730 | { .div = 0 } | |
731 | }; | |
732 | ||
733 | static const struct clksel_rate omap_48m_alt_rates[] = { | |
734 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
735 | { .div = 0 } | |
736 | }; | |
737 | ||
738 | static const struct clksel omap_48m_clksel[] = { | |
739 | { .parent = &cm_96m_fck, .rates = omap_48m_96md2_rates }, | |
740 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, | |
741 | { .parent = NULL } | |
742 | }; | |
743 | ||
744 | static struct clk omap_48m_fck = { | |
745 | .name = "omap_48m_fck", | |
746 | .init = &omap2_init_clksel_parent, | |
747 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
748 | .clksel_mask = OMAP3430_SOURCE_48M, | |
749 | .clksel = omap_48m_clksel, | |
750 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
751 | PARENT_CONTROLS_CLOCK, | |
752 | .recalc = &omap2_clksel_recalc, | |
753 | }; | |
754 | ||
755 | static struct clk omap_12m_fck = { | |
756 | .name = "omap_12m_fck", | |
757 | .parent = &omap_48m_fck, | |
758 | .fixed_div = 4, | |
759 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
760 | PARENT_CONTROLS_CLOCK, | |
761 | .recalc = &omap2_fixed_divisor_recalc, | |
762 | }; | |
763 | ||
3760d31f RT |
764 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
765 | static struct clk dpll4_m4_ck = { | |
766 | .name = "dpll4_m4_ck", | |
767 | .parent = &dpll4_ck, | |
768 | .init = &omap2_init_clksel_parent, | |
769 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
770 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | |
771 | .clksel = div16_dpll4_clksel, | |
772 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
773 | PARENT_CONTROLS_CLOCK, | |
774 | .recalc = &omap2_clksel_recalc, | |
775 | }; | |
776 | ||
b045d080 PW |
777 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
778 | static struct clk dpll4_m4x2_ck = { | |
779 | .name = "dpll4_m4x2_ck", | |
3760d31f | 780 | .parent = &dpll4_m4_ck, |
b045d080 PW |
781 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
782 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
b045d080 | 783 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
784 | .recalc = &omap3_clkoutx2_recalc, |
785 | }; | |
786 | ||
787 | /* This virtual clock is the source for dpll4_m5x2_ck */ | |
788 | static struct clk dpll4_m5_ck = { | |
789 | .name = "dpll4_m5_ck", | |
790 | .parent = &dpll4_ck, | |
791 | .init = &omap2_init_clksel_parent, | |
792 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | |
793 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | |
794 | .clksel = div16_dpll4_clksel, | |
795 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
796 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
797 | .recalc = &omap2_clksel_recalc, |
798 | }; | |
799 | ||
800 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
801 | static struct clk dpll4_m5x2_ck = { | |
802 | .name = "dpll4_m5x2_ck", | |
3760d31f | 803 | .parent = &dpll4_m5_ck, |
b045d080 PW |
804 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
805 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
b045d080 | 806 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f RT |
807 | .recalc = &omap3_clkoutx2_recalc, |
808 | }; | |
809 | ||
810 | /* This virtual clock is the source for dpll4_m6x2_ck */ | |
811 | static struct clk dpll4_m6_ck = { | |
812 | .name = "dpll4_m6_ck", | |
813 | .parent = &dpll4_ck, | |
814 | .init = &omap2_init_clksel_parent, | |
815 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
816 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | |
817 | .clksel = div16_dpll4_clksel, | |
818 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
819 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
820 | .recalc = &omap2_clksel_recalc, |
821 | }; | |
822 | ||
823 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
824 | static struct clk dpll4_m6x2_ck = { | |
825 | .name = "dpll4_m6x2_ck", | |
3760d31f | 826 | .parent = &dpll4_m6_ck, |
b045d080 PW |
827 | .init = &omap2_init_clksel_parent, |
828 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
829 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | |
b045d080 | 830 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | INVERT_ENABLE, |
3760d31f | 831 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
832 | }; |
833 | ||
834 | static struct clk emu_per_alwon_ck = { | |
835 | .name = "emu_per_alwon_ck", | |
836 | .parent = &dpll4_m6x2_ck, | |
837 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
838 | PARENT_CONTROLS_CLOCK, | |
839 | .recalc = &followparent_recalc, | |
840 | }; | |
841 | ||
842 | /* DPLL5 */ | |
843 | /* Supplies 120MHz clock, USIM source clock */ | |
844 | /* Type: DPLL */ | |
845 | /* 3430ES2 only */ | |
846 | static const struct dpll_data dpll5_dd = { | |
847 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), | |
848 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | |
849 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | |
850 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), | |
851 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | |
542313cc | 852 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
b045d080 PW |
853 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
854 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | |
855 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | |
542313cc PW |
856 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
857 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | |
858 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | |
859 | .idlest_bit = OMAP3430ES2_ST_PERIPH2_CLK_SHIFT, | |
b045d080 PW |
860 | }; |
861 | ||
862 | static struct clk dpll5_ck = { | |
863 | .name = "dpll5_ck", | |
864 | .parent = &sys_ck, | |
865 | .dpll_data = &dpll5_dd, | |
542313cc PW |
866 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES, |
867 | .enable = &omap3_noncore_dpll_enable, | |
868 | .disable = &omap3_noncore_dpll_disable, | |
b045d080 PW |
869 | .recalc = &omap3_dpll_recalc, |
870 | }; | |
871 | ||
3760d31f | 872 | static const struct clksel div16_dpll5_clksel[] = { |
b045d080 PW |
873 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
874 | { .parent = NULL } | |
875 | }; | |
876 | ||
877 | static struct clk dpll5_m2_ck = { | |
878 | .name = "dpll5_m2_ck", | |
879 | .parent = &dpll5_ck, | |
880 | .init = &omap2_init_clksel_parent, | |
881 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | |
882 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | |
3760d31f | 883 | .clksel = div16_dpll5_clksel, |
d756f54e HJ |
884 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | |
885 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
886 | .recalc = &omap2_clksel_recalc, |
887 | }; | |
888 | ||
3760d31f RT |
889 | static const struct clksel omap_120m_fck_clksel[] = { |
890 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
891 | { .parent = &dpll5_m2_ck, .rates = dpll_locked_rates }, | |
892 | { .parent = NULL } | |
893 | }; | |
894 | ||
b045d080 PW |
895 | static struct clk omap_120m_fck = { |
896 | .name = "omap_120m_fck", | |
897 | .parent = &dpll5_m2_ck, | |
3760d31f RT |
898 | .init = &omap2_init_clksel_parent, |
899 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | |
900 | .clksel_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, | |
901 | .clksel = omap_120m_fck_clksel, | |
902 | .flags = CLOCK_IN_OMAP3430ES2 | RATE_PROPAGATES | | |
903 | PARENT_CONTROLS_CLOCK, | |
904 | .recalc = &omap2_clksel_recalc, | |
b045d080 PW |
905 | }; |
906 | ||
907 | /* CM EXTERNAL CLOCK OUTPUTS */ | |
908 | ||
909 | static const struct clksel_rate clkout2_src_core_rates[] = { | |
910 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
911 | { .div = 0 } | |
912 | }; | |
913 | ||
914 | static const struct clksel_rate clkout2_src_sys_rates[] = { | |
915 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
916 | { .div = 0 } | |
917 | }; | |
918 | ||
919 | static const struct clksel_rate clkout2_src_96m_rates[] = { | |
920 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
921 | { .div = 0 } | |
922 | }; | |
923 | ||
924 | static const struct clksel_rate clkout2_src_54m_rates[] = { | |
925 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
926 | { .div = 0 } | |
927 | }; | |
928 | ||
929 | static const struct clksel clkout2_src_clksel[] = { | |
930 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, | |
931 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | |
932 | { .parent = &omap_96m_alwon_fck, .rates = clkout2_src_96m_rates }, | |
933 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | |
934 | { .parent = NULL } | |
935 | }; | |
936 | ||
937 | static struct clk clkout2_src_ck = { | |
938 | .name = "clkout2_src_ck", | |
939 | .init = &omap2_init_clksel_parent, | |
940 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | |
941 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | |
942 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
943 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | |
944 | .clksel = clkout2_src_clksel, | |
945 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
946 | .recalc = &omap2_clksel_recalc, | |
947 | }; | |
948 | ||
949 | static const struct clksel_rate sys_clkout2_rates[] = { | |
950 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
951 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
952 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | |
953 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | |
954 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | |
955 | { .div = 0 }, | |
956 | }; | |
957 | ||
958 | static const struct clksel sys_clkout2_clksel[] = { | |
959 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | |
960 | { .parent = NULL }, | |
961 | }; | |
962 | ||
963 | static struct clk sys_clkout2 = { | |
964 | .name = "sys_clkout2", | |
965 | .init = &omap2_init_clksel_parent, | |
966 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
967 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | |
968 | .clksel = sys_clkout2_clksel, | |
969 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
970 | .recalc = &omap2_clksel_recalc, | |
971 | }; | |
972 | ||
973 | /* CM OUTPUT CLOCKS */ | |
974 | ||
975 | static struct clk corex2_fck = { | |
976 | .name = "corex2_fck", | |
977 | .parent = &dpll3_m2x2_ck, | |
978 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
979 | PARENT_CONTROLS_CLOCK, | |
980 | .recalc = &followparent_recalc, | |
981 | }; | |
982 | ||
983 | /* DPLL power domain clock controls */ | |
984 | ||
985 | static const struct clksel div2_core_clksel[] = { | |
986 | { .parent = &core_ck, .rates = div2_rates }, | |
987 | { .parent = NULL } | |
988 | }; | |
989 | ||
3760d31f RT |
990 | /* |
991 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | |
992 | * may be inconsistent here? | |
993 | */ | |
b045d080 PW |
994 | static struct clk dpll1_fck = { |
995 | .name = "dpll1_fck", | |
996 | .parent = &core_ck, | |
997 | .init = &omap2_init_clksel_parent, | |
998 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
999 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | |
1000 | .clksel = div2_core_clksel, | |
1001 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1002 | PARENT_CONTROLS_CLOCK, | |
1003 | .recalc = &omap2_clksel_recalc, | |
1004 | }; | |
1005 | ||
3760d31f RT |
1006 | /* |
1007 | * MPU clksel: | |
1008 | * If DPLL1 is locked, mpu_ck derives from DPLL1; otherwise, mpu_ck | |
1009 | * derives from the high-frequency bypass clock originating from DPLL3, | |
1010 | * called 'dpll1_fck' | |
1011 | */ | |
1012 | static const struct clksel mpu_clksel[] = { | |
1013 | { .parent = &dpll1_fck, .rates = dpll_bypass_rates }, | |
1014 | { .parent = &dpll1_x2m2_ck, .rates = dpll_locked_rates }, | |
1015 | { .parent = NULL } | |
1016 | }; | |
1017 | ||
1018 | static struct clk mpu_ck = { | |
1019 | .name = "mpu_ck", | |
1020 | .parent = &dpll1_x2m2_ck, | |
1021 | .init = &omap2_init_clksel_parent, | |
1022 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
1023 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | |
1024 | .clksel = mpu_clksel, | |
1025 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1026 | PARENT_CONTROLS_CLOCK, | |
1027 | .recalc = &omap2_clksel_recalc, | |
1028 | }; | |
1029 | ||
1030 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | |
1031 | static const struct clksel_rate arm_fck_rates[] = { | |
1032 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1033 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
1034 | { .div = 0 }, | |
1035 | }; | |
1036 | ||
1037 | static const struct clksel arm_fck_clksel[] = { | |
1038 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | |
1039 | { .parent = NULL } | |
1040 | }; | |
1041 | ||
1042 | static struct clk arm_fck = { | |
1043 | .name = "arm_fck", | |
1044 | .parent = &mpu_ck, | |
1045 | .init = &omap2_init_clksel_parent, | |
1046 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
1047 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | |
1048 | .clksel = arm_fck_clksel, | |
1049 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1050 | PARENT_CONTROLS_CLOCK, | |
1051 | .recalc = &omap2_clksel_recalc, | |
1052 | }; | |
1053 | ||
1054 | /* | |
1055 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | |
1056 | * although it is referenced - so this is a guess | |
1057 | */ | |
1058 | static struct clk emu_mpu_alwon_ck = { | |
1059 | .name = "emu_mpu_alwon_ck", | |
1060 | .parent = &mpu_ck, | |
1061 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1062 | PARENT_CONTROLS_CLOCK, | |
1063 | .recalc = &followparent_recalc, | |
1064 | }; | |
1065 | ||
b045d080 PW |
1066 | static struct clk dpll2_fck = { |
1067 | .name = "dpll2_fck", | |
1068 | .parent = &core_ck, | |
1069 | .init = &omap2_init_clksel_parent, | |
1070 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
1071 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | |
1072 | .clksel = div2_core_clksel, | |
1073 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1074 | PARENT_CONTROLS_CLOCK, | |
1075 | .recalc = &omap2_clksel_recalc, | |
1076 | }; | |
1077 | ||
3760d31f RT |
1078 | /* |
1079 | * IVA2 clksel: | |
1080 | * If DPLL2 is locked, iva2_ck derives from DPLL2; otherwise, iva2_ck | |
1081 | * derives from the high-frequency bypass clock originating from DPLL3, | |
1082 | * called 'dpll2_fck' | |
1083 | */ | |
1084 | ||
1085 | static const struct clksel iva2_clksel[] = { | |
1086 | { .parent = &dpll2_fck, .rates = dpll_bypass_rates }, | |
1087 | { .parent = &dpll2_m2_ck, .rates = dpll_locked_rates }, | |
1088 | { .parent = NULL } | |
1089 | }; | |
1090 | ||
1091 | static struct clk iva2_ck = { | |
1092 | .name = "iva2_ck", | |
1093 | .parent = &dpll2_m2_ck, | |
1094 | .init = &omap2_init_clksel_parent, | |
31c203d4 HD |
1095 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
1096 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
3760d31f RT |
1097 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, |
1098 | OMAP3430_CM_IDLEST_PLL), | |
1099 | .clksel_mask = OMAP3430_ST_IVA2_CLK_MASK, | |
1100 | .clksel = iva2_clksel, | |
31c203d4 | 1101 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, |
3760d31f RT |
1102 | .recalc = &omap2_clksel_recalc, |
1103 | }; | |
1104 | ||
b045d080 PW |
1105 | /* Common interface clocks */ |
1106 | ||
1107 | static struct clk l3_ick = { | |
1108 | .name = "l3_ick", | |
1109 | .parent = &core_ck, | |
1110 | .init = &omap2_init_clksel_parent, | |
1111 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1112 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | |
1113 | .clksel = div2_core_clksel, | |
1114 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1115 | PARENT_CONTROLS_CLOCK, | |
1116 | .recalc = &omap2_clksel_recalc, | |
1117 | }; | |
1118 | ||
1119 | static const struct clksel div2_l3_clksel[] = { | |
1120 | { .parent = &l3_ick, .rates = div2_rates }, | |
1121 | { .parent = NULL } | |
1122 | }; | |
1123 | ||
1124 | static struct clk l4_ick = { | |
1125 | .name = "l4_ick", | |
1126 | .parent = &l3_ick, | |
1127 | .init = &omap2_init_clksel_parent, | |
1128 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1129 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | |
1130 | .clksel = div2_l3_clksel, | |
1131 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1132 | PARENT_CONTROLS_CLOCK, | |
1133 | .recalc = &omap2_clksel_recalc, | |
1134 | ||
1135 | }; | |
1136 | ||
1137 | static const struct clksel div2_l4_clksel[] = { | |
1138 | { .parent = &l4_ick, .rates = div2_rates }, | |
1139 | { .parent = NULL } | |
1140 | }; | |
1141 | ||
1142 | static struct clk rm_ick = { | |
1143 | .name = "rm_ick", | |
1144 | .parent = &l4_ick, | |
1145 | .init = &omap2_init_clksel_parent, | |
1146 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
1147 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | |
1148 | .clksel = div2_l4_clksel, | |
1149 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
1150 | .recalc = &omap2_clksel_recalc, | |
1151 | }; | |
1152 | ||
1153 | /* GFX power domain */ | |
1154 | ||
3760d31f | 1155 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
b045d080 PW |
1156 | |
1157 | static const struct clksel gfx_l3_clksel[] = { | |
1158 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | |
1159 | { .parent = NULL } | |
1160 | }; | |
1161 | ||
1162 | static struct clk gfx_l3_fck = { | |
1163 | .name = "gfx_l3_fck", | |
1164 | .parent = &l3_ick, | |
1165 | .init = &omap2_init_clksel_parent, | |
1166 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
1167 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
1168 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), | |
1169 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
1170 | .clksel = gfx_l3_clksel, | |
1171 | .flags = CLOCK_IN_OMAP3430ES1 | RATE_PROPAGATES, | |
1172 | .recalc = &omap2_clksel_recalc, | |
1173 | }; | |
1174 | ||
1175 | static struct clk gfx_l3_ick = { | |
1176 | .name = "gfx_l3_ick", | |
1177 | .parent = &l3_ick, | |
1178 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
1179 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
1180 | .flags = CLOCK_IN_OMAP3430ES1, | |
1181 | .recalc = &followparent_recalc, | |
1182 | }; | |
1183 | ||
1184 | static struct clk gfx_cg1_ck = { | |
1185 | .name = "gfx_cg1_ck", | |
1186 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
1187 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
1188 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | |
1189 | .flags = CLOCK_IN_OMAP3430ES1, | |
1190 | .recalc = &followparent_recalc, | |
1191 | }; | |
1192 | ||
1193 | static struct clk gfx_cg2_ck = { | |
1194 | .name = "gfx_cg2_ck", | |
1195 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ | |
1196 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), | |
1197 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | |
1198 | .flags = CLOCK_IN_OMAP3430ES1, | |
1199 | .recalc = &followparent_recalc, | |
1200 | }; | |
1201 | ||
1202 | /* SGX power domain - 3430ES2 only */ | |
1203 | ||
1204 | static const struct clksel_rate sgx_core_rates[] = { | |
1205 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1206 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | |
1207 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | |
1208 | { .div = 0 }, | |
1209 | }; | |
1210 | ||
1211 | static const struct clksel_rate sgx_96m_rates[] = { | |
1212 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1213 | { .div = 0 }, | |
1214 | }; | |
1215 | ||
1216 | static const struct clksel sgx_clksel[] = { | |
1217 | { .parent = &core_ck, .rates = sgx_core_rates }, | |
1218 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | |
1219 | { .parent = NULL }, | |
1220 | }; | |
1221 | ||
1222 | static struct clk sgx_fck = { | |
1223 | .name = "sgx_fck", | |
1224 | .init = &omap2_init_clksel_parent, | |
1225 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | |
1226 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | |
1227 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), | |
1228 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | |
1229 | .clksel = sgx_clksel, | |
1230 | .flags = CLOCK_IN_OMAP3430ES2, | |
1231 | .recalc = &omap2_clksel_recalc, | |
1232 | }; | |
1233 | ||
1234 | static struct clk sgx_ick = { | |
1235 | .name = "sgx_ick", | |
1236 | .parent = &l3_ick, | |
1237 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), | |
1238 | .enable_bit = OMAP3430ES2_EN_SGX_SHIFT, | |
1239 | .flags = CLOCK_IN_OMAP3430ES2, | |
1240 | .recalc = &followparent_recalc, | |
1241 | }; | |
1242 | ||
1243 | /* CORE power domain */ | |
1244 | ||
1245 | static struct clk d2d_26m_fck = { | |
1246 | .name = "d2d_26m_fck", | |
1247 | .parent = &sys_ck, | |
1248 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1249 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | |
1250 | .flags = CLOCK_IN_OMAP3430ES1, | |
1251 | .recalc = &followparent_recalc, | |
1252 | }; | |
1253 | ||
1254 | static const struct clksel omap343x_gpt_clksel[] = { | |
1255 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | |
1256 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
1257 | { .parent = NULL} | |
1258 | }; | |
1259 | ||
1260 | static struct clk gpt10_fck = { | |
1261 | .name = "gpt10_fck", | |
1262 | .parent = &sys_ck, | |
1263 | .init = &omap2_init_clksel_parent, | |
1264 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1265 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1266 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1267 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | |
1268 | .clksel = omap343x_gpt_clksel, | |
1269 | .flags = CLOCK_IN_OMAP343X, | |
1270 | .recalc = &omap2_clksel_recalc, | |
1271 | }; | |
1272 | ||
1273 | static struct clk gpt11_fck = { | |
1274 | .name = "gpt11_fck", | |
1275 | .parent = &sys_ck, | |
1276 | .init = &omap2_init_clksel_parent, | |
1277 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1278 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1279 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1280 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | |
1281 | .clksel = omap343x_gpt_clksel, | |
1282 | .flags = CLOCK_IN_OMAP343X, | |
1283 | .recalc = &omap2_clksel_recalc, | |
1284 | }; | |
1285 | ||
1286 | static struct clk cpefuse_fck = { | |
1287 | .name = "cpefuse_fck", | |
1288 | .parent = &sys_ck, | |
1289 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1290 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | |
1291 | .flags = CLOCK_IN_OMAP3430ES2, | |
1292 | .recalc = &followparent_recalc, | |
1293 | }; | |
1294 | ||
1295 | static struct clk ts_fck = { | |
1296 | .name = "ts_fck", | |
1297 | .parent = &omap_32k_fck, | |
1298 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1299 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | |
1300 | .flags = CLOCK_IN_OMAP3430ES2, | |
1301 | .recalc = &followparent_recalc, | |
1302 | }; | |
1303 | ||
1304 | static struct clk usbtll_fck = { | |
1305 | .name = "usbtll_fck", | |
1306 | .parent = &omap_120m_fck, | |
1307 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1308 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1309 | .flags = CLOCK_IN_OMAP3430ES2, | |
1310 | .recalc = &followparent_recalc, | |
1311 | }; | |
1312 | ||
1313 | /* CORE 96M FCLK-derived clocks */ | |
1314 | ||
1315 | static struct clk core_96m_fck = { | |
1316 | .name = "core_96m_fck", | |
1317 | .parent = &omap_96m_fck, | |
1318 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1319 | PARENT_CONTROLS_CLOCK, | |
1320 | .recalc = &followparent_recalc, | |
1321 | }; | |
1322 | ||
1323 | static struct clk mmchs3_fck = { | |
1324 | .name = "mmchs_fck", | |
1325 | .id = 3, | |
1326 | .parent = &core_96m_fck, | |
1327 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1328 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1329 | .flags = CLOCK_IN_OMAP3430ES2, | |
1330 | .recalc = &followparent_recalc, | |
1331 | }; | |
1332 | ||
1333 | static struct clk mmchs2_fck = { | |
1334 | .name = "mmchs_fck", | |
1335 | .id = 2, | |
1336 | .parent = &core_96m_fck, | |
1337 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1338 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1339 | .flags = CLOCK_IN_OMAP343X, | |
1340 | .recalc = &followparent_recalc, | |
1341 | }; | |
1342 | ||
1343 | static struct clk mspro_fck = { | |
1344 | .name = "mspro_fck", | |
1345 | .parent = &core_96m_fck, | |
1346 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1347 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1348 | .flags = CLOCK_IN_OMAP343X, | |
1349 | .recalc = &followparent_recalc, | |
1350 | }; | |
1351 | ||
1352 | static struct clk mmchs1_fck = { | |
1353 | .name = "mmchs_fck", | |
1354 | .id = 1, | |
1355 | .parent = &core_96m_fck, | |
1356 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1357 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1358 | .flags = CLOCK_IN_OMAP343X, | |
1359 | .recalc = &followparent_recalc, | |
1360 | }; | |
1361 | ||
1362 | static struct clk i2c3_fck = { | |
1363 | .name = "i2c_fck", | |
1364 | .id = 3, | |
1365 | .parent = &core_96m_fck, | |
1366 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1367 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1368 | .flags = CLOCK_IN_OMAP343X, | |
1369 | .recalc = &followparent_recalc, | |
1370 | }; | |
1371 | ||
1372 | static struct clk i2c2_fck = { | |
1373 | .name = "i2c_fck", | |
1374 | .id = 2, | |
1375 | .parent = &core_96m_fck, | |
1376 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1377 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1378 | .flags = CLOCK_IN_OMAP343X, | |
1379 | .recalc = &followparent_recalc, | |
1380 | }; | |
1381 | ||
1382 | static struct clk i2c1_fck = { | |
1383 | .name = "i2c_fck", | |
1384 | .id = 1, | |
1385 | .parent = &core_96m_fck, | |
1386 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1387 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1388 | .flags = CLOCK_IN_OMAP343X, | |
1389 | .recalc = &followparent_recalc, | |
1390 | }; | |
1391 | ||
1392 | /* | |
1393 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | |
1394 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | |
1395 | */ | |
1396 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | |
1397 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1398 | { .div = 0 } | |
1399 | }; | |
1400 | ||
1401 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1402 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1403 | { .div = 0 } | |
1404 | }; | |
1405 | ||
1406 | static const struct clksel mcbsp_15_clksel[] = { | |
1407 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | |
1408 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1409 | { .parent = NULL } | |
1410 | }; | |
1411 | ||
1412 | static struct clk mcbsp5_fck = { | |
78673bc8 EV |
1413 | .name = "mcbsp_fck", |
1414 | .id = 5, | |
b045d080 PW |
1415 | .init = &omap2_init_clksel_parent, |
1416 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1417 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1418 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
1419 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | |
1420 | .clksel = mcbsp_15_clksel, | |
1421 | .flags = CLOCK_IN_OMAP343X, | |
1422 | .recalc = &omap2_clksel_recalc, | |
1423 | }; | |
1424 | ||
1425 | static struct clk mcbsp1_fck = { | |
78673bc8 EV |
1426 | .name = "mcbsp_fck", |
1427 | .id = 1, | |
b045d080 PW |
1428 | .init = &omap2_init_clksel_parent, |
1429 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1430 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1431 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1432 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1433 | .clksel = mcbsp_15_clksel, | |
1434 | .flags = CLOCK_IN_OMAP343X, | |
1435 | .recalc = &omap2_clksel_recalc, | |
1436 | }; | |
1437 | ||
1438 | /* CORE_48M_FCK-derived clocks */ | |
1439 | ||
1440 | static struct clk core_48m_fck = { | |
1441 | .name = "core_48m_fck", | |
1442 | .parent = &omap_48m_fck, | |
1443 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1444 | PARENT_CONTROLS_CLOCK, | |
1445 | .recalc = &followparent_recalc, | |
1446 | }; | |
1447 | ||
1448 | static struct clk mcspi4_fck = { | |
1449 | .name = "mcspi_fck", | |
1450 | .id = 4, | |
1451 | .parent = &core_48m_fck, | |
1452 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1453 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1454 | .flags = CLOCK_IN_OMAP343X, | |
1455 | .recalc = &followparent_recalc, | |
1456 | }; | |
1457 | ||
1458 | static struct clk mcspi3_fck = { | |
1459 | .name = "mcspi_fck", | |
1460 | .id = 3, | |
1461 | .parent = &core_48m_fck, | |
1462 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1463 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1464 | .flags = CLOCK_IN_OMAP343X, | |
1465 | .recalc = &followparent_recalc, | |
1466 | }; | |
1467 | ||
1468 | static struct clk mcspi2_fck = { | |
1469 | .name = "mcspi_fck", | |
1470 | .id = 2, | |
1471 | .parent = &core_48m_fck, | |
1472 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1473 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1474 | .flags = CLOCK_IN_OMAP343X, | |
1475 | .recalc = &followparent_recalc, | |
1476 | }; | |
1477 | ||
1478 | static struct clk mcspi1_fck = { | |
1479 | .name = "mcspi_fck", | |
1480 | .id = 1, | |
1481 | .parent = &core_48m_fck, | |
1482 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1483 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1484 | .flags = CLOCK_IN_OMAP343X, | |
1485 | .recalc = &followparent_recalc, | |
1486 | }; | |
1487 | ||
1488 | static struct clk uart2_fck = { | |
1489 | .name = "uart2_fck", | |
1490 | .parent = &core_48m_fck, | |
1491 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1492 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1493 | .flags = CLOCK_IN_OMAP343X, | |
1494 | .recalc = &followparent_recalc, | |
1495 | }; | |
1496 | ||
1497 | static struct clk uart1_fck = { | |
1498 | .name = "uart1_fck", | |
1499 | .parent = &core_48m_fck, | |
1500 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1501 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1502 | .flags = CLOCK_IN_OMAP343X, | |
1503 | .recalc = &followparent_recalc, | |
1504 | }; | |
1505 | ||
1506 | static struct clk fshostusb_fck = { | |
1507 | .name = "fshostusb_fck", | |
1508 | .parent = &core_48m_fck, | |
1509 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1510 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
1511 | .flags = CLOCK_IN_OMAP3430ES1, | |
1512 | .recalc = &followparent_recalc, | |
1513 | }; | |
1514 | ||
1515 | /* CORE_12M_FCK based clocks */ | |
1516 | ||
1517 | static struct clk core_12m_fck = { | |
1518 | .name = "core_12m_fck", | |
1519 | .parent = &omap_12m_fck, | |
1520 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1521 | PARENT_CONTROLS_CLOCK, | |
1522 | .recalc = &followparent_recalc, | |
1523 | }; | |
1524 | ||
1525 | static struct clk hdq_fck = { | |
1526 | .name = "hdq_fck", | |
1527 | .parent = &core_12m_fck, | |
1528 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1529 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1530 | .flags = CLOCK_IN_OMAP343X, | |
1531 | .recalc = &followparent_recalc, | |
1532 | }; | |
1533 | ||
1534 | /* DPLL3-derived clock */ | |
1535 | ||
1536 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | |
1537 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1538 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
1539 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
1540 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
1541 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
1542 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
1543 | { .div = 0 } | |
1544 | }; | |
1545 | ||
1546 | static const struct clksel ssi_ssr_clksel[] = { | |
1547 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | |
1548 | { .parent = NULL } | |
1549 | }; | |
1550 | ||
1551 | static struct clk ssi_ssr_fck = { | |
1552 | .name = "ssi_ssr_fck", | |
1553 | .init = &omap2_init_clksel_parent, | |
1554 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1555 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1556 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1557 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1558 | .clksel = ssi_ssr_clksel, | |
1559 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
1560 | .recalc = &omap2_clksel_recalc, | |
1561 | }; | |
1562 | ||
1563 | static struct clk ssi_sst_fck = { | |
1564 | .name = "ssi_sst_fck", | |
1565 | .parent = &ssi_ssr_fck, | |
1566 | .fixed_div = 2, | |
1567 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK, | |
1568 | .recalc = &omap2_fixed_divisor_recalc, | |
1569 | }; | |
1570 | ||
1571 | ||
1572 | ||
1573 | /* CORE_L3_ICK based clocks */ | |
1574 | ||
1575 | static struct clk core_l3_ick = { | |
1576 | .name = "core_l3_ick", | |
1577 | .parent = &l3_ick, | |
1578 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1579 | PARENT_CONTROLS_CLOCK, | |
1580 | .recalc = &followparent_recalc, | |
1581 | }; | |
1582 | ||
1583 | static struct clk hsotgusb_ick = { | |
1584 | .name = "hsotgusb_ick", | |
1585 | .parent = &core_l3_ick, | |
1586 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1587 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1588 | .flags = CLOCK_IN_OMAP343X, | |
1589 | .recalc = &followparent_recalc, | |
1590 | }; | |
1591 | ||
1592 | static struct clk sdrc_ick = { | |
1593 | .name = "sdrc_ick", | |
1594 | .parent = &core_l3_ick, | |
1595 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1596 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | |
1597 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | |
1598 | .recalc = &followparent_recalc, | |
1599 | }; | |
1600 | ||
1601 | static struct clk gpmc_fck = { | |
1602 | .name = "gpmc_fck", | |
1603 | .parent = &core_l3_ick, | |
1604 | .flags = CLOCK_IN_OMAP343X | PARENT_CONTROLS_CLOCK | | |
1605 | ENABLE_ON_INIT, | |
1606 | .recalc = &followparent_recalc, | |
1607 | }; | |
1608 | ||
1609 | /* SECURITY_L3_ICK based clocks */ | |
1610 | ||
1611 | static struct clk security_l3_ick = { | |
1612 | .name = "security_l3_ick", | |
1613 | .parent = &l3_ick, | |
1614 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1615 | PARENT_CONTROLS_CLOCK, | |
1616 | .recalc = &followparent_recalc, | |
1617 | }; | |
1618 | ||
1619 | static struct clk pka_ick = { | |
1620 | .name = "pka_ick", | |
1621 | .parent = &security_l3_ick, | |
1622 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1623 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | |
1624 | .flags = CLOCK_IN_OMAP343X, | |
1625 | .recalc = &followparent_recalc, | |
1626 | }; | |
1627 | ||
1628 | /* CORE_L4_ICK based clocks */ | |
1629 | ||
1630 | static struct clk core_l4_ick = { | |
1631 | .name = "core_l4_ick", | |
1632 | .parent = &l4_ick, | |
1633 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1634 | PARENT_CONTROLS_CLOCK, | |
1635 | .recalc = &followparent_recalc, | |
1636 | }; | |
1637 | ||
1638 | static struct clk usbtll_ick = { | |
1639 | .name = "usbtll_ick", | |
1640 | .parent = &core_l4_ick, | |
1641 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1642 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
1643 | .flags = CLOCK_IN_OMAP3430ES2, | |
1644 | .recalc = &followparent_recalc, | |
1645 | }; | |
1646 | ||
1647 | static struct clk mmchs3_ick = { | |
1648 | .name = "mmchs_ick", | |
1649 | .id = 3, | |
1650 | .parent = &core_l4_ick, | |
1651 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1652 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
1653 | .flags = CLOCK_IN_OMAP3430ES2, | |
1654 | .recalc = &followparent_recalc, | |
1655 | }; | |
1656 | ||
1657 | /* Intersystem Communication Registers - chassis mode only */ | |
1658 | static struct clk icr_ick = { | |
1659 | .name = "icr_ick", | |
1660 | .parent = &core_l4_ick, | |
1661 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1662 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | |
1663 | .flags = CLOCK_IN_OMAP343X, | |
1664 | .recalc = &followparent_recalc, | |
1665 | }; | |
1666 | ||
1667 | static struct clk aes2_ick = { | |
1668 | .name = "aes2_ick", | |
1669 | .parent = &core_l4_ick, | |
1670 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1671 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | |
1672 | .flags = CLOCK_IN_OMAP343X, | |
1673 | .recalc = &followparent_recalc, | |
1674 | }; | |
1675 | ||
1676 | static struct clk sha12_ick = { | |
1677 | .name = "sha12_ick", | |
1678 | .parent = &core_l4_ick, | |
1679 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1680 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | |
1681 | .flags = CLOCK_IN_OMAP343X, | |
1682 | .recalc = &followparent_recalc, | |
1683 | }; | |
1684 | ||
1685 | static struct clk des2_ick = { | |
1686 | .name = "des2_ick", | |
1687 | .parent = &core_l4_ick, | |
1688 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1689 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | |
1690 | .flags = CLOCK_IN_OMAP343X, | |
1691 | .recalc = &followparent_recalc, | |
1692 | }; | |
1693 | ||
1694 | static struct clk mmchs2_ick = { | |
1695 | .name = "mmchs_ick", | |
1696 | .id = 2, | |
1697 | .parent = &core_l4_ick, | |
1698 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1699 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
1700 | .flags = CLOCK_IN_OMAP343X, | |
1701 | .recalc = &followparent_recalc, | |
1702 | }; | |
1703 | ||
1704 | static struct clk mmchs1_ick = { | |
1705 | .name = "mmchs_ick", | |
1706 | .id = 1, | |
1707 | .parent = &core_l4_ick, | |
1708 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1709 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
1710 | .flags = CLOCK_IN_OMAP343X, | |
1711 | .recalc = &followparent_recalc, | |
1712 | }; | |
1713 | ||
1714 | static struct clk mspro_ick = { | |
1715 | .name = "mspro_ick", | |
1716 | .parent = &core_l4_ick, | |
1717 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1718 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
1719 | .flags = CLOCK_IN_OMAP343X, | |
1720 | .recalc = &followparent_recalc, | |
1721 | }; | |
1722 | ||
1723 | static struct clk hdq_ick = { | |
1724 | .name = "hdq_ick", | |
1725 | .parent = &core_l4_ick, | |
1726 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1727 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
1728 | .flags = CLOCK_IN_OMAP343X, | |
1729 | .recalc = &followparent_recalc, | |
1730 | }; | |
1731 | ||
1732 | static struct clk mcspi4_ick = { | |
1733 | .name = "mcspi_ick", | |
1734 | .id = 4, | |
1735 | .parent = &core_l4_ick, | |
1736 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1737 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
1738 | .flags = CLOCK_IN_OMAP343X, | |
1739 | .recalc = &followparent_recalc, | |
1740 | }; | |
1741 | ||
1742 | static struct clk mcspi3_ick = { | |
1743 | .name = "mcspi_ick", | |
1744 | .id = 3, | |
1745 | .parent = &core_l4_ick, | |
1746 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1747 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
1748 | .flags = CLOCK_IN_OMAP343X, | |
1749 | .recalc = &followparent_recalc, | |
1750 | }; | |
1751 | ||
1752 | static struct clk mcspi2_ick = { | |
1753 | .name = "mcspi_ick", | |
1754 | .id = 2, | |
1755 | .parent = &core_l4_ick, | |
1756 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1757 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
1758 | .flags = CLOCK_IN_OMAP343X, | |
1759 | .recalc = &followparent_recalc, | |
1760 | }; | |
1761 | ||
1762 | static struct clk mcspi1_ick = { | |
1763 | .name = "mcspi_ick", | |
1764 | .id = 1, | |
1765 | .parent = &core_l4_ick, | |
1766 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1767 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
1768 | .flags = CLOCK_IN_OMAP343X, | |
1769 | .recalc = &followparent_recalc, | |
1770 | }; | |
1771 | ||
1772 | static struct clk i2c3_ick = { | |
1773 | .name = "i2c_ick", | |
1774 | .id = 3, | |
1775 | .parent = &core_l4_ick, | |
1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1777 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
1778 | .flags = CLOCK_IN_OMAP343X, | |
1779 | .recalc = &followparent_recalc, | |
1780 | }; | |
1781 | ||
1782 | static struct clk i2c2_ick = { | |
1783 | .name = "i2c_ick", | |
1784 | .id = 2, | |
1785 | .parent = &core_l4_ick, | |
1786 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1787 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
1788 | .flags = CLOCK_IN_OMAP343X, | |
1789 | .recalc = &followparent_recalc, | |
1790 | }; | |
1791 | ||
1792 | static struct clk i2c1_ick = { | |
1793 | .name = "i2c_ick", | |
1794 | .id = 1, | |
1795 | .parent = &core_l4_ick, | |
1796 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1797 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
1798 | .flags = CLOCK_IN_OMAP343X, | |
1799 | .recalc = &followparent_recalc, | |
1800 | }; | |
1801 | ||
1802 | static struct clk uart2_ick = { | |
1803 | .name = "uart2_ick", | |
1804 | .parent = &core_l4_ick, | |
1805 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1806 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
1807 | .flags = CLOCK_IN_OMAP343X, | |
1808 | .recalc = &followparent_recalc, | |
1809 | }; | |
1810 | ||
1811 | static struct clk uart1_ick = { | |
1812 | .name = "uart1_ick", | |
1813 | .parent = &core_l4_ick, | |
1814 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1815 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
1816 | .flags = CLOCK_IN_OMAP343X, | |
1817 | .recalc = &followparent_recalc, | |
1818 | }; | |
1819 | ||
1820 | static struct clk gpt11_ick = { | |
1821 | .name = "gpt11_ick", | |
1822 | .parent = &core_l4_ick, | |
1823 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1824 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1825 | .flags = CLOCK_IN_OMAP343X, | |
1826 | .recalc = &followparent_recalc, | |
1827 | }; | |
1828 | ||
1829 | static struct clk gpt10_ick = { | |
1830 | .name = "gpt10_ick", | |
1831 | .parent = &core_l4_ick, | |
1832 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1833 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1834 | .flags = CLOCK_IN_OMAP343X, | |
1835 | .recalc = &followparent_recalc, | |
1836 | }; | |
1837 | ||
1838 | static struct clk mcbsp5_ick = { | |
78673bc8 EV |
1839 | .name = "mcbsp_ick", |
1840 | .id = 5, | |
b045d080 PW |
1841 | .parent = &core_l4_ick, |
1842 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1843 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1844 | .flags = CLOCK_IN_OMAP343X, | |
1845 | .recalc = &followparent_recalc, | |
1846 | }; | |
1847 | ||
1848 | static struct clk mcbsp1_ick = { | |
78673bc8 EV |
1849 | .name = "mcbsp_ick", |
1850 | .id = 1, | |
b045d080 PW |
1851 | .parent = &core_l4_ick, |
1852 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1853 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1854 | .flags = CLOCK_IN_OMAP343X, | |
1855 | .recalc = &followparent_recalc, | |
1856 | }; | |
1857 | ||
1858 | static struct clk fac_ick = { | |
1859 | .name = "fac_ick", | |
1860 | .parent = &core_l4_ick, | |
1861 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1862 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | |
1863 | .flags = CLOCK_IN_OMAP3430ES1, | |
1864 | .recalc = &followparent_recalc, | |
1865 | }; | |
1866 | ||
1867 | static struct clk mailboxes_ick = { | |
1868 | .name = "mailboxes_ick", | |
1869 | .parent = &core_l4_ick, | |
1870 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1871 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
1872 | .flags = CLOCK_IN_OMAP343X, | |
1873 | .recalc = &followparent_recalc, | |
1874 | }; | |
1875 | ||
1876 | static struct clk omapctrl_ick = { | |
1877 | .name = "omapctrl_ick", | |
1878 | .parent = &core_l4_ick, | |
1879 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1880 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | |
1881 | .flags = CLOCK_IN_OMAP343X | ENABLE_ON_INIT, | |
1882 | .recalc = &followparent_recalc, | |
1883 | }; | |
1884 | ||
1885 | /* SSI_L4_ICK based clocks */ | |
1886 | ||
1887 | static struct clk ssi_l4_ick = { | |
1888 | .name = "ssi_l4_ick", | |
1889 | .parent = &l4_ick, | |
1971a390 JH |
1890 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | |
1891 | PARENT_CONTROLS_CLOCK, | |
b045d080 PW |
1892 | .recalc = &followparent_recalc, |
1893 | }; | |
1894 | ||
1895 | static struct clk ssi_ick = { | |
1896 | .name = "ssi_ick", | |
1897 | .parent = &ssi_l4_ick, | |
1898 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1899 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1900 | .flags = CLOCK_IN_OMAP343X, | |
1901 | .recalc = &followparent_recalc, | |
1902 | }; | |
1903 | ||
1904 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, | |
1905 | * but l4_ick makes more sense to me */ | |
1906 | ||
1907 | static const struct clksel usb_l4_clksel[] = { | |
1908 | { .parent = &l4_ick, .rates = div2_rates }, | |
1909 | { .parent = NULL }, | |
1910 | }; | |
1911 | ||
1912 | static struct clk usb_l4_ick = { | |
1913 | .name = "usb_l4_ick", | |
1914 | .parent = &l4_ick, | |
1915 | .init = &omap2_init_clksel_parent, | |
1916 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1917 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
1918 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1919 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | |
1920 | .clksel = usb_l4_clksel, | |
1921 | .flags = CLOCK_IN_OMAP3430ES1, | |
1922 | .recalc = &omap2_clksel_recalc, | |
1923 | }; | |
1924 | ||
1925 | /* XXX MDM_INTC_ICK, SAD2D_ICK ?? */ | |
1926 | ||
1927 | /* SECURITY_L4_ICK2 based clocks */ | |
1928 | ||
1929 | static struct clk security_l4_ick2 = { | |
1930 | .name = "security_l4_ick2", | |
1931 | .parent = &l4_ick, | |
1932 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
1933 | PARENT_CONTROLS_CLOCK, | |
1934 | .recalc = &followparent_recalc, | |
1935 | }; | |
1936 | ||
1937 | static struct clk aes1_ick = { | |
1938 | .name = "aes1_ick", | |
1939 | .parent = &security_l4_ick2, | |
1940 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1941 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | |
1942 | .flags = CLOCK_IN_OMAP343X, | |
1943 | .recalc = &followparent_recalc, | |
1944 | }; | |
1945 | ||
1946 | static struct clk rng_ick = { | |
1947 | .name = "rng_ick", | |
1948 | .parent = &security_l4_ick2, | |
1949 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1950 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | |
1951 | .flags = CLOCK_IN_OMAP343X, | |
1952 | .recalc = &followparent_recalc, | |
1953 | }; | |
1954 | ||
1955 | static struct clk sha11_ick = { | |
1956 | .name = "sha11_ick", | |
1957 | .parent = &security_l4_ick2, | |
1958 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1959 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | |
1960 | .flags = CLOCK_IN_OMAP343X, | |
1961 | .recalc = &followparent_recalc, | |
1962 | }; | |
1963 | ||
1964 | static struct clk des1_ick = { | |
1965 | .name = "des1_ick", | |
1966 | .parent = &security_l4_ick2, | |
1967 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1968 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | |
1969 | .flags = CLOCK_IN_OMAP343X, | |
1970 | .recalc = &followparent_recalc, | |
1971 | }; | |
1972 | ||
1973 | /* DSS */ | |
3760d31f RT |
1974 | static const struct clksel dss1_alwon_fck_clksel[] = { |
1975 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
1976 | { .parent = &dpll4_m4x2_ck, .rates = dpll_locked_rates }, | |
1977 | { .parent = NULL } | |
1978 | }; | |
b045d080 PW |
1979 | |
1980 | static struct clk dss1_alwon_fck = { | |
1981 | .name = "dss1_alwon_fck", | |
1982 | .parent = &dpll4_m4x2_ck, | |
3760d31f | 1983 | .init = &omap2_init_clksel_parent, |
b045d080 PW |
1984 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
1985 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
3760d31f | 1986 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
542313cc | 1987 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 1988 | .clksel = dss1_alwon_fck_clksel, |
b045d080 | 1989 | .flags = CLOCK_IN_OMAP343X, |
3760d31f | 1990 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
1991 | }; |
1992 | ||
1993 | static struct clk dss_tv_fck = { | |
1994 | .name = "dss_tv_fck", | |
1995 | .parent = &omap_54m_fck, | |
1996 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
1997 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
1998 | .flags = CLOCK_IN_OMAP343X, | |
1999 | .recalc = &followparent_recalc, | |
2000 | }; | |
2001 | ||
2002 | static struct clk dss_96m_fck = { | |
2003 | .name = "dss_96m_fck", | |
2004 | .parent = &omap_96m_fck, | |
2005 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2006 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
2007 | .flags = CLOCK_IN_OMAP343X, | |
2008 | .recalc = &followparent_recalc, | |
2009 | }; | |
2010 | ||
2011 | static struct clk dss2_alwon_fck = { | |
2012 | .name = "dss2_alwon_fck", | |
2013 | .parent = &sys_ck, | |
2014 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2015 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | |
2016 | .flags = CLOCK_IN_OMAP343X, | |
2017 | .recalc = &followparent_recalc, | |
2018 | }; | |
2019 | ||
2020 | static struct clk dss_ick = { | |
2021 | /* Handles both L3 and L4 clocks */ | |
2022 | .name = "dss_ick", | |
2023 | .parent = &l4_ick, | |
2024 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | |
2025 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
2026 | .flags = CLOCK_IN_OMAP343X, | |
2027 | .recalc = &followparent_recalc, | |
2028 | }; | |
2029 | ||
2030 | /* CAM */ | |
2031 | ||
3760d31f RT |
2032 | static const struct clksel cam_mclk_clksel[] = { |
2033 | { .parent = &sys_ck, .rates = dpll_bypass_rates }, | |
2034 | { .parent = &dpll4_m5x2_ck, .rates = dpll_locked_rates }, | |
2035 | { .parent = NULL } | |
2036 | }; | |
2037 | ||
b045d080 PW |
2038 | static struct clk cam_mclk = { |
2039 | .name = "cam_mclk", | |
2040 | .parent = &dpll4_m5x2_ck, | |
3760d31f RT |
2041 | .init = &omap2_init_clksel_parent, |
2042 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
542313cc | 2043 | .clksel_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
3760d31f | 2044 | .clksel = cam_mclk_clksel, |
b045d080 PW |
2045 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), |
2046 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2047 | .flags = CLOCK_IN_OMAP343X, | |
3760d31f | 2048 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
2049 | }; |
2050 | ||
2051 | static struct clk cam_l3_ick = { | |
2052 | .name = "cam_l3_ick", | |
2053 | .parent = &l3_ick, | |
2054 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | |
2055 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2056 | .flags = CLOCK_IN_OMAP343X, | |
2057 | .recalc = &followparent_recalc, | |
2058 | }; | |
2059 | ||
2060 | static struct clk cam_l4_ick = { | |
2061 | .name = "cam_l4_ick", | |
2062 | .parent = &l4_ick, | |
2063 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), | |
2064 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
2065 | .flags = CLOCK_IN_OMAP343X, | |
2066 | .recalc = &followparent_recalc, | |
2067 | }; | |
2068 | ||
2069 | /* USBHOST - 3430ES2 only */ | |
2070 | ||
2071 | static struct clk usbhost_120m_fck = { | |
2072 | .name = "usbhost_120m_fck", | |
2073 | .parent = &omap_120m_fck, | |
2074 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | |
2075 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | |
2076 | .flags = CLOCK_IN_OMAP3430ES2, | |
2077 | .recalc = &followparent_recalc, | |
2078 | }; | |
2079 | ||
2080 | static struct clk usbhost_48m_fck = { | |
2081 | .name = "usbhost_48m_fck", | |
2082 | .parent = &omap_48m_fck, | |
2083 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), | |
2084 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | |
2085 | .flags = CLOCK_IN_OMAP3430ES2, | |
2086 | .recalc = &followparent_recalc, | |
2087 | }; | |
2088 | ||
2089 | static struct clk usbhost_l3_ick = { | |
2090 | .name = "usbhost_l3_ick", | |
2091 | .parent = &l3_ick, | |
2092 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | |
2093 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
2094 | .flags = CLOCK_IN_OMAP3430ES2, | |
2095 | .recalc = &followparent_recalc, | |
2096 | }; | |
2097 | ||
2098 | static struct clk usbhost_l4_ick = { | |
2099 | .name = "usbhost_l4_ick", | |
2100 | .parent = &l4_ick, | |
2101 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), | |
2102 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
2103 | .flags = CLOCK_IN_OMAP3430ES2, | |
2104 | .recalc = &followparent_recalc, | |
2105 | }; | |
2106 | ||
2107 | static struct clk usbhost_sar_fck = { | |
2108 | .name = "usbhost_sar_fck", | |
2109 | .parent = &osc_sys_ck, | |
2110 | .enable_reg = OMAP_PRM_REGADDR(OMAP3430ES2_USBHOST_MOD, PM_PWSTCTRL), | |
2111 | .enable_bit = OMAP3430ES2_SAVEANDRESTORE_SHIFT, | |
2112 | .flags = CLOCK_IN_OMAP3430ES2, | |
2113 | .recalc = &followparent_recalc, | |
2114 | }; | |
2115 | ||
2116 | /* WKUP */ | |
2117 | ||
2118 | static const struct clksel_rate usim_96m_rates[] = { | |
2119 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2120 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2121 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | |
2122 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | |
2123 | { .div = 0 }, | |
2124 | }; | |
2125 | ||
2126 | static const struct clksel_rate usim_120m_rates[] = { | |
2127 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2128 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
2129 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | |
2130 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | |
2131 | { .div = 0 }, | |
2132 | }; | |
2133 | ||
2134 | static const struct clksel usim_clksel[] = { | |
2135 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | |
2136 | { .parent = &omap_120m_fck, .rates = usim_120m_rates }, | |
2137 | { .parent = &sys_ck, .rates = div2_rates }, | |
2138 | { .parent = NULL }, | |
2139 | }; | |
2140 | ||
2141 | /* 3430ES2 only */ | |
2142 | static struct clk usim_fck = { | |
2143 | .name = "usim_fck", | |
2144 | .init = &omap2_init_clksel_parent, | |
2145 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2146 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2147 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2148 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | |
2149 | .clksel = usim_clksel, | |
2150 | .flags = CLOCK_IN_OMAP3430ES2, | |
2151 | .recalc = &omap2_clksel_recalc, | |
2152 | }; | |
2153 | ||
2154 | static struct clk gpt1_fck = { | |
2155 | .name = "gpt1_fck", | |
2156 | .init = &omap2_init_clksel_parent, | |
2157 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2158 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2159 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2160 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | |
2161 | .clksel = omap343x_gpt_clksel, | |
2162 | .flags = CLOCK_IN_OMAP343X, | |
2163 | .recalc = &omap2_clksel_recalc, | |
2164 | }; | |
2165 | ||
2166 | static struct clk wkup_32k_fck = { | |
2167 | .name = "wkup_32k_fck", | |
2168 | .parent = &omap_32k_fck, | |
2169 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2170 | .recalc = &followparent_recalc, | |
2171 | }; | |
2172 | ||
2173 | static struct clk gpio1_fck = { | |
2174 | .name = "gpio1_fck", | |
2175 | .parent = &wkup_32k_fck, | |
2176 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2177 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
2178 | .flags = CLOCK_IN_OMAP343X, | |
2179 | .recalc = &followparent_recalc, | |
2180 | }; | |
2181 | ||
2182 | static struct clk wdt2_fck = { | |
2183 | .name = "wdt2_fck", | |
2184 | .parent = &wkup_32k_fck, | |
2185 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2186 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
2187 | .flags = CLOCK_IN_OMAP343X, | |
2188 | .recalc = &followparent_recalc, | |
2189 | }; | |
2190 | ||
2191 | static struct clk wkup_l4_ick = { | |
2192 | .name = "wkup_l4_ick", | |
2193 | .parent = &sys_ck, | |
2194 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2195 | .recalc = &followparent_recalc, | |
2196 | }; | |
2197 | ||
2198 | /* 3430ES2 only */ | |
2199 | /* Never specifically named in the TRM, so we have to infer a likely name */ | |
2200 | static struct clk usim_ick = { | |
2201 | .name = "usim_ick", | |
2202 | .parent = &wkup_l4_ick, | |
2203 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2204 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2205 | .flags = CLOCK_IN_OMAP3430ES2, | |
2206 | .recalc = &followparent_recalc, | |
2207 | }; | |
2208 | ||
2209 | static struct clk wdt2_ick = { | |
2210 | .name = "wdt2_ick", | |
2211 | .parent = &wkup_l4_ick, | |
2212 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2213 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
2214 | .flags = CLOCK_IN_OMAP343X, | |
2215 | .recalc = &followparent_recalc, | |
2216 | }; | |
2217 | ||
2218 | static struct clk wdt1_ick = { | |
2219 | .name = "wdt1_ick", | |
2220 | .parent = &wkup_l4_ick, | |
2221 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2222 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | |
2223 | .flags = CLOCK_IN_OMAP343X, | |
2224 | .recalc = &followparent_recalc, | |
2225 | }; | |
2226 | ||
2227 | static struct clk gpio1_ick = { | |
2228 | .name = "gpio1_ick", | |
2229 | .parent = &wkup_l4_ick, | |
2230 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2231 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
2232 | .flags = CLOCK_IN_OMAP343X, | |
2233 | .recalc = &followparent_recalc, | |
2234 | }; | |
2235 | ||
2236 | static struct clk omap_32ksync_ick = { | |
2237 | .name = "omap_32ksync_ick", | |
2238 | .parent = &wkup_l4_ick, | |
2239 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2240 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | |
2241 | .flags = CLOCK_IN_OMAP343X, | |
2242 | .recalc = &followparent_recalc, | |
2243 | }; | |
2244 | ||
2245 | static struct clk gpt12_ick = { | |
2246 | .name = "gpt12_ick", | |
2247 | .parent = &wkup_l4_ick, | |
2248 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2249 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | |
2250 | .flags = CLOCK_IN_OMAP343X, | |
2251 | .recalc = &followparent_recalc, | |
2252 | }; | |
2253 | ||
2254 | static struct clk gpt1_ick = { | |
2255 | .name = "gpt1_ick", | |
2256 | .parent = &wkup_l4_ick, | |
2257 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2258 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2259 | .flags = CLOCK_IN_OMAP343X, | |
2260 | .recalc = &followparent_recalc, | |
2261 | }; | |
2262 | ||
2263 | ||
2264 | ||
2265 | /* PER clock domain */ | |
2266 | ||
2267 | static struct clk per_96m_fck = { | |
2268 | .name = "per_96m_fck", | |
2269 | .parent = &omap_96m_alwon_fck, | |
2270 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
2271 | PARENT_CONTROLS_CLOCK, | |
2272 | .recalc = &followparent_recalc, | |
2273 | }; | |
2274 | ||
2275 | static struct clk per_48m_fck = { | |
2276 | .name = "per_48m_fck", | |
2277 | .parent = &omap_48m_fck, | |
2278 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
2279 | PARENT_CONTROLS_CLOCK, | |
2280 | .recalc = &followparent_recalc, | |
2281 | }; | |
2282 | ||
2283 | static struct clk uart3_fck = { | |
2284 | .name = "uart3_fck", | |
2285 | .parent = &per_48m_fck, | |
2286 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2287 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2288 | .flags = CLOCK_IN_OMAP343X, | |
2289 | .recalc = &followparent_recalc, | |
2290 | }; | |
2291 | ||
2292 | static struct clk gpt2_fck = { | |
2293 | .name = "gpt2_fck", | |
2294 | .init = &omap2_init_clksel_parent, | |
2295 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2296 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2297 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2298 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | |
2299 | .clksel = omap343x_gpt_clksel, | |
2300 | .flags = CLOCK_IN_OMAP343X, | |
2301 | .recalc = &omap2_clksel_recalc, | |
2302 | }; | |
2303 | ||
2304 | static struct clk gpt3_fck = { | |
2305 | .name = "gpt3_fck", | |
2306 | .init = &omap2_init_clksel_parent, | |
2307 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2308 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2309 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2310 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | |
2311 | .clksel = omap343x_gpt_clksel, | |
2312 | .flags = CLOCK_IN_OMAP343X, | |
2313 | .recalc = &omap2_clksel_recalc, | |
2314 | }; | |
2315 | ||
2316 | static struct clk gpt4_fck = { | |
2317 | .name = "gpt4_fck", | |
2318 | .init = &omap2_init_clksel_parent, | |
2319 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2320 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2321 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2322 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | |
2323 | .clksel = omap343x_gpt_clksel, | |
2324 | .flags = CLOCK_IN_OMAP343X, | |
2325 | .recalc = &omap2_clksel_recalc, | |
2326 | }; | |
2327 | ||
2328 | static struct clk gpt5_fck = { | |
2329 | .name = "gpt5_fck", | |
2330 | .init = &omap2_init_clksel_parent, | |
2331 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2332 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2333 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2334 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | |
2335 | .clksel = omap343x_gpt_clksel, | |
2336 | .flags = CLOCK_IN_OMAP343X, | |
2337 | .recalc = &omap2_clksel_recalc, | |
2338 | }; | |
2339 | ||
2340 | static struct clk gpt6_fck = { | |
2341 | .name = "gpt6_fck", | |
2342 | .init = &omap2_init_clksel_parent, | |
2343 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2344 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2345 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2346 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | |
2347 | .clksel = omap343x_gpt_clksel, | |
2348 | .flags = CLOCK_IN_OMAP343X, | |
2349 | .recalc = &omap2_clksel_recalc, | |
2350 | }; | |
2351 | ||
2352 | static struct clk gpt7_fck = { | |
2353 | .name = "gpt7_fck", | |
2354 | .init = &omap2_init_clksel_parent, | |
2355 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2356 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2357 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2358 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | |
2359 | .clksel = omap343x_gpt_clksel, | |
2360 | .flags = CLOCK_IN_OMAP343X, | |
2361 | .recalc = &omap2_clksel_recalc, | |
2362 | }; | |
2363 | ||
2364 | static struct clk gpt8_fck = { | |
2365 | .name = "gpt8_fck", | |
2366 | .init = &omap2_init_clksel_parent, | |
2367 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2368 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2369 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2370 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | |
2371 | .clksel = omap343x_gpt_clksel, | |
2372 | .flags = CLOCK_IN_OMAP343X, | |
2373 | .recalc = &omap2_clksel_recalc, | |
2374 | }; | |
2375 | ||
2376 | static struct clk gpt9_fck = { | |
2377 | .name = "gpt9_fck", | |
2378 | .init = &omap2_init_clksel_parent, | |
2379 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2380 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2381 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2382 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | |
2383 | .clksel = omap343x_gpt_clksel, | |
2384 | .flags = CLOCK_IN_OMAP343X, | |
2385 | .recalc = &omap2_clksel_recalc, | |
2386 | }; | |
2387 | ||
2388 | static struct clk per_32k_alwon_fck = { | |
2389 | .name = "per_32k_alwon_fck", | |
2390 | .parent = &omap_32k_fck, | |
2391 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2392 | .recalc = &followparent_recalc, | |
2393 | }; | |
2394 | ||
2395 | static struct clk gpio6_fck = { | |
2396 | .name = "gpio6_fck", | |
2397 | .parent = &per_32k_alwon_fck, | |
2398 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2399 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
b045d080 PW |
2400 | .flags = CLOCK_IN_OMAP343X, |
2401 | .recalc = &followparent_recalc, | |
2402 | }; | |
2403 | ||
2404 | static struct clk gpio5_fck = { | |
2405 | .name = "gpio5_fck", | |
2406 | .parent = &per_32k_alwon_fck, | |
2407 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2408 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
b045d080 PW |
2409 | .flags = CLOCK_IN_OMAP343X, |
2410 | .recalc = &followparent_recalc, | |
2411 | }; | |
2412 | ||
2413 | static struct clk gpio4_fck = { | |
2414 | .name = "gpio4_fck", | |
2415 | .parent = &per_32k_alwon_fck, | |
2416 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2417 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
b045d080 PW |
2418 | .flags = CLOCK_IN_OMAP343X, |
2419 | .recalc = &followparent_recalc, | |
2420 | }; | |
2421 | ||
2422 | static struct clk gpio3_fck = { | |
2423 | .name = "gpio3_fck", | |
2424 | .parent = &per_32k_alwon_fck, | |
2425 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2426 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
b045d080 PW |
2427 | .flags = CLOCK_IN_OMAP343X, |
2428 | .recalc = &followparent_recalc, | |
2429 | }; | |
2430 | ||
2431 | static struct clk gpio2_fck = { | |
2432 | .name = "gpio2_fck", | |
2433 | .parent = &per_32k_alwon_fck, | |
2434 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2435 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
b045d080 PW |
2436 | .flags = CLOCK_IN_OMAP343X, |
2437 | .recalc = &followparent_recalc, | |
2438 | }; | |
2439 | ||
2440 | static struct clk wdt3_fck = { | |
2441 | .name = "wdt3_fck", | |
2442 | .parent = &per_32k_alwon_fck, | |
2443 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2444 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2445 | .flags = CLOCK_IN_OMAP343X, | |
2446 | .recalc = &followparent_recalc, | |
2447 | }; | |
2448 | ||
2449 | static struct clk per_l4_ick = { | |
2450 | .name = "per_l4_ick", | |
2451 | .parent = &l4_ick, | |
2452 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | | |
2453 | PARENT_CONTROLS_CLOCK, | |
2454 | .recalc = &followparent_recalc, | |
2455 | }; | |
2456 | ||
2457 | static struct clk gpio6_ick = { | |
2458 | .name = "gpio6_ick", | |
2459 | .parent = &per_l4_ick, | |
2460 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2461 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | |
2462 | .flags = CLOCK_IN_OMAP343X, | |
2463 | .recalc = &followparent_recalc, | |
2464 | }; | |
2465 | ||
2466 | static struct clk gpio5_ick = { | |
2467 | .name = "gpio5_ick", | |
2468 | .parent = &per_l4_ick, | |
2469 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2470 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | |
2471 | .flags = CLOCK_IN_OMAP343X, | |
2472 | .recalc = &followparent_recalc, | |
2473 | }; | |
2474 | ||
2475 | static struct clk gpio4_ick = { | |
2476 | .name = "gpio4_ick", | |
2477 | .parent = &per_l4_ick, | |
2478 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2479 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | |
2480 | .flags = CLOCK_IN_OMAP343X, | |
2481 | .recalc = &followparent_recalc, | |
2482 | }; | |
2483 | ||
2484 | static struct clk gpio3_ick = { | |
2485 | .name = "gpio3_ick", | |
2486 | .parent = &per_l4_ick, | |
2487 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2488 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | |
2489 | .flags = CLOCK_IN_OMAP343X, | |
2490 | .recalc = &followparent_recalc, | |
2491 | }; | |
2492 | ||
2493 | static struct clk gpio2_ick = { | |
2494 | .name = "gpio2_ick", | |
2495 | .parent = &per_l4_ick, | |
2496 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2497 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | |
2498 | .flags = CLOCK_IN_OMAP343X, | |
2499 | .recalc = &followparent_recalc, | |
2500 | }; | |
2501 | ||
2502 | static struct clk wdt3_ick = { | |
2503 | .name = "wdt3_ick", | |
2504 | .parent = &per_l4_ick, | |
2505 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2506 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
2507 | .flags = CLOCK_IN_OMAP343X, | |
2508 | .recalc = &followparent_recalc, | |
2509 | }; | |
2510 | ||
2511 | static struct clk uart3_ick = { | |
2512 | .name = "uart3_ick", | |
2513 | .parent = &per_l4_ick, | |
2514 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2515 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
2516 | .flags = CLOCK_IN_OMAP343X, | |
2517 | .recalc = &followparent_recalc, | |
2518 | }; | |
2519 | ||
2520 | static struct clk gpt9_ick = { | |
2521 | .name = "gpt9_ick", | |
2522 | .parent = &per_l4_ick, | |
2523 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2524 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2525 | .flags = CLOCK_IN_OMAP343X, | |
2526 | .recalc = &followparent_recalc, | |
2527 | }; | |
2528 | ||
2529 | static struct clk gpt8_ick = { | |
2530 | .name = "gpt8_ick", | |
2531 | .parent = &per_l4_ick, | |
2532 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2533 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2534 | .flags = CLOCK_IN_OMAP343X, | |
2535 | .recalc = &followparent_recalc, | |
2536 | }; | |
2537 | ||
2538 | static struct clk gpt7_ick = { | |
2539 | .name = "gpt7_ick", | |
2540 | .parent = &per_l4_ick, | |
2541 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2542 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2543 | .flags = CLOCK_IN_OMAP343X, | |
2544 | .recalc = &followparent_recalc, | |
2545 | }; | |
2546 | ||
2547 | static struct clk gpt6_ick = { | |
2548 | .name = "gpt6_ick", | |
2549 | .parent = &per_l4_ick, | |
2550 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2551 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2552 | .flags = CLOCK_IN_OMAP343X, | |
2553 | .recalc = &followparent_recalc, | |
2554 | }; | |
2555 | ||
2556 | static struct clk gpt5_ick = { | |
2557 | .name = "gpt5_ick", | |
2558 | .parent = &per_l4_ick, | |
2559 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2560 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2561 | .flags = CLOCK_IN_OMAP343X, | |
2562 | .recalc = &followparent_recalc, | |
2563 | }; | |
2564 | ||
2565 | static struct clk gpt4_ick = { | |
2566 | .name = "gpt4_ick", | |
2567 | .parent = &per_l4_ick, | |
2568 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2569 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2570 | .flags = CLOCK_IN_OMAP343X, | |
2571 | .recalc = &followparent_recalc, | |
2572 | }; | |
2573 | ||
2574 | static struct clk gpt3_ick = { | |
2575 | .name = "gpt3_ick", | |
2576 | .parent = &per_l4_ick, | |
2577 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2578 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2579 | .flags = CLOCK_IN_OMAP343X, | |
2580 | .recalc = &followparent_recalc, | |
2581 | }; | |
2582 | ||
2583 | static struct clk gpt2_ick = { | |
2584 | .name = "gpt2_ick", | |
2585 | .parent = &per_l4_ick, | |
2586 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2587 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2588 | .flags = CLOCK_IN_OMAP343X, | |
2589 | .recalc = &followparent_recalc, | |
2590 | }; | |
2591 | ||
2592 | static struct clk mcbsp2_ick = { | |
78673bc8 EV |
2593 | .name = "mcbsp_ick", |
2594 | .id = 2, | |
b045d080 PW |
2595 | .parent = &per_l4_ick, |
2596 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2597 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2598 | .flags = CLOCK_IN_OMAP343X, | |
2599 | .recalc = &followparent_recalc, | |
2600 | }; | |
2601 | ||
2602 | static struct clk mcbsp3_ick = { | |
78673bc8 EV |
2603 | .name = "mcbsp_ick", |
2604 | .id = 3, | |
b045d080 PW |
2605 | .parent = &per_l4_ick, |
2606 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2607 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2608 | .flags = CLOCK_IN_OMAP343X, | |
2609 | .recalc = &followparent_recalc, | |
2610 | }; | |
2611 | ||
2612 | static struct clk mcbsp4_ick = { | |
78673bc8 EV |
2613 | .name = "mcbsp_ick", |
2614 | .id = 4, | |
b045d080 PW |
2615 | .parent = &per_l4_ick, |
2616 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2617 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2618 | .flags = CLOCK_IN_OMAP343X, | |
2619 | .recalc = &followparent_recalc, | |
2620 | }; | |
2621 | ||
2622 | static const struct clksel mcbsp_234_clksel[] = { | |
2623 | { .parent = &per_96m_fck, .rates = common_mcbsp_96m_rates }, | |
2624 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
2625 | { .parent = NULL } | |
2626 | }; | |
2627 | ||
2628 | static struct clk mcbsp2_fck = { | |
78673bc8 EV |
2629 | .name = "mcbsp_fck", |
2630 | .id = 2, | |
b045d080 PW |
2631 | .init = &omap2_init_clksel_parent, |
2632 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2633 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2634 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
2635 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
2636 | .clksel = mcbsp_234_clksel, | |
2637 | .flags = CLOCK_IN_OMAP343X, | |
2638 | .recalc = &omap2_clksel_recalc, | |
2639 | }; | |
2640 | ||
2641 | static struct clk mcbsp3_fck = { | |
78673bc8 EV |
2642 | .name = "mcbsp_fck", |
2643 | .id = 3, | |
b045d080 PW |
2644 | .init = &omap2_init_clksel_parent, |
2645 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2646 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2647 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2648 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | |
2649 | .clksel = mcbsp_234_clksel, | |
2650 | .flags = CLOCK_IN_OMAP343X, | |
2651 | .recalc = &omap2_clksel_recalc, | |
2652 | }; | |
2653 | ||
2654 | static struct clk mcbsp4_fck = { | |
78673bc8 EV |
2655 | .name = "mcbsp_fck", |
2656 | .id = 4, | |
b045d080 PW |
2657 | .init = &omap2_init_clksel_parent, |
2658 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2659 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2660 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2661 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | |
2662 | .clksel = mcbsp_234_clksel, | |
2663 | .flags = CLOCK_IN_OMAP343X, | |
2664 | .recalc = &omap2_clksel_recalc, | |
2665 | }; | |
2666 | ||
2667 | /* EMU clocks */ | |
2668 | ||
2669 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | |
2670 | ||
2671 | static const struct clksel_rate emu_src_sys_rates[] = { | |
2672 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2673 | { .div = 0 }, | |
2674 | }; | |
2675 | ||
2676 | static const struct clksel_rate emu_src_core_rates[] = { | |
2677 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2678 | { .div = 0 }, | |
2679 | }; | |
2680 | ||
2681 | static const struct clksel_rate emu_src_per_rates[] = { | |
2682 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2683 | { .div = 0 }, | |
2684 | }; | |
2685 | ||
2686 | static const struct clksel_rate emu_src_mpu_rates[] = { | |
2687 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2688 | { .div = 0 }, | |
2689 | }; | |
2690 | ||
2691 | static const struct clksel emu_src_clksel[] = { | |
2692 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | |
2693 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | |
2694 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | |
2695 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | |
2696 | { .parent = NULL }, | |
2697 | }; | |
2698 | ||
2699 | /* | |
2700 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | |
2701 | * to switch the source of some of the EMU clocks. | |
2702 | * XXX Are there CLKEN bits for these EMU clks? | |
2703 | */ | |
2704 | static struct clk emu_src_ck = { | |
2705 | .name = "emu_src_ck", | |
2706 | .init = &omap2_init_clksel_parent, | |
2707 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2708 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | |
2709 | .clksel = emu_src_clksel, | |
2710 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2711 | .recalc = &omap2_clksel_recalc, | |
2712 | }; | |
2713 | ||
2714 | static const struct clksel_rate pclk_emu_rates[] = { | |
2715 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2716 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2717 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2718 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
2719 | { .div = 0 }, | |
2720 | }; | |
2721 | ||
2722 | static const struct clksel pclk_emu_clksel[] = { | |
2723 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | |
2724 | { .parent = NULL }, | |
2725 | }; | |
2726 | ||
2727 | static struct clk pclk_fck = { | |
2728 | .name = "pclk_fck", | |
2729 | .init = &omap2_init_clksel_parent, | |
2730 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2731 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | |
2732 | .clksel = pclk_emu_clksel, | |
2733 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2734 | .recalc = &omap2_clksel_recalc, | |
2735 | }; | |
2736 | ||
2737 | static const struct clksel_rate pclkx2_emu_rates[] = { | |
2738 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2739 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2740 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2741 | { .div = 0 }, | |
2742 | }; | |
2743 | ||
2744 | static const struct clksel pclkx2_emu_clksel[] = { | |
2745 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | |
2746 | { .parent = NULL }, | |
2747 | }; | |
2748 | ||
2749 | static struct clk pclkx2_fck = { | |
2750 | .name = "pclkx2_fck", | |
2751 | .init = &omap2_init_clksel_parent, | |
2752 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2753 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | |
2754 | .clksel = pclkx2_emu_clksel, | |
2755 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2756 | .recalc = &omap2_clksel_recalc, | |
2757 | }; | |
2758 | ||
2759 | static const struct clksel atclk_emu_clksel[] = { | |
2760 | { .parent = &emu_src_ck, .rates = div2_rates }, | |
2761 | { .parent = NULL }, | |
2762 | }; | |
2763 | ||
2764 | static struct clk atclk_fck = { | |
2765 | .name = "atclk_fck", | |
2766 | .init = &omap2_init_clksel_parent, | |
2767 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2768 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | |
2769 | .clksel = atclk_emu_clksel, | |
2770 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2771 | .recalc = &omap2_clksel_recalc, | |
2772 | }; | |
2773 | ||
2774 | static struct clk traceclk_src_fck = { | |
2775 | .name = "traceclk_src_fck", | |
2776 | .init = &omap2_init_clksel_parent, | |
2777 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2778 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | |
2779 | .clksel = emu_src_clksel, | |
2780 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES | ALWAYS_ENABLED, | |
2781 | .recalc = &omap2_clksel_recalc, | |
2782 | }; | |
2783 | ||
2784 | static const struct clksel_rate traceclk_rates[] = { | |
2785 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2786 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2787 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2788 | { .div = 0 }, | |
2789 | }; | |
2790 | ||
2791 | static const struct clksel traceclk_clksel[] = { | |
2792 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | |
2793 | { .parent = NULL }, | |
2794 | }; | |
2795 | ||
2796 | static struct clk traceclk_fck = { | |
2797 | .name = "traceclk_fck", | |
2798 | .init = &omap2_init_clksel_parent, | |
2799 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2800 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | |
2801 | .clksel = traceclk_clksel, | |
2802 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
2803 | .recalc = &omap2_clksel_recalc, | |
2804 | }; | |
2805 | ||
2806 | /* SR clocks */ | |
2807 | ||
2808 | /* SmartReflex fclk (VDD1) */ | |
2809 | static struct clk sr1_fck = { | |
2810 | .name = "sr1_fck", | |
2811 | .parent = &sys_ck, | |
2812 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2813 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | |
2814 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
2815 | .recalc = &followparent_recalc, | |
2816 | }; | |
2817 | ||
2818 | /* SmartReflex fclk (VDD2) */ | |
2819 | static struct clk sr2_fck = { | |
2820 | .name = "sr2_fck", | |
2821 | .parent = &sys_ck, | |
2822 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2823 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | |
2824 | .flags = CLOCK_IN_OMAP343X | RATE_PROPAGATES, | |
2825 | .recalc = &followparent_recalc, | |
2826 | }; | |
2827 | ||
2828 | static struct clk sr_l4_ick = { | |
2829 | .name = "sr_l4_ick", | |
2830 | .parent = &l4_ick, | |
2831 | .flags = CLOCK_IN_OMAP343X, | |
2832 | .recalc = &followparent_recalc, | |
2833 | }; | |
2834 | ||
2835 | /* SECURE_32K_FCK clocks */ | |
2836 | ||
2837 | static struct clk gpt12_fck = { | |
2838 | .name = "gpt12_fck", | |
2839 | .parent = &secure_32k_fck, | |
2840 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
2841 | .recalc = &followparent_recalc, | |
2842 | }; | |
2843 | ||
2844 | static struct clk wdt1_fck = { | |
2845 | .name = "wdt1_fck", | |
2846 | .parent = &secure_32k_fck, | |
2847 | .flags = CLOCK_IN_OMAP343X | ALWAYS_ENABLED, | |
2848 | .recalc = &followparent_recalc, | |
2849 | }; | |
2850 | ||
b045d080 PW |
2851 | static struct clk *onchip_34xx_clks[] __initdata = { |
2852 | &omap_32k_fck, | |
2853 | &virt_12m_ck, | |
2854 | &virt_13m_ck, | |
2855 | &virt_16_8m_ck, | |
2856 | &virt_19_2m_ck, | |
2857 | &virt_26m_ck, | |
2858 | &virt_38_4m_ck, | |
2859 | &osc_sys_ck, | |
2860 | &sys_ck, | |
2861 | &sys_altclk, | |
2862 | &mcbsp_clks, | |
2863 | &sys_clkout1, | |
2864 | &dpll1_ck, | |
3760d31f RT |
2865 | &dpll1_x2_ck, |
2866 | &dpll1_x2m2_ck, | |
b045d080 | 2867 | &dpll2_ck, |
3760d31f | 2868 | &dpll2_m2_ck, |
b045d080 PW |
2869 | &dpll3_ck, |
2870 | &core_ck, | |
2871 | &dpll3_x2_ck, | |
2872 | &dpll3_m2_ck, | |
2873 | &dpll3_m2x2_ck, | |
3760d31f | 2874 | &dpll3_m3_ck, |
b045d080 PW |
2875 | &dpll3_m3x2_ck, |
2876 | &emu_core_alwon_ck, | |
2877 | &dpll4_ck, | |
2878 | &dpll4_x2_ck, | |
2879 | &omap_96m_alwon_fck, | |
2880 | &omap_96m_fck, | |
2881 | &cm_96m_fck, | |
3760d31f | 2882 | &virt_omap_54m_fck, |
b045d080 PW |
2883 | &omap_54m_fck, |
2884 | &omap_48m_fck, | |
2885 | &omap_12m_fck, | |
3760d31f | 2886 | &dpll4_m2_ck, |
b045d080 | 2887 | &dpll4_m2x2_ck, |
3760d31f | 2888 | &dpll4_m3_ck, |
b045d080 | 2889 | &dpll4_m3x2_ck, |
3760d31f | 2890 | &dpll4_m4_ck, |
b045d080 | 2891 | &dpll4_m4x2_ck, |
3760d31f | 2892 | &dpll4_m5_ck, |
b045d080 | 2893 | &dpll4_m5x2_ck, |
3760d31f | 2894 | &dpll4_m6_ck, |
b045d080 PW |
2895 | &dpll4_m6x2_ck, |
2896 | &emu_per_alwon_ck, | |
2897 | &dpll5_ck, | |
2898 | &dpll5_m2_ck, | |
2899 | &omap_120m_fck, | |
2900 | &clkout2_src_ck, | |
2901 | &sys_clkout2, | |
2902 | &corex2_fck, | |
2903 | &dpll1_fck, | |
3760d31f RT |
2904 | &mpu_ck, |
2905 | &arm_fck, | |
2906 | &emu_mpu_alwon_ck, | |
b045d080 | 2907 | &dpll2_fck, |
3760d31f | 2908 | &iva2_ck, |
b045d080 PW |
2909 | &l3_ick, |
2910 | &l4_ick, | |
2911 | &rm_ick, | |
2912 | &gfx_l3_fck, | |
2913 | &gfx_l3_ick, | |
2914 | &gfx_cg1_ck, | |
2915 | &gfx_cg2_ck, | |
2916 | &sgx_fck, | |
2917 | &sgx_ick, | |
2918 | &d2d_26m_fck, | |
2919 | &gpt10_fck, | |
2920 | &gpt11_fck, | |
2921 | &cpefuse_fck, | |
2922 | &ts_fck, | |
2923 | &usbtll_fck, | |
2924 | &core_96m_fck, | |
2925 | &mmchs3_fck, | |
2926 | &mmchs2_fck, | |
2927 | &mspro_fck, | |
2928 | &mmchs1_fck, | |
2929 | &i2c3_fck, | |
2930 | &i2c2_fck, | |
2931 | &i2c1_fck, | |
2932 | &mcbsp5_fck, | |
2933 | &mcbsp1_fck, | |
2934 | &core_48m_fck, | |
2935 | &mcspi4_fck, | |
2936 | &mcspi3_fck, | |
2937 | &mcspi2_fck, | |
2938 | &mcspi1_fck, | |
2939 | &uart2_fck, | |
2940 | &uart1_fck, | |
2941 | &fshostusb_fck, | |
2942 | &core_12m_fck, | |
2943 | &hdq_fck, | |
2944 | &ssi_ssr_fck, | |
2945 | &ssi_sst_fck, | |
2946 | &core_l3_ick, | |
2947 | &hsotgusb_ick, | |
2948 | &sdrc_ick, | |
2949 | &gpmc_fck, | |
2950 | &security_l3_ick, | |
2951 | &pka_ick, | |
2952 | &core_l4_ick, | |
2953 | &usbtll_ick, | |
2954 | &mmchs3_ick, | |
2955 | &icr_ick, | |
2956 | &aes2_ick, | |
2957 | &sha12_ick, | |
2958 | &des2_ick, | |
2959 | &mmchs2_ick, | |
2960 | &mmchs1_ick, | |
2961 | &mspro_ick, | |
2962 | &hdq_ick, | |
2963 | &mcspi4_ick, | |
2964 | &mcspi3_ick, | |
2965 | &mcspi2_ick, | |
2966 | &mcspi1_ick, | |
2967 | &i2c3_ick, | |
2968 | &i2c2_ick, | |
2969 | &i2c1_ick, | |
2970 | &uart2_ick, | |
2971 | &uart1_ick, | |
2972 | &gpt11_ick, | |
2973 | &gpt10_ick, | |
2974 | &mcbsp5_ick, | |
2975 | &mcbsp1_ick, | |
2976 | &fac_ick, | |
2977 | &mailboxes_ick, | |
2978 | &omapctrl_ick, | |
2979 | &ssi_l4_ick, | |
2980 | &ssi_ick, | |
2981 | &usb_l4_ick, | |
2982 | &security_l4_ick2, | |
2983 | &aes1_ick, | |
2984 | &rng_ick, | |
2985 | &sha11_ick, | |
2986 | &des1_ick, | |
2987 | &dss1_alwon_fck, | |
2988 | &dss_tv_fck, | |
2989 | &dss_96m_fck, | |
2990 | &dss2_alwon_fck, | |
2991 | &dss_ick, | |
2992 | &cam_mclk, | |
2993 | &cam_l3_ick, | |
2994 | &cam_l4_ick, | |
2995 | &usbhost_120m_fck, | |
2996 | &usbhost_48m_fck, | |
2997 | &usbhost_l3_ick, | |
2998 | &usbhost_l4_ick, | |
2999 | &usbhost_sar_fck, | |
3000 | &usim_fck, | |
3001 | &gpt1_fck, | |
3002 | &wkup_32k_fck, | |
3003 | &gpio1_fck, | |
3004 | &wdt2_fck, | |
3005 | &wkup_l4_ick, | |
3006 | &usim_ick, | |
3007 | &wdt2_ick, | |
3008 | &wdt1_ick, | |
3009 | &gpio1_ick, | |
3010 | &omap_32ksync_ick, | |
3011 | &gpt12_ick, | |
3012 | &gpt1_ick, | |
3013 | &per_96m_fck, | |
3014 | &per_48m_fck, | |
3015 | &uart3_fck, | |
3016 | &gpt2_fck, | |
3017 | &gpt3_fck, | |
3018 | &gpt4_fck, | |
3019 | &gpt5_fck, | |
3020 | &gpt6_fck, | |
3021 | &gpt7_fck, | |
3022 | &gpt8_fck, | |
3023 | &gpt9_fck, | |
3024 | &per_32k_alwon_fck, | |
3025 | &gpio6_fck, | |
3026 | &gpio5_fck, | |
3027 | &gpio4_fck, | |
3028 | &gpio3_fck, | |
3029 | &gpio2_fck, | |
3030 | &wdt3_fck, | |
3031 | &per_l4_ick, | |
3032 | &gpio6_ick, | |
3033 | &gpio5_ick, | |
3034 | &gpio4_ick, | |
3035 | &gpio3_ick, | |
3036 | &gpio2_ick, | |
3037 | &wdt3_ick, | |
3038 | &uart3_ick, | |
3039 | &gpt9_ick, | |
3040 | &gpt8_ick, | |
3041 | &gpt7_ick, | |
3042 | &gpt6_ick, | |
3043 | &gpt5_ick, | |
3044 | &gpt4_ick, | |
3045 | &gpt3_ick, | |
3046 | &gpt2_ick, | |
3047 | &mcbsp2_ick, | |
3048 | &mcbsp3_ick, | |
3049 | &mcbsp4_ick, | |
3050 | &mcbsp2_fck, | |
3051 | &mcbsp3_fck, | |
3052 | &mcbsp4_fck, | |
3053 | &emu_src_ck, | |
3054 | &pclk_fck, | |
3055 | &pclkx2_fck, | |
3056 | &atclk_fck, | |
3057 | &traceclk_src_fck, | |
3058 | &traceclk_fck, | |
3059 | &sr1_fck, | |
3060 | &sr2_fck, | |
3061 | &sr_l4_ick, | |
3062 | &secure_32k_fck, | |
3063 | &gpt12_fck, | |
3064 | &wdt1_fck, | |
3065 | }; | |
3066 | ||
3067 | #endif |