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b045d080 PW |
1 | /* |
2 | * OMAP3 clock framework | |
3 | * | |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. | |
5 | * Copyright (C) 2007-2008 Nokia Corporation | |
6 | * | |
7 | * Written by Paul Walmsley | |
542313cc PW |
8 | * With many device clock fixes by Kevin Hilman and Jouni Högander |
9 | * DPLL bypass clock support added by Roman Tereshonkov | |
10 | * | |
11 | */ | |
12 | ||
13 | /* | |
14 | * Virtual clocks are introduced as convenient tools. | |
15 | * They are sources for other clocks and not supposed | |
16 | * to be requested from drivers directly. | |
b045d080 PW |
17 | */ |
18 | ||
19 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
20 | #define __ARCH_ARM_MACH_OMAP2_CLOCK34XX_H | |
21 | ||
a09e64fb | 22 | #include <mach/control.h> |
b045d080 PW |
23 | |
24 | #include "clock.h" | |
25 | #include "cm.h" | |
26 | #include "cm-regbits-34xx.h" | |
27 | #include "prm.h" | |
28 | #include "prm-regbits-34xx.h" | |
29 | ||
ef6685a6 TL |
30 | #define OMAP_CM_REGADDR OMAP34XX_CM_REGADDR |
31 | ||
8b9dbc16 RK |
32 | static unsigned long omap3_dpll_recalc(struct clk *clk); |
33 | static unsigned long omap3_clkoutx2_recalc(struct clk *clk); | |
542313cc PW |
34 | static void omap3_dpll_allow_idle(struct clk *clk); |
35 | static void omap3_dpll_deny_idle(struct clk *clk); | |
36 | static u32 omap3_dpll_autoidle_read(struct clk *clk); | |
16c90f02 PW |
37 | static int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); |
38 | static int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate); | |
0eafd472 | 39 | static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate); |
b045d080 | 40 | |
88b8ba90 PW |
41 | /* Maximum DPLL multiplier, divider values for OMAP3 */ |
42 | #define OMAP3_MAX_DPLL_MULT 2048 | |
43 | #define OMAP3_MAX_DPLL_DIV 128 | |
44 | ||
b045d080 PW |
45 | /* |
46 | * DPLL1 supplies clock to the MPU. | |
47 | * DPLL2 supplies clock to the IVA2. | |
48 | * DPLL3 supplies CORE domain clocks. | |
49 | * DPLL4 supplies peripheral clocks. | |
50 | * DPLL5 supplies other peripheral clocks (USBHOST, USIM). | |
51 | */ | |
52 | ||
c0bf3132 RK |
53 | /* Forward declarations for DPLL bypass clocks */ |
54 | static struct clk dpll1_fck; | |
55 | static struct clk dpll2_fck; | |
56 | ||
542313cc PW |
57 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
58 | #define DPLL_LOW_POWER_STOP 0x1 | |
59 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
60 | #define DPLL_LOCKED 0x7 | |
61 | ||
b045d080 PW |
62 | /* PRM CLOCKS */ |
63 | ||
64 | /* According to timer32k.c, this is a 32768Hz clock, not a 32000Hz clock. */ | |
65 | static struct clk omap_32k_fck = { | |
66 | .name = "omap_32k_fck", | |
897dcded | 67 | .ops = &clkops_null, |
b045d080 | 68 | .rate = 32768, |
3f0a820c | 69 | .flags = RATE_FIXED, |
b045d080 PW |
70 | }; |
71 | ||
72 | static struct clk secure_32k_fck = { | |
73 | .name = "secure_32k_fck", | |
897dcded | 74 | .ops = &clkops_null, |
b045d080 | 75 | .rate = 32768, |
3f0a820c | 76 | .flags = RATE_FIXED, |
b045d080 PW |
77 | }; |
78 | ||
79 | /* Virtual source clocks for osc_sys_ck */ | |
80 | static struct clk virt_12m_ck = { | |
81 | .name = "virt_12m_ck", | |
897dcded | 82 | .ops = &clkops_null, |
b045d080 | 83 | .rate = 12000000, |
3f0a820c | 84 | .flags = RATE_FIXED, |
b045d080 PW |
85 | }; |
86 | ||
87 | static struct clk virt_13m_ck = { | |
88 | .name = "virt_13m_ck", | |
897dcded | 89 | .ops = &clkops_null, |
b045d080 | 90 | .rate = 13000000, |
3f0a820c | 91 | .flags = RATE_FIXED, |
b045d080 PW |
92 | }; |
93 | ||
94 | static struct clk virt_16_8m_ck = { | |
95 | .name = "virt_16_8m_ck", | |
897dcded | 96 | .ops = &clkops_null, |
b045d080 | 97 | .rate = 16800000, |
3f0a820c | 98 | .flags = RATE_FIXED, |
b045d080 PW |
99 | }; |
100 | ||
101 | static struct clk virt_19_2m_ck = { | |
102 | .name = "virt_19_2m_ck", | |
897dcded | 103 | .ops = &clkops_null, |
b045d080 | 104 | .rate = 19200000, |
3f0a820c | 105 | .flags = RATE_FIXED, |
b045d080 PW |
106 | }; |
107 | ||
108 | static struct clk virt_26m_ck = { | |
109 | .name = "virt_26m_ck", | |
897dcded | 110 | .ops = &clkops_null, |
b045d080 | 111 | .rate = 26000000, |
3f0a820c | 112 | .flags = RATE_FIXED, |
b045d080 PW |
113 | }; |
114 | ||
115 | static struct clk virt_38_4m_ck = { | |
116 | .name = "virt_38_4m_ck", | |
897dcded | 117 | .ops = &clkops_null, |
b045d080 | 118 | .rate = 38400000, |
3f0a820c | 119 | .flags = RATE_FIXED, |
b045d080 PW |
120 | }; |
121 | ||
122 | static const struct clksel_rate osc_sys_12m_rates[] = { | |
123 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
124 | { .div = 0 } | |
125 | }; | |
126 | ||
127 | static const struct clksel_rate osc_sys_13m_rates[] = { | |
128 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
129 | { .div = 0 } | |
130 | }; | |
131 | ||
132 | static const struct clksel_rate osc_sys_16_8m_rates[] = { | |
133 | { .div = 1, .val = 5, .flags = RATE_IN_3430ES2 | DEFAULT_RATE }, | |
134 | { .div = 0 } | |
135 | }; | |
136 | ||
137 | static const struct clksel_rate osc_sys_19_2m_rates[] = { | |
138 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
139 | { .div = 0 } | |
140 | }; | |
141 | ||
142 | static const struct clksel_rate osc_sys_26m_rates[] = { | |
143 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
144 | { .div = 0 } | |
145 | }; | |
146 | ||
147 | static const struct clksel_rate osc_sys_38_4m_rates[] = { | |
148 | { .div = 1, .val = 4, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
149 | { .div = 0 } | |
150 | }; | |
151 | ||
152 | static const struct clksel osc_sys_clksel[] = { | |
153 | { .parent = &virt_12m_ck, .rates = osc_sys_12m_rates }, | |
154 | { .parent = &virt_13m_ck, .rates = osc_sys_13m_rates }, | |
155 | { .parent = &virt_16_8m_ck, .rates = osc_sys_16_8m_rates }, | |
156 | { .parent = &virt_19_2m_ck, .rates = osc_sys_19_2m_rates }, | |
157 | { .parent = &virt_26m_ck, .rates = osc_sys_26m_rates }, | |
158 | { .parent = &virt_38_4m_ck, .rates = osc_sys_38_4m_rates }, | |
159 | { .parent = NULL }, | |
160 | }; | |
161 | ||
162 | /* Oscillator clock */ | |
163 | /* 12, 13, 16.8, 19.2, 26, or 38.4 MHz */ | |
164 | static struct clk osc_sys_ck = { | |
165 | .name = "osc_sys_ck", | |
897dcded | 166 | .ops = &clkops_null, |
b045d080 PW |
167 | .init = &omap2_init_clksel_parent, |
168 | .clksel_reg = OMAP3430_PRM_CLKSEL, | |
169 | .clksel_mask = OMAP3430_SYS_CLKIN_SEL_MASK, | |
170 | .clksel = osc_sys_clksel, | |
171 | /* REVISIT: deal with autoextclkmode? */ | |
3f0a820c | 172 | .flags = RATE_FIXED, |
b045d080 PW |
173 | .recalc = &omap2_clksel_recalc, |
174 | }; | |
175 | ||
176 | static const struct clksel_rate div2_rates[] = { | |
177 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
178 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
179 | { .div = 0 } | |
180 | }; | |
181 | ||
182 | static const struct clksel sys_clksel[] = { | |
183 | { .parent = &osc_sys_ck, .rates = div2_rates }, | |
184 | { .parent = NULL } | |
185 | }; | |
186 | ||
187 | /* Latency: this clock is only enabled after PRM_CLKSETUP.SETUP_TIME */ | |
188 | /* Feeds DPLLs - divided first by PRM_CLKSRC_CTRL.SYSCLKDIV? */ | |
189 | static struct clk sys_ck = { | |
190 | .name = "sys_ck", | |
897dcded | 191 | .ops = &clkops_null, |
b045d080 PW |
192 | .parent = &osc_sys_ck, |
193 | .init = &omap2_init_clksel_parent, | |
194 | .clksel_reg = OMAP3430_PRM_CLKSRC_CTRL, | |
195 | .clksel_mask = OMAP_SYSCLKDIV_MASK, | |
196 | .clksel = sys_clksel, | |
b045d080 PW |
197 | .recalc = &omap2_clksel_recalc, |
198 | }; | |
199 | ||
200 | static struct clk sys_altclk = { | |
201 | .name = "sys_altclk", | |
897dcded | 202 | .ops = &clkops_null, |
b045d080 PW |
203 | }; |
204 | ||
205 | /* Optional external clock input for some McBSPs */ | |
206 | static struct clk mcbsp_clks = { | |
207 | .name = "mcbsp_clks", | |
897dcded | 208 | .ops = &clkops_null, |
b045d080 PW |
209 | }; |
210 | ||
211 | /* PRM EXTERNAL CLOCK OUTPUT */ | |
212 | ||
213 | static struct clk sys_clkout1 = { | |
214 | .name = "sys_clkout1", | |
c1168dc3 | 215 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
216 | .parent = &osc_sys_ck, |
217 | .enable_reg = OMAP3430_PRM_CLKOUT_CTRL, | |
218 | .enable_bit = OMAP3430_CLKOUT_EN_SHIFT, | |
b045d080 PW |
219 | .recalc = &followparent_recalc, |
220 | }; | |
221 | ||
222 | /* DPLLS */ | |
223 | ||
224 | /* CM CLOCKS */ | |
225 | ||
3760d31f RT |
226 | static const struct clksel_rate div16_dpll_rates[] = { |
227 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
228 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
229 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
230 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
231 | { .div = 5, .val = 5, .flags = RATE_IN_343X }, | |
232 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
233 | { .div = 7, .val = 7, .flags = RATE_IN_343X }, | |
234 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
235 | { .div = 9, .val = 9, .flags = RATE_IN_343X }, | |
236 | { .div = 10, .val = 10, .flags = RATE_IN_343X }, | |
237 | { .div = 11, .val = 11, .flags = RATE_IN_343X }, | |
238 | { .div = 12, .val = 12, .flags = RATE_IN_343X }, | |
239 | { .div = 13, .val = 13, .flags = RATE_IN_343X }, | |
240 | { .div = 14, .val = 14, .flags = RATE_IN_343X }, | |
241 | { .div = 15, .val = 15, .flags = RATE_IN_343X }, | |
242 | { .div = 16, .val = 16, .flags = RATE_IN_343X }, | |
243 | { .div = 0 } | |
244 | }; | |
245 | ||
b045d080 PW |
246 | /* DPLL1 */ |
247 | /* MPU clock source */ | |
248 | /* Type: DPLL */ | |
88b8ba90 | 249 | static struct dpll_data dpll1_dd = { |
b045d080 PW |
250 | .mult_div1_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), |
251 | .mult_mask = OMAP3430_MPU_DPLL_MULT_MASK, | |
252 | .div1_mask = OMAP3430_MPU_DPLL_DIV_MASK, | |
c0bf3132 RK |
253 | .clk_bypass = &dpll1_fck, |
254 | .clk_ref = &sys_ck, | |
16c90f02 | 255 | .freqsel_mask = OMAP3430_MPU_DPLL_FREQSEL_MASK, |
b045d080 PW |
256 | .control_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKEN_PLL), |
257 | .enable_mask = OMAP3430_EN_MPU_DPLL_MASK, | |
542313cc | 258 | .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED), |
b045d080 PW |
259 | .auto_recal_bit = OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT, |
260 | .recal_en_bit = OMAP3430_MPU_DPLL_RECAL_EN_SHIFT, | |
261 | .recal_st_bit = OMAP3430_MPU_DPLL_ST_SHIFT, | |
542313cc PW |
262 | .autoidle_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
263 | .autoidle_mask = OMAP3430_AUTO_MPU_DPLL_MASK, | |
264 | .idlest_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
c1bd7aaf | 265 | .idlest_mask = OMAP3430_ST_MPU_CLK_MASK, |
88b8ba90 | 266 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
95f538ac | 267 | .min_divider = 1, |
88b8ba90 PW |
268 | .max_divider = OMAP3_MAX_DPLL_DIV, |
269 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
270 | }; |
271 | ||
272 | static struct clk dpll1_ck = { | |
273 | .name = "dpll1_ck", | |
897dcded | 274 | .ops = &clkops_null, |
b045d080 PW |
275 | .parent = &sys_ck, |
276 | .dpll_data = &dpll1_dd, | |
88b8ba90 | 277 | .round_rate = &omap2_dpll_round_rate, |
16c90f02 | 278 | .set_rate = &omap3_noncore_dpll_set_rate, |
46e0ccf8 | 279 | .clkdm_name = "dpll1_clkdm", |
b045d080 PW |
280 | .recalc = &omap3_dpll_recalc, |
281 | }; | |
282 | ||
283 | /* | |
3760d31f RT |
284 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the |
285 | * DPLL isn't bypassed. | |
b045d080 | 286 | */ |
3760d31f RT |
287 | static struct clk dpll1_x2_ck = { |
288 | .name = "dpll1_x2_ck", | |
57137181 | 289 | .ops = &clkops_null, |
b045d080 | 290 | .parent = &dpll1_ck, |
46e0ccf8 | 291 | .clkdm_name = "dpll1_clkdm", |
3760d31f RT |
292 | .recalc = &omap3_clkoutx2_recalc, |
293 | }; | |
294 | ||
295 | /* On DPLL1, unlike other DPLLs, the divider is downstream from CLKOUTX2 */ | |
296 | static const struct clksel div16_dpll1_x2m2_clksel[] = { | |
297 | { .parent = &dpll1_x2_ck, .rates = div16_dpll_rates }, | |
298 | { .parent = NULL } | |
299 | }; | |
300 | ||
301 | /* | |
302 | * Does not exist in the TRM - needed to separate the M2 divider from | |
303 | * bypass selection in mpu_ck | |
304 | */ | |
305 | static struct clk dpll1_x2m2_ck = { | |
306 | .name = "dpll1_x2m2_ck", | |
57137181 | 307 | .ops = &clkops_null, |
3760d31f RT |
308 | .parent = &dpll1_x2_ck, |
309 | .init = &omap2_init_clksel_parent, | |
310 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL), | |
311 | .clksel_mask = OMAP3430_MPU_DPLL_CLKOUT_DIV_MASK, | |
312 | .clksel = div16_dpll1_x2m2_clksel, | |
46e0ccf8 | 313 | .clkdm_name = "dpll1_clkdm", |
3760d31f | 314 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
315 | }; |
316 | ||
317 | /* DPLL2 */ | |
318 | /* IVA2 clock source */ | |
319 | /* Type: DPLL */ | |
320 | ||
88b8ba90 | 321 | static struct dpll_data dpll2_dd = { |
b045d080 PW |
322 | .mult_div1_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), |
323 | .mult_mask = OMAP3430_IVA2_DPLL_MULT_MASK, | |
324 | .div1_mask = OMAP3430_IVA2_DPLL_DIV_MASK, | |
c0bf3132 RK |
325 | .clk_bypass = &dpll2_fck, |
326 | .clk_ref = &sys_ck, | |
16c90f02 | 327 | .freqsel_mask = OMAP3430_IVA2_DPLL_FREQSEL_MASK, |
b045d080 PW |
328 | .control_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL), |
329 | .enable_mask = OMAP3430_EN_IVA2_DPLL_MASK, | |
542313cc PW |
330 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED) | |
331 | (1 << DPLL_LOW_POWER_BYPASS), | |
b045d080 PW |
332 | .auto_recal_bit = OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT, |
333 | .recal_en_bit = OMAP3430_PRM_IRQENABLE_MPU_IVA2_DPLL_RECAL_EN_SHIFT, | |
334 | .recal_st_bit = OMAP3430_PRM_IRQSTATUS_MPU_IVA2_DPLL_ST_SHIFT, | |
542313cc PW |
335 | .autoidle_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL), |
336 | .autoidle_mask = OMAP3430_AUTO_IVA2_DPLL_MASK, | |
337 | .idlest_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_IDLEST_PLL), | |
c1bd7aaf | 338 | .idlest_mask = OMAP3430_ST_IVA2_CLK_MASK, |
88b8ba90 | 339 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
95f538ac | 340 | .min_divider = 1, |
88b8ba90 PW |
341 | .max_divider = OMAP3_MAX_DPLL_DIV, |
342 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
343 | }; |
344 | ||
345 | static struct clk dpll2_ck = { | |
346 | .name = "dpll2_ck", | |
548d8495 | 347 | .ops = &clkops_noncore_dpll_ops, |
b045d080 PW |
348 | .parent = &sys_ck, |
349 | .dpll_data = &dpll2_dd, | |
88b8ba90 | 350 | .round_rate = &omap2_dpll_round_rate, |
16c90f02 | 351 | .set_rate = &omap3_noncore_dpll_set_rate, |
46e0ccf8 | 352 | .clkdm_name = "dpll2_clkdm", |
b045d080 PW |
353 | .recalc = &omap3_dpll_recalc, |
354 | }; | |
355 | ||
3760d31f RT |
356 | static const struct clksel div16_dpll2_m2x2_clksel[] = { |
357 | { .parent = &dpll2_ck, .rates = div16_dpll_rates }, | |
358 | { .parent = NULL } | |
359 | }; | |
360 | ||
361 | /* | |
362 | * The TRM is conflicted on whether IVA2 clock comes from DPLL2 CLKOUT | |
363 | * or CLKOUTX2. CLKOUT seems most plausible. | |
364 | */ | |
365 | static struct clk dpll2_m2_ck = { | |
366 | .name = "dpll2_m2_ck", | |
57137181 | 367 | .ops = &clkops_null, |
3760d31f RT |
368 | .parent = &dpll2_ck, |
369 | .init = &omap2_init_clksel_parent, | |
370 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, | |
371 | OMAP3430_CM_CLKSEL2_PLL), | |
372 | .clksel_mask = OMAP3430_IVA2_DPLL_CLKOUT_DIV_MASK, | |
373 | .clksel = div16_dpll2_m2x2_clksel, | |
46e0ccf8 | 374 | .clkdm_name = "dpll2_clkdm", |
3760d31f RT |
375 | .recalc = &omap2_clksel_recalc, |
376 | }; | |
377 | ||
542313cc PW |
378 | /* |
379 | * DPLL3 | |
380 | * Source clock for all interfaces and for some device fclks | |
381 | * REVISIT: Also supports fast relock bypass - not included below | |
382 | */ | |
88b8ba90 | 383 | static struct dpll_data dpll3_dd = { |
b045d080 PW |
384 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
385 | .mult_mask = OMAP3430_CORE_DPLL_MULT_MASK, | |
386 | .div1_mask = OMAP3430_CORE_DPLL_DIV_MASK, | |
c0bf3132 RK |
387 | .clk_bypass = &sys_ck, |
388 | .clk_ref = &sys_ck, | |
16c90f02 | 389 | .freqsel_mask = OMAP3430_CORE_DPLL_FREQSEL_MASK, |
b045d080 PW |
390 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
391 | .enable_mask = OMAP3430_EN_CORE_DPLL_MASK, | |
392 | .auto_recal_bit = OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT, | |
393 | .recal_en_bit = OMAP3430_CORE_DPLL_RECAL_EN_SHIFT, | |
394 | .recal_st_bit = OMAP3430_CORE_DPLL_ST_SHIFT, | |
542313cc PW |
395 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
396 | .autoidle_mask = OMAP3430_AUTO_CORE_DPLL_MASK, | |
c1bd7aaf PW |
397 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), |
398 | .idlest_mask = OMAP3430_ST_CORE_CLK_MASK, | |
88b8ba90 | 399 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
95f538ac | 400 | .min_divider = 1, |
88b8ba90 PW |
401 | .max_divider = OMAP3_MAX_DPLL_DIV, |
402 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
403 | }; |
404 | ||
405 | static struct clk dpll3_ck = { | |
406 | .name = "dpll3_ck", | |
897dcded | 407 | .ops = &clkops_null, |
b045d080 PW |
408 | .parent = &sys_ck, |
409 | .dpll_data = &dpll3_dd, | |
88b8ba90 | 410 | .round_rate = &omap2_dpll_round_rate, |
46e0ccf8 | 411 | .clkdm_name = "dpll3_clkdm", |
b045d080 PW |
412 | .recalc = &omap3_dpll_recalc, |
413 | }; | |
414 | ||
3760d31f RT |
415 | /* |
416 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
417 | * DPLL isn't bypassed | |
418 | */ | |
419 | static struct clk dpll3_x2_ck = { | |
420 | .name = "dpll3_x2_ck", | |
57137181 | 421 | .ops = &clkops_null, |
3760d31f | 422 | .parent = &dpll3_ck, |
46e0ccf8 | 423 | .clkdm_name = "dpll3_clkdm", |
3760d31f | 424 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
425 | }; |
426 | ||
427 | static const struct clksel_rate div31_dpll3_rates[] = { | |
428 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
429 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
430 | { .div = 3, .val = 3, .flags = RATE_IN_3430ES2 }, | |
431 | { .div = 4, .val = 4, .flags = RATE_IN_3430ES2 }, | |
432 | { .div = 5, .val = 5, .flags = RATE_IN_3430ES2 }, | |
433 | { .div = 6, .val = 6, .flags = RATE_IN_3430ES2 }, | |
434 | { .div = 7, .val = 7, .flags = RATE_IN_3430ES2 }, | |
435 | { .div = 8, .val = 8, .flags = RATE_IN_3430ES2 }, | |
436 | { .div = 9, .val = 9, .flags = RATE_IN_3430ES2 }, | |
437 | { .div = 10, .val = 10, .flags = RATE_IN_3430ES2 }, | |
438 | { .div = 11, .val = 11, .flags = RATE_IN_3430ES2 }, | |
439 | { .div = 12, .val = 12, .flags = RATE_IN_3430ES2 }, | |
440 | { .div = 13, .val = 13, .flags = RATE_IN_3430ES2 }, | |
441 | { .div = 14, .val = 14, .flags = RATE_IN_3430ES2 }, | |
442 | { .div = 15, .val = 15, .flags = RATE_IN_3430ES2 }, | |
443 | { .div = 16, .val = 16, .flags = RATE_IN_3430ES2 }, | |
444 | { .div = 17, .val = 17, .flags = RATE_IN_3430ES2 }, | |
445 | { .div = 18, .val = 18, .flags = RATE_IN_3430ES2 }, | |
446 | { .div = 19, .val = 19, .flags = RATE_IN_3430ES2 }, | |
447 | { .div = 20, .val = 20, .flags = RATE_IN_3430ES2 }, | |
448 | { .div = 21, .val = 21, .flags = RATE_IN_3430ES2 }, | |
449 | { .div = 22, .val = 22, .flags = RATE_IN_3430ES2 }, | |
450 | { .div = 23, .val = 23, .flags = RATE_IN_3430ES2 }, | |
451 | { .div = 24, .val = 24, .flags = RATE_IN_3430ES2 }, | |
452 | { .div = 25, .val = 25, .flags = RATE_IN_3430ES2 }, | |
453 | { .div = 26, .val = 26, .flags = RATE_IN_3430ES2 }, | |
454 | { .div = 27, .val = 27, .flags = RATE_IN_3430ES2 }, | |
455 | { .div = 28, .val = 28, .flags = RATE_IN_3430ES2 }, | |
456 | { .div = 29, .val = 29, .flags = RATE_IN_3430ES2 }, | |
457 | { .div = 30, .val = 30, .flags = RATE_IN_3430ES2 }, | |
458 | { .div = 31, .val = 31, .flags = RATE_IN_3430ES2 }, | |
459 | { .div = 0 }, | |
460 | }; | |
461 | ||
462 | static const struct clksel div31_dpll3m2_clksel[] = { | |
463 | { .parent = &dpll3_ck, .rates = div31_dpll3_rates }, | |
464 | { .parent = NULL } | |
465 | }; | |
466 | ||
0eafd472 | 467 | /* DPLL3 output M2 - primary control point for CORE speed */ |
b045d080 PW |
468 | static struct clk dpll3_m2_ck = { |
469 | .name = "dpll3_m2_ck", | |
57137181 | 470 | .ops = &clkops_null, |
b045d080 PW |
471 | .parent = &dpll3_ck, |
472 | .init = &omap2_init_clksel_parent, | |
473 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
474 | .clksel_mask = OMAP3430_CORE_DPLL_CLKOUT_DIV_MASK, | |
475 | .clksel = div31_dpll3m2_clksel, | |
46e0ccf8 | 476 | .clkdm_name = "dpll3_clkdm", |
0eafd472 PW |
477 | .round_rate = &omap2_clksel_round_rate, |
478 | .set_rate = &omap3_core_dpll_m2_set_rate, | |
b045d080 PW |
479 | .recalc = &omap2_clksel_recalc, |
480 | }; | |
481 | ||
482 | static struct clk core_ck = { | |
483 | .name = "core_ck", | |
57137181 | 484 | .ops = &clkops_null, |
c0bf3132 RK |
485 | .parent = &dpll3_m2_ck, |
486 | .recalc = &followparent_recalc, | |
b045d080 PW |
487 | }; |
488 | ||
489 | static struct clk dpll3_m2x2_ck = { | |
490 | .name = "dpll3_m2x2_ck", | |
57137181 | 491 | .ops = &clkops_null, |
c0bf3132 | 492 | .parent = &dpll3_x2_ck, |
46e0ccf8 | 493 | .clkdm_name = "dpll3_clkdm", |
c0bf3132 | 494 | .recalc = &followparent_recalc, |
3760d31f RT |
495 | }; |
496 | ||
497 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
498 | static const struct clksel div16_dpll3_clksel[] = { | |
499 | { .parent = &dpll3_ck, .rates = div16_dpll_rates }, | |
500 | { .parent = NULL } | |
501 | }; | |
502 | ||
503 | /* This virtual clock is the source for dpll3_m3x2_ck */ | |
504 | static struct clk dpll3_m3_ck = { | |
505 | .name = "dpll3_m3_ck", | |
57137181 | 506 | .ops = &clkops_null, |
3760d31f RT |
507 | .parent = &dpll3_ck, |
508 | .init = &omap2_init_clksel_parent, | |
509 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
510 | .clksel_mask = OMAP3430_DIV_DPLL3_MASK, | |
511 | .clksel = div16_dpll3_clksel, | |
46e0ccf8 | 512 | .clkdm_name = "dpll3_clkdm", |
3760d31f | 513 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
514 | }; |
515 | ||
516 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
517 | static struct clk dpll3_m3x2_ck = { | |
518 | .name = "dpll3_m3x2_ck", | |
b36ee724 | 519 | .ops = &clkops_omap2_dflt_wait, |
3760d31f | 520 | .parent = &dpll3_m3_ck, |
b045d080 PW |
521 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
522 | .enable_bit = OMAP3430_PWRDN_EMU_CORE_SHIFT, | |
3f0a820c | 523 | .flags = INVERT_ENABLE, |
46e0ccf8 | 524 | .clkdm_name = "dpll3_clkdm", |
3760d31f | 525 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
526 | }; |
527 | ||
b045d080 PW |
528 | static struct clk emu_core_alwon_ck = { |
529 | .name = "emu_core_alwon_ck", | |
57137181 | 530 | .ops = &clkops_null, |
3760d31f | 531 | .parent = &dpll3_m3x2_ck, |
46e0ccf8 | 532 | .clkdm_name = "dpll3_clkdm", |
c0bf3132 | 533 | .recalc = &followparent_recalc, |
b045d080 PW |
534 | }; |
535 | ||
536 | /* DPLL4 */ | |
537 | /* Supplies 96MHz, 54Mhz TV DAC, DSS fclk, CAM sensor clock, emul trace clk */ | |
538 | /* Type: DPLL */ | |
88b8ba90 | 539 | static struct dpll_data dpll4_dd = { |
b045d080 PW |
540 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL2), |
541 | .mult_mask = OMAP3430_PERIPH_DPLL_MULT_MASK, | |
542 | .div1_mask = OMAP3430_PERIPH_DPLL_DIV_MASK, | |
c0bf3132 RK |
543 | .clk_bypass = &sys_ck, |
544 | .clk_ref = &sys_ck, | |
16c90f02 | 545 | .freqsel_mask = OMAP3430_PERIPH_DPLL_FREQSEL_MASK, |
b045d080 PW |
546 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
547 | .enable_mask = OMAP3430_EN_PERIPH_DPLL_MASK, | |
542313cc | 548 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
b045d080 PW |
549 | .auto_recal_bit = OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT, |
550 | .recal_en_bit = OMAP3430_PERIPH_DPLL_RECAL_EN_SHIFT, | |
551 | .recal_st_bit = OMAP3430_PERIPH_DPLL_ST_SHIFT, | |
542313cc PW |
552 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, CM_AUTOIDLE), |
553 | .autoidle_mask = OMAP3430_AUTO_PERIPH_DPLL_MASK, | |
554 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), | |
c1bd7aaf | 555 | .idlest_mask = OMAP3430_ST_PERIPH_CLK_MASK, |
88b8ba90 | 556 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
95f538ac | 557 | .min_divider = 1, |
88b8ba90 PW |
558 | .max_divider = OMAP3_MAX_DPLL_DIV, |
559 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
560 | }; |
561 | ||
562 | static struct clk dpll4_ck = { | |
563 | .name = "dpll4_ck", | |
548d8495 | 564 | .ops = &clkops_noncore_dpll_ops, |
b045d080 PW |
565 | .parent = &sys_ck, |
566 | .dpll_data = &dpll4_dd, | |
88b8ba90 | 567 | .round_rate = &omap2_dpll_round_rate, |
16c90f02 | 568 | .set_rate = &omap3_dpll4_set_rate, |
46e0ccf8 | 569 | .clkdm_name = "dpll4_clkdm", |
b045d080 PW |
570 | .recalc = &omap3_dpll_recalc, |
571 | }; | |
572 | ||
573 | /* | |
574 | * This virtual clock provides the CLKOUTX2 output from the DPLL if the | |
3760d31f RT |
575 | * DPLL isn't bypassed -- |
576 | * XXX does this serve any downstream clocks? | |
b045d080 PW |
577 | */ |
578 | static struct clk dpll4_x2_ck = { | |
579 | .name = "dpll4_x2_ck", | |
57137181 | 580 | .ops = &clkops_null, |
b045d080 | 581 | .parent = &dpll4_ck, |
46e0ccf8 | 582 | .clkdm_name = "dpll4_clkdm", |
b045d080 PW |
583 | .recalc = &omap3_clkoutx2_recalc, |
584 | }; | |
585 | ||
586 | static const struct clksel div16_dpll4_clksel[] = { | |
3760d31f | 587 | { .parent = &dpll4_ck, .rates = div16_dpll_rates }, |
b045d080 PW |
588 | { .parent = NULL } |
589 | }; | |
590 | ||
3760d31f RT |
591 | /* This virtual clock is the source for dpll4_m2x2_ck */ |
592 | static struct clk dpll4_m2_ck = { | |
593 | .name = "dpll4_m2_ck", | |
57137181 | 594 | .ops = &clkops_null, |
3760d31f RT |
595 | .parent = &dpll4_ck, |
596 | .init = &omap2_init_clksel_parent, | |
597 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430_CM_CLKSEL3), | |
598 | .clksel_mask = OMAP3430_DIV_96M_MASK, | |
599 | .clksel = div16_dpll4_clksel, | |
46e0ccf8 | 600 | .clkdm_name = "dpll4_clkdm", |
3760d31f RT |
601 | .recalc = &omap2_clksel_recalc, |
602 | }; | |
603 | ||
b045d080 PW |
604 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
605 | static struct clk dpll4_m2x2_ck = { | |
606 | .name = "dpll4_m2x2_ck", | |
b36ee724 | 607 | .ops = &clkops_omap2_dflt_wait, |
3760d31f | 608 | .parent = &dpll4_m2_ck, |
b045d080 PW |
609 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
610 | .enable_bit = OMAP3430_PWRDN_96M_SHIFT, | |
3f0a820c | 611 | .flags = INVERT_ENABLE, |
46e0ccf8 | 612 | .clkdm_name = "dpll4_clkdm", |
3760d31f RT |
613 | .recalc = &omap3_clkoutx2_recalc, |
614 | }; | |
615 | ||
9cfd985e PW |
616 | /* |
617 | * DPLL4 generates DPLL4_M2X2_CLK which is then routed into the PRM as | |
618 | * PRM_96M_ALWON_(F)CLK. Two clocks then emerge from the PRM: | |
619 | * 96M_ALWON_FCLK (called "omap_96m_alwon_fck" below) and | |
620 | * CM_96K_(F)CLK. | |
621 | */ | |
b045d080 PW |
622 | static struct clk omap_96m_alwon_fck = { |
623 | .name = "omap_96m_alwon_fck", | |
57137181 | 624 | .ops = &clkops_null, |
b045d080 | 625 | .parent = &dpll4_m2x2_ck, |
c0bf3132 | 626 | .recalc = &followparent_recalc, |
b045d080 PW |
627 | }; |
628 | ||
9cfd985e PW |
629 | static struct clk cm_96m_fck = { |
630 | .name = "cm_96m_fck", | |
57137181 | 631 | .ops = &clkops_null, |
b045d080 | 632 | .parent = &omap_96m_alwon_fck, |
b045d080 PW |
633 | .recalc = &followparent_recalc, |
634 | }; | |
635 | ||
9cfd985e PW |
636 | static const struct clksel_rate omap_96m_dpll_rates[] = { |
637 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
638 | { .div = 0 } | |
639 | }; | |
640 | ||
641 | static const struct clksel_rate omap_96m_sys_rates[] = { | |
642 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
643 | { .div = 0 } | |
644 | }; | |
645 | ||
646 | static const struct clksel omap_96m_fck_clksel[] = { | |
647 | { .parent = &cm_96m_fck, .rates = omap_96m_dpll_rates }, | |
648 | { .parent = &sys_ck, .rates = omap_96m_sys_rates }, | |
3760d31f RT |
649 | { .parent = NULL } |
650 | }; | |
651 | ||
9cfd985e PW |
652 | static struct clk omap_96m_fck = { |
653 | .name = "omap_96m_fck", | |
57137181 | 654 | .ops = &clkops_null, |
9cfd985e | 655 | .parent = &sys_ck, |
3760d31f | 656 | .init = &omap2_init_clksel_parent, |
9cfd985e PW |
657 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), |
658 | .clksel_mask = OMAP3430_SOURCE_96M_MASK, | |
659 | .clksel = omap_96m_fck_clksel, | |
3760d31f RT |
660 | .recalc = &omap2_clksel_recalc, |
661 | }; | |
662 | ||
663 | /* This virtual clock is the source for dpll4_m3x2_ck */ | |
664 | static struct clk dpll4_m3_ck = { | |
665 | .name = "dpll4_m3_ck", | |
57137181 | 666 | .ops = &clkops_null, |
3760d31f RT |
667 | .parent = &dpll4_ck, |
668 | .init = &omap2_init_clksel_parent, | |
669 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
670 | .clksel_mask = OMAP3430_CLKSEL_TV_MASK, | |
671 | .clksel = div16_dpll4_clksel, | |
46e0ccf8 | 672 | .clkdm_name = "dpll4_clkdm", |
3760d31f | 673 | .recalc = &omap2_clksel_recalc, |
b045d080 PW |
674 | }; |
675 | ||
676 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
677 | static struct clk dpll4_m3x2_ck = { | |
678 | .name = "dpll4_m3x2_ck", | |
b36ee724 | 679 | .ops = &clkops_omap2_dflt_wait, |
3760d31f | 680 | .parent = &dpll4_m3_ck, |
b045d080 PW |
681 | .init = &omap2_init_clksel_parent, |
682 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
683 | .enable_bit = OMAP3430_PWRDN_TV_SHIFT, | |
3f0a820c | 684 | .flags = INVERT_ENABLE, |
46e0ccf8 | 685 | .clkdm_name = "dpll4_clkdm", |
3760d31f RT |
686 | .recalc = &omap3_clkoutx2_recalc, |
687 | }; | |
688 | ||
b045d080 PW |
689 | static const struct clksel_rate omap_54m_d4m3x2_rates[] = { |
690 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
691 | { .div = 0 } | |
692 | }; | |
693 | ||
694 | static const struct clksel_rate omap_54m_alt_rates[] = { | |
695 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
696 | { .div = 0 } | |
697 | }; | |
698 | ||
699 | static const struct clksel omap_54m_clksel[] = { | |
c0bf3132 | 700 | { .parent = &dpll4_m3x2_ck, .rates = omap_54m_d4m3x2_rates }, |
b045d080 PW |
701 | { .parent = &sys_altclk, .rates = omap_54m_alt_rates }, |
702 | { .parent = NULL } | |
703 | }; | |
704 | ||
705 | static struct clk omap_54m_fck = { | |
706 | .name = "omap_54m_fck", | |
57137181 | 707 | .ops = &clkops_null, |
b045d080 PW |
708 | .init = &omap2_init_clksel_parent, |
709 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
9cfd985e | 710 | .clksel_mask = OMAP3430_SOURCE_54M_MASK, |
b045d080 | 711 | .clksel = omap_54m_clksel, |
b045d080 PW |
712 | .recalc = &omap2_clksel_recalc, |
713 | }; | |
714 | ||
9cfd985e | 715 | static const struct clksel_rate omap_48m_cm96m_rates[] = { |
b045d080 PW |
716 | { .div = 2, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, |
717 | { .div = 0 } | |
718 | }; | |
719 | ||
720 | static const struct clksel_rate omap_48m_alt_rates[] = { | |
721 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
722 | { .div = 0 } | |
723 | }; | |
724 | ||
725 | static const struct clksel omap_48m_clksel[] = { | |
9cfd985e | 726 | { .parent = &cm_96m_fck, .rates = omap_48m_cm96m_rates }, |
b045d080 PW |
727 | { .parent = &sys_altclk, .rates = omap_48m_alt_rates }, |
728 | { .parent = NULL } | |
729 | }; | |
730 | ||
731 | static struct clk omap_48m_fck = { | |
732 | .name = "omap_48m_fck", | |
57137181 | 733 | .ops = &clkops_null, |
b045d080 PW |
734 | .init = &omap2_init_clksel_parent, |
735 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1), | |
9cfd985e | 736 | .clksel_mask = OMAP3430_SOURCE_48M_MASK, |
b045d080 | 737 | .clksel = omap_48m_clksel, |
b045d080 PW |
738 | .recalc = &omap2_clksel_recalc, |
739 | }; | |
740 | ||
741 | static struct clk omap_12m_fck = { | |
742 | .name = "omap_12m_fck", | |
57137181 | 743 | .ops = &clkops_null, |
b045d080 PW |
744 | .parent = &omap_48m_fck, |
745 | .fixed_div = 4, | |
b045d080 PW |
746 | .recalc = &omap2_fixed_divisor_recalc, |
747 | }; | |
748 | ||
3760d31f RT |
749 | /* This virstual clock is the source for dpll4_m4x2_ck */ |
750 | static struct clk dpll4_m4_ck = { | |
751 | .name = "dpll4_m4_ck", | |
57137181 | 752 | .ops = &clkops_null, |
3760d31f RT |
753 | .parent = &dpll4_ck, |
754 | .init = &omap2_init_clksel_parent, | |
755 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_CLKSEL), | |
756 | .clksel_mask = OMAP3430_CLKSEL_DSS1_MASK, | |
757 | .clksel = div16_dpll4_clksel, | |
46e0ccf8 | 758 | .clkdm_name = "dpll4_clkdm", |
3760d31f | 759 | .recalc = &omap2_clksel_recalc, |
ae8578c0 PW |
760 | .set_rate = &omap2_clksel_set_rate, |
761 | .round_rate = &omap2_clksel_round_rate, | |
3760d31f RT |
762 | }; |
763 | ||
b045d080 PW |
764 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ |
765 | static struct clk dpll4_m4x2_ck = { | |
766 | .name = "dpll4_m4x2_ck", | |
b36ee724 | 767 | .ops = &clkops_omap2_dflt_wait, |
3760d31f | 768 | .parent = &dpll4_m4_ck, |
b045d080 PW |
769 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
770 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
3f0a820c | 771 | .flags = INVERT_ENABLE, |
46e0ccf8 | 772 | .clkdm_name = "dpll4_clkdm", |
3760d31f RT |
773 | .recalc = &omap3_clkoutx2_recalc, |
774 | }; | |
775 | ||
776 | /* This virtual clock is the source for dpll4_m5x2_ck */ | |
777 | static struct clk dpll4_m5_ck = { | |
778 | .name = "dpll4_m5_ck", | |
57137181 | 779 | .ops = &clkops_null, |
3760d31f RT |
780 | .parent = &dpll4_ck, |
781 | .init = &omap2_init_clksel_parent, | |
782 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_CLKSEL), | |
783 | .clksel_mask = OMAP3430_CLKSEL_CAM_MASK, | |
784 | .clksel = div16_dpll4_clksel, | |
46e0ccf8 | 785 | .clkdm_name = "dpll4_clkdm", |
b045d080 PW |
786 | .recalc = &omap2_clksel_recalc, |
787 | }; | |
788 | ||
789 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
790 | static struct clk dpll4_m5x2_ck = { | |
791 | .name = "dpll4_m5x2_ck", | |
b36ee724 | 792 | .ops = &clkops_omap2_dflt_wait, |
3760d31f | 793 | .parent = &dpll4_m5_ck, |
b045d080 PW |
794 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), |
795 | .enable_bit = OMAP3430_PWRDN_CAM_SHIFT, | |
3f0a820c | 796 | .flags = INVERT_ENABLE, |
46e0ccf8 | 797 | .clkdm_name = "dpll4_clkdm", |
3760d31f RT |
798 | .recalc = &omap3_clkoutx2_recalc, |
799 | }; | |
800 | ||
801 | /* This virtual clock is the source for dpll4_m6x2_ck */ | |
802 | static struct clk dpll4_m6_ck = { | |
803 | .name = "dpll4_m6_ck", | |
57137181 | 804 | .ops = &clkops_null, |
3760d31f RT |
805 | .parent = &dpll4_ck, |
806 | .init = &omap2_init_clksel_parent, | |
807 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
808 | .clksel_mask = OMAP3430_DIV_DPLL4_MASK, | |
809 | .clksel = div16_dpll4_clksel, | |
46e0ccf8 | 810 | .clkdm_name = "dpll4_clkdm", |
b045d080 PW |
811 | .recalc = &omap2_clksel_recalc, |
812 | }; | |
813 | ||
814 | /* The PWRDN bit is apparently only available on 3430ES2 and above */ | |
815 | static struct clk dpll4_m6x2_ck = { | |
816 | .name = "dpll4_m6x2_ck", | |
b36ee724 | 817 | .ops = &clkops_omap2_dflt_wait, |
3760d31f | 818 | .parent = &dpll4_m6_ck, |
b045d080 PW |
819 | .init = &omap2_init_clksel_parent, |
820 | .enable_reg = OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN), | |
821 | .enable_bit = OMAP3430_PWRDN_EMU_PERIPH_SHIFT, | |
3f0a820c | 822 | .flags = INVERT_ENABLE, |
46e0ccf8 | 823 | .clkdm_name = "dpll4_clkdm", |
3760d31f | 824 | .recalc = &omap3_clkoutx2_recalc, |
b045d080 PW |
825 | }; |
826 | ||
827 | static struct clk emu_per_alwon_ck = { | |
828 | .name = "emu_per_alwon_ck", | |
57137181 | 829 | .ops = &clkops_null, |
b045d080 | 830 | .parent = &dpll4_m6x2_ck, |
46e0ccf8 | 831 | .clkdm_name = "dpll4_clkdm", |
b045d080 PW |
832 | .recalc = &followparent_recalc, |
833 | }; | |
834 | ||
835 | /* DPLL5 */ | |
836 | /* Supplies 120MHz clock, USIM source clock */ | |
837 | /* Type: DPLL */ | |
838 | /* 3430ES2 only */ | |
88b8ba90 | 839 | static struct dpll_data dpll5_dd = { |
b045d080 PW |
840 | .mult_div1_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL4), |
841 | .mult_mask = OMAP3430ES2_PERIPH2_DPLL_MULT_MASK, | |
842 | .div1_mask = OMAP3430ES2_PERIPH2_DPLL_DIV_MASK, | |
c0bf3132 RK |
843 | .clk_bypass = &sys_ck, |
844 | .clk_ref = &sys_ck, | |
16c90f02 | 845 | .freqsel_mask = OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK, |
b045d080 PW |
846 | .control_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKEN2), |
847 | .enable_mask = OMAP3430ES2_EN_PERIPH2_DPLL_MASK, | |
542313cc | 848 | .modes = (1 << DPLL_LOW_POWER_STOP) | (1 << DPLL_LOCKED), |
b045d080 PW |
849 | .auto_recal_bit = OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT, |
850 | .recal_en_bit = OMAP3430ES2_SND_PERIPH_DPLL_RECAL_EN_SHIFT, | |
851 | .recal_st_bit = OMAP3430ES2_SND_PERIPH_DPLL_ST_SHIFT, | |
542313cc PW |
852 | .autoidle_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_AUTOIDLE2_PLL), |
853 | .autoidle_mask = OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK, | |
854 | .idlest_reg = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST2), | |
c1bd7aaf | 855 | .idlest_mask = OMAP3430ES2_ST_PERIPH2_CLK_MASK, |
88b8ba90 | 856 | .max_multiplier = OMAP3_MAX_DPLL_MULT, |
95f538ac | 857 | .min_divider = 1, |
88b8ba90 PW |
858 | .max_divider = OMAP3_MAX_DPLL_DIV, |
859 | .rate_tolerance = DEFAULT_DPLL_RATE_TOLERANCE | |
b045d080 PW |
860 | }; |
861 | ||
862 | static struct clk dpll5_ck = { | |
863 | .name = "dpll5_ck", | |
548d8495 | 864 | .ops = &clkops_noncore_dpll_ops, |
b045d080 PW |
865 | .parent = &sys_ck, |
866 | .dpll_data = &dpll5_dd, | |
88b8ba90 | 867 | .round_rate = &omap2_dpll_round_rate, |
16c90f02 | 868 | .set_rate = &omap3_noncore_dpll_set_rate, |
46e0ccf8 | 869 | .clkdm_name = "dpll5_clkdm", |
b045d080 PW |
870 | .recalc = &omap3_dpll_recalc, |
871 | }; | |
872 | ||
3760d31f | 873 | static const struct clksel div16_dpll5_clksel[] = { |
b045d080 PW |
874 | { .parent = &dpll5_ck, .rates = div16_dpll_rates }, |
875 | { .parent = NULL } | |
876 | }; | |
877 | ||
878 | static struct clk dpll5_m2_ck = { | |
879 | .name = "dpll5_m2_ck", | |
57137181 | 880 | .ops = &clkops_null, |
b045d080 PW |
881 | .parent = &dpll5_ck, |
882 | .init = &omap2_init_clksel_parent, | |
883 | .clksel_reg = OMAP_CM_REGADDR(PLL_MOD, OMAP3430ES2_CM_CLKSEL5), | |
884 | .clksel_mask = OMAP3430ES2_DIV_120M_MASK, | |
3760d31f | 885 | .clksel = div16_dpll5_clksel, |
46e0ccf8 | 886 | .clkdm_name = "dpll5_clkdm", |
b045d080 PW |
887 | .recalc = &omap2_clksel_recalc, |
888 | }; | |
889 | ||
b045d080 PW |
890 | /* CM EXTERNAL CLOCK OUTPUTS */ |
891 | ||
892 | static const struct clksel_rate clkout2_src_core_rates[] = { | |
893 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
894 | { .div = 0 } | |
895 | }; | |
896 | ||
897 | static const struct clksel_rate clkout2_src_sys_rates[] = { | |
898 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
899 | { .div = 0 } | |
900 | }; | |
901 | ||
902 | static const struct clksel_rate clkout2_src_96m_rates[] = { | |
903 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
904 | { .div = 0 } | |
905 | }; | |
906 | ||
907 | static const struct clksel_rate clkout2_src_54m_rates[] = { | |
908 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
909 | { .div = 0 } | |
910 | }; | |
911 | ||
912 | static const struct clksel clkout2_src_clksel[] = { | |
9cfd985e PW |
913 | { .parent = &core_ck, .rates = clkout2_src_core_rates }, |
914 | { .parent = &sys_ck, .rates = clkout2_src_sys_rates }, | |
915 | { .parent = &cm_96m_fck, .rates = clkout2_src_96m_rates }, | |
916 | { .parent = &omap_54m_fck, .rates = clkout2_src_54m_rates }, | |
b045d080 PW |
917 | { .parent = NULL } |
918 | }; | |
919 | ||
920 | static struct clk clkout2_src_ck = { | |
921 | .name = "clkout2_src_ck", | |
c1168dc3 | 922 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
923 | .init = &omap2_init_clksel_parent, |
924 | .enable_reg = OMAP3430_CM_CLKOUT_CTRL, | |
925 | .enable_bit = OMAP3430_CLKOUT2_EN_SHIFT, | |
926 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
927 | .clksel_mask = OMAP3430_CLKOUT2SOURCE_MASK, | |
928 | .clksel = clkout2_src_clksel, | |
15b52bc4 | 929 | .clkdm_name = "core_clkdm", |
b045d080 PW |
930 | .recalc = &omap2_clksel_recalc, |
931 | }; | |
932 | ||
933 | static const struct clksel_rate sys_clkout2_rates[] = { | |
934 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
935 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
936 | { .div = 4, .val = 2, .flags = RATE_IN_343X }, | |
937 | { .div = 8, .val = 3, .flags = RATE_IN_343X }, | |
938 | { .div = 16, .val = 4, .flags = RATE_IN_343X }, | |
939 | { .div = 0 }, | |
940 | }; | |
941 | ||
942 | static const struct clksel sys_clkout2_clksel[] = { | |
943 | { .parent = &clkout2_src_ck, .rates = sys_clkout2_rates }, | |
944 | { .parent = NULL }, | |
945 | }; | |
946 | ||
947 | static struct clk sys_clkout2 = { | |
948 | .name = "sys_clkout2", | |
57137181 | 949 | .ops = &clkops_null, |
b045d080 PW |
950 | .init = &omap2_init_clksel_parent, |
951 | .clksel_reg = OMAP3430_CM_CLKOUT_CTRL, | |
952 | .clksel_mask = OMAP3430_CLKOUT2_DIV_MASK, | |
953 | .clksel = sys_clkout2_clksel, | |
b045d080 PW |
954 | .recalc = &omap2_clksel_recalc, |
955 | }; | |
956 | ||
957 | /* CM OUTPUT CLOCKS */ | |
958 | ||
959 | static struct clk corex2_fck = { | |
960 | .name = "corex2_fck", | |
57137181 | 961 | .ops = &clkops_null, |
b045d080 | 962 | .parent = &dpll3_m2x2_ck, |
b045d080 PW |
963 | .recalc = &followparent_recalc, |
964 | }; | |
965 | ||
966 | /* DPLL power domain clock controls */ | |
967 | ||
b8168d1e PW |
968 | static const struct clksel_rate div4_rates[] = { |
969 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
970 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
971 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
972 | { .div = 0 } | |
973 | }; | |
974 | ||
975 | static const struct clksel div4_core_clksel[] = { | |
976 | { .parent = &core_ck, .rates = div4_rates }, | |
b045d080 PW |
977 | { .parent = NULL } |
978 | }; | |
979 | ||
3760d31f RT |
980 | /* |
981 | * REVISIT: Are these in DPLL power domain or CM power domain? docs | |
982 | * may be inconsistent here? | |
983 | */ | |
b045d080 PW |
984 | static struct clk dpll1_fck = { |
985 | .name = "dpll1_fck", | |
57137181 | 986 | .ops = &clkops_null, |
b045d080 PW |
987 | .parent = &core_ck, |
988 | .init = &omap2_init_clksel_parent, | |
989 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
990 | .clksel_mask = OMAP3430_MPU_CLK_SRC_MASK, | |
b8168d1e | 991 | .clksel = div4_core_clksel, |
b045d080 PW |
992 | .recalc = &omap2_clksel_recalc, |
993 | }; | |
994 | ||
3760d31f RT |
995 | static struct clk mpu_ck = { |
996 | .name = "mpu_ck", | |
57137181 | 997 | .ops = &clkops_null, |
3760d31f | 998 | .parent = &dpll1_x2m2_ck, |
333943ba | 999 | .clkdm_name = "mpu_clkdm", |
c0bf3132 | 1000 | .recalc = &followparent_recalc, |
3760d31f RT |
1001 | }; |
1002 | ||
1003 | /* arm_fck is divided by two when DPLL1 locked; otherwise, passthrough mpu_ck */ | |
1004 | static const struct clksel_rate arm_fck_rates[] = { | |
1005 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1006 | { .div = 2, .val = 1, .flags = RATE_IN_343X }, | |
1007 | { .div = 0 }, | |
1008 | }; | |
1009 | ||
1010 | static const struct clksel arm_fck_clksel[] = { | |
1011 | { .parent = &mpu_ck, .rates = arm_fck_rates }, | |
1012 | { .parent = NULL } | |
1013 | }; | |
1014 | ||
1015 | static struct clk arm_fck = { | |
1016 | .name = "arm_fck", | |
57137181 | 1017 | .ops = &clkops_null, |
3760d31f RT |
1018 | .parent = &mpu_ck, |
1019 | .init = &omap2_init_clksel_parent, | |
1020 | .clksel_reg = OMAP_CM_REGADDR(MPU_MOD, OMAP3430_CM_IDLEST_PLL), | |
1021 | .clksel_mask = OMAP3430_ST_MPU_CLK_MASK, | |
1022 | .clksel = arm_fck_clksel, | |
3760d31f RT |
1023 | .recalc = &omap2_clksel_recalc, |
1024 | }; | |
1025 | ||
333943ba PW |
1026 | /* XXX What about neon_clkdm ? */ |
1027 | ||
3760d31f RT |
1028 | /* |
1029 | * REVISIT: This clock is never specifically defined in the 3430 TRM, | |
1030 | * although it is referenced - so this is a guess | |
1031 | */ | |
1032 | static struct clk emu_mpu_alwon_ck = { | |
1033 | .name = "emu_mpu_alwon_ck", | |
57137181 | 1034 | .ops = &clkops_null, |
3760d31f | 1035 | .parent = &mpu_ck, |
3760d31f RT |
1036 | .recalc = &followparent_recalc, |
1037 | }; | |
1038 | ||
b045d080 PW |
1039 | static struct clk dpll2_fck = { |
1040 | .name = "dpll2_fck", | |
57137181 | 1041 | .ops = &clkops_null, |
b045d080 PW |
1042 | .parent = &core_ck, |
1043 | .init = &omap2_init_clksel_parent, | |
1044 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSEL1_PLL), | |
1045 | .clksel_mask = OMAP3430_IVA2_CLK_SRC_MASK, | |
b8168d1e | 1046 | .clksel = div4_core_clksel, |
b045d080 PW |
1047 | .recalc = &omap2_clksel_recalc, |
1048 | }; | |
1049 | ||
3760d31f RT |
1050 | static struct clk iva2_ck = { |
1051 | .name = "iva2_ck", | |
b36ee724 | 1052 | .ops = &clkops_omap2_dflt_wait, |
3760d31f RT |
1053 | .parent = &dpll2_m2_ck, |
1054 | .init = &omap2_init_clksel_parent, | |
31c203d4 HD |
1055 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_IVA2_MOD, CM_FCLKEN), |
1056 | .enable_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT, | |
333943ba | 1057 | .clkdm_name = "iva2_clkdm", |
c0bf3132 | 1058 | .recalc = &followparent_recalc, |
3760d31f RT |
1059 | }; |
1060 | ||
b045d080 PW |
1061 | /* Common interface clocks */ |
1062 | ||
b8168d1e PW |
1063 | static const struct clksel div2_core_clksel[] = { |
1064 | { .parent = &core_ck, .rates = div2_rates }, | |
1065 | { .parent = NULL } | |
1066 | }; | |
1067 | ||
b045d080 PW |
1068 | static struct clk l3_ick = { |
1069 | .name = "l3_ick", | |
57137181 | 1070 | .ops = &clkops_null, |
b045d080 PW |
1071 | .parent = &core_ck, |
1072 | .init = &omap2_init_clksel_parent, | |
1073 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1074 | .clksel_mask = OMAP3430_CLKSEL_L3_MASK, | |
1075 | .clksel = div2_core_clksel, | |
333943ba | 1076 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1077 | .recalc = &omap2_clksel_recalc, |
1078 | }; | |
1079 | ||
1080 | static const struct clksel div2_l3_clksel[] = { | |
1081 | { .parent = &l3_ick, .rates = div2_rates }, | |
1082 | { .parent = NULL } | |
1083 | }; | |
1084 | ||
1085 | static struct clk l4_ick = { | |
1086 | .name = "l4_ick", | |
57137181 | 1087 | .ops = &clkops_null, |
b045d080 PW |
1088 | .parent = &l3_ick, |
1089 | .init = &omap2_init_clksel_parent, | |
1090 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1091 | .clksel_mask = OMAP3430_CLKSEL_L4_MASK, | |
1092 | .clksel = div2_l3_clksel, | |
333943ba | 1093 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1094 | .recalc = &omap2_clksel_recalc, |
1095 | ||
1096 | }; | |
1097 | ||
1098 | static const struct clksel div2_l4_clksel[] = { | |
1099 | { .parent = &l4_ick, .rates = div2_rates }, | |
1100 | { .parent = NULL } | |
1101 | }; | |
1102 | ||
1103 | static struct clk rm_ick = { | |
1104 | .name = "rm_ick", | |
57137181 | 1105 | .ops = &clkops_null, |
b045d080 PW |
1106 | .parent = &l4_ick, |
1107 | .init = &omap2_init_clksel_parent, | |
1108 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
1109 | .clksel_mask = OMAP3430_CLKSEL_RM_MASK, | |
1110 | .clksel = div2_l4_clksel, | |
b045d080 PW |
1111 | .recalc = &omap2_clksel_recalc, |
1112 | }; | |
1113 | ||
1114 | /* GFX power domain */ | |
1115 | ||
3760d31f | 1116 | /* GFX clocks are in 3430ES1 only. 3430ES2 and later uses the SGX instead */ |
b045d080 PW |
1117 | |
1118 | static const struct clksel gfx_l3_clksel[] = { | |
1119 | { .parent = &l3_ick, .rates = gfx_l3_rates }, | |
1120 | { .parent = NULL } | |
1121 | }; | |
1122 | ||
5955902f HJ |
1123 | /* Virtual parent clock for gfx_l3_ick and gfx_l3_fck */ |
1124 | static struct clk gfx_l3_ck = { | |
1125 | .name = "gfx_l3_ck", | |
b36ee724 | 1126 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1127 | .parent = &l3_ick, |
1128 | .init = &omap2_init_clksel_parent, | |
1129 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN), | |
1130 | .enable_bit = OMAP_EN_GFX_SHIFT, | |
5955902f HJ |
1131 | .recalc = &followparent_recalc, |
1132 | }; | |
1133 | ||
1134 | static struct clk gfx_l3_fck = { | |
1135 | .name = "gfx_l3_fck", | |
57137181 | 1136 | .ops = &clkops_null, |
5955902f HJ |
1137 | .parent = &gfx_l3_ck, |
1138 | .init = &omap2_init_clksel_parent, | |
b045d080 PW |
1139 | .clksel_reg = OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL), |
1140 | .clksel_mask = OMAP_CLKSEL_GFX_MASK, | |
1141 | .clksel = gfx_l3_clksel, | |
333943ba | 1142 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1143 | .recalc = &omap2_clksel_recalc, |
1144 | }; | |
1145 | ||
1146 | static struct clk gfx_l3_ick = { | |
1147 | .name = "gfx_l3_ick", | |
57137181 | 1148 | .ops = &clkops_null, |
5955902f | 1149 | .parent = &gfx_l3_ck, |
333943ba | 1150 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1151 | .recalc = &followparent_recalc, |
1152 | }; | |
1153 | ||
1154 | static struct clk gfx_cg1_ck = { | |
1155 | .name = "gfx_cg1_ck", | |
b36ee724 | 1156 | .ops = &clkops_omap2_dflt_wait, |
b045d080 | 1157 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
333943ba | 1158 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1159 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1160 | .enable_bit = OMAP3430ES1_EN_2D_SHIFT, | |
333943ba | 1161 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1162 | .recalc = &followparent_recalc, |
1163 | }; | |
1164 | ||
1165 | static struct clk gfx_cg2_ck = { | |
1166 | .name = "gfx_cg2_ck", | |
b36ee724 | 1167 | .ops = &clkops_omap2_dflt_wait, |
b045d080 | 1168 | .parent = &gfx_l3_fck, /* REVISIT: correct? */ |
333943ba | 1169 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1170 | .enable_reg = OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN), |
1171 | .enable_bit = OMAP3430ES1_EN_3D_SHIFT, | |
333943ba | 1172 | .clkdm_name = "gfx_3430es1_clkdm", |
b045d080 PW |
1173 | .recalc = &followparent_recalc, |
1174 | }; | |
1175 | ||
1176 | /* SGX power domain - 3430ES2 only */ | |
1177 | ||
1178 | static const struct clksel_rate sgx_core_rates[] = { | |
1179 | { .div = 3, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1180 | { .div = 4, .val = 1, .flags = RATE_IN_343X }, | |
1181 | { .div = 6, .val = 2, .flags = RATE_IN_343X }, | |
1182 | { .div = 0 }, | |
1183 | }; | |
1184 | ||
1185 | static const struct clksel_rate sgx_96m_rates[] = { | |
1186 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1187 | { .div = 0 }, | |
1188 | }; | |
1189 | ||
1190 | static const struct clksel sgx_clksel[] = { | |
1191 | { .parent = &core_ck, .rates = sgx_core_rates }, | |
1192 | { .parent = &cm_96m_fck, .rates = sgx_96m_rates }, | |
1193 | { .parent = NULL }, | |
1194 | }; | |
1195 | ||
1196 | static struct clk sgx_fck = { | |
1197 | .name = "sgx_fck", | |
b36ee724 | 1198 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1199 | .init = &omap2_init_clksel_parent, |
1200 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_FCLKEN), | |
712d7c86 | 1201 | .enable_bit = OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT, |
b045d080 PW |
1202 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_CLKSEL), |
1203 | .clksel_mask = OMAP3430ES2_CLKSEL_SGX_MASK, | |
1204 | .clksel = sgx_clksel, | |
333943ba | 1205 | .clkdm_name = "sgx_clkdm", |
b045d080 PW |
1206 | .recalc = &omap2_clksel_recalc, |
1207 | }; | |
1208 | ||
1209 | static struct clk sgx_ick = { | |
1210 | .name = "sgx_ick", | |
b36ee724 | 1211 | .ops = &clkops_omap2_dflt_wait, |
b045d080 | 1212 | .parent = &l3_ick, |
333943ba | 1213 | .init = &omap2_init_clk_clkdm, |
b045d080 | 1214 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_SGX_MOD, CM_ICLKEN), |
712d7c86 | 1215 | .enable_bit = OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT, |
333943ba | 1216 | .clkdm_name = "sgx_clkdm", |
b045d080 PW |
1217 | .recalc = &followparent_recalc, |
1218 | }; | |
1219 | ||
1220 | /* CORE power domain */ | |
1221 | ||
1222 | static struct clk d2d_26m_fck = { | |
1223 | .name = "d2d_26m_fck", | |
b36ee724 | 1224 | .ops = &clkops_omap2_dflt_wait, |
b045d080 | 1225 | .parent = &sys_ck, |
333943ba | 1226 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
1227 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), |
1228 | .enable_bit = OMAP3430ES1_EN_D2D_SHIFT, | |
333943ba | 1229 | .clkdm_name = "d2d_clkdm", |
b045d080 PW |
1230 | .recalc = &followparent_recalc, |
1231 | }; | |
1232 | ||
8111b221 KH |
1233 | static struct clk modem_fck = { |
1234 | .name = "modem_fck", | |
1235 | .ops = &clkops_omap2_dflt_wait, | |
1236 | .parent = &sys_ck, | |
1237 | .init = &omap2_init_clk_clkdm, | |
1238 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1239 | .enable_bit = OMAP3430_EN_MODEM_SHIFT, | |
1240 | .clkdm_name = "d2d_clkdm", | |
1241 | .recalc = &followparent_recalc, | |
1242 | }; | |
1243 | ||
1244 | static struct clk sad2d_ick = { | |
1245 | .name = "sad2d_ick", | |
1246 | .ops = &clkops_omap2_dflt_wait, | |
1247 | .parent = &l3_ick, | |
1248 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1249 | .enable_bit = OMAP3430_EN_SAD2D_SHIFT, | |
1250 | .clkdm_name = "d2d_clkdm", | |
1251 | .recalc = &followparent_recalc, | |
1252 | }; | |
1253 | ||
1254 | static struct clk mad2d_ick = { | |
1255 | .name = "mad2d_ick", | |
1256 | .ops = &clkops_omap2_dflt_wait, | |
1257 | .parent = &l3_ick, | |
1258 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1259 | .enable_bit = OMAP3430_EN_MAD2D_SHIFT, | |
1260 | .clkdm_name = "d2d_clkdm", | |
1261 | .recalc = &followparent_recalc, | |
1262 | }; | |
1263 | ||
b045d080 PW |
1264 | static const struct clksel omap343x_gpt_clksel[] = { |
1265 | { .parent = &omap_32k_fck, .rates = gpt_32k_rates }, | |
1266 | { .parent = &sys_ck, .rates = gpt_sys_rates }, | |
1267 | { .parent = NULL} | |
1268 | }; | |
1269 | ||
1270 | static struct clk gpt10_fck = { | |
1271 | .name = "gpt10_fck", | |
b36ee724 | 1272 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1273 | .parent = &sys_ck, |
1274 | .init = &omap2_init_clksel_parent, | |
1275 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1276 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
1277 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1278 | .clksel_mask = OMAP3430_CLKSEL_GPT10_MASK, | |
1279 | .clksel = omap343x_gpt_clksel, | |
333943ba | 1280 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1281 | .recalc = &omap2_clksel_recalc, |
1282 | }; | |
1283 | ||
1284 | static struct clk gpt11_fck = { | |
1285 | .name = "gpt11_fck", | |
b36ee724 | 1286 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1287 | .parent = &sys_ck, |
1288 | .init = &omap2_init_clksel_parent, | |
1289 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1290 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
1291 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1292 | .clksel_mask = OMAP3430_CLKSEL_GPT11_MASK, | |
1293 | .clksel = omap343x_gpt_clksel, | |
333943ba | 1294 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1295 | .recalc = &omap2_clksel_recalc, |
1296 | }; | |
1297 | ||
1298 | static struct clk cpefuse_fck = { | |
1299 | .name = "cpefuse_fck", | |
c1168dc3 | 1300 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
1301 | .parent = &sys_ck, |
1302 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1303 | .enable_bit = OMAP3430ES2_EN_CPEFUSE_SHIFT, | |
b045d080 PW |
1304 | .recalc = &followparent_recalc, |
1305 | }; | |
1306 | ||
1307 | static struct clk ts_fck = { | |
1308 | .name = "ts_fck", | |
c1168dc3 | 1309 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
1310 | .parent = &omap_32k_fck, |
1311 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), | |
1312 | .enable_bit = OMAP3430ES2_EN_TS_SHIFT, | |
b045d080 PW |
1313 | .recalc = &followparent_recalc, |
1314 | }; | |
1315 | ||
1316 | static struct clk usbtll_fck = { | |
1317 | .name = "usbtll_fck", | |
c1168dc3 | 1318 | .ops = &clkops_omap2_dflt, |
c0bf3132 | 1319 | .parent = &dpll5_m2_ck, |
b045d080 PW |
1320 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP3430ES2_CM_FCLKEN3), |
1321 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
b045d080 PW |
1322 | .recalc = &followparent_recalc, |
1323 | }; | |
1324 | ||
1325 | /* CORE 96M FCLK-derived clocks */ | |
1326 | ||
1327 | static struct clk core_96m_fck = { | |
1328 | .name = "core_96m_fck", | |
57137181 | 1329 | .ops = &clkops_null, |
b045d080 | 1330 | .parent = &omap_96m_fck, |
333943ba | 1331 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1332 | .recalc = &followparent_recalc, |
1333 | }; | |
1334 | ||
1335 | static struct clk mmchs3_fck = { | |
1336 | .name = "mmchs_fck", | |
b36ee724 | 1337 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 1338 | .id = 2, |
b045d080 PW |
1339 | .parent = &core_96m_fck, |
1340 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1341 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
333943ba | 1342 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1343 | .recalc = &followparent_recalc, |
1344 | }; | |
1345 | ||
1346 | static struct clk mmchs2_fck = { | |
1347 | .name = "mmchs_fck", | |
b36ee724 | 1348 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 1349 | .id = 1, |
b045d080 PW |
1350 | .parent = &core_96m_fck, |
1351 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1352 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
333943ba | 1353 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1354 | .recalc = &followparent_recalc, |
1355 | }; | |
1356 | ||
1357 | static struct clk mspro_fck = { | |
1358 | .name = "mspro_fck", | |
b36ee724 | 1359 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1360 | .parent = &core_96m_fck, |
1361 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1362 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
333943ba | 1363 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1364 | .recalc = &followparent_recalc, |
1365 | }; | |
1366 | ||
1367 | static struct clk mmchs1_fck = { | |
1368 | .name = "mmchs_fck", | |
b36ee724 | 1369 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1370 | .parent = &core_96m_fck, |
1371 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1372 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
333943ba | 1373 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1374 | .recalc = &followparent_recalc, |
1375 | }; | |
1376 | ||
1377 | static struct clk i2c3_fck = { | |
1378 | .name = "i2c_fck", | |
b36ee724 | 1379 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1380 | .id = 3, |
1381 | .parent = &core_96m_fck, | |
1382 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1383 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
333943ba | 1384 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1385 | .recalc = &followparent_recalc, |
1386 | }; | |
1387 | ||
1388 | static struct clk i2c2_fck = { | |
1389 | .name = "i2c_fck", | |
b36ee724 | 1390 | .ops = &clkops_omap2_dflt_wait, |
333943ba | 1391 | .id = 2, |
b045d080 PW |
1392 | .parent = &core_96m_fck, |
1393 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1394 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
333943ba | 1395 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1396 | .recalc = &followparent_recalc, |
1397 | }; | |
1398 | ||
1399 | static struct clk i2c1_fck = { | |
1400 | .name = "i2c_fck", | |
b36ee724 | 1401 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1402 | .id = 1, |
1403 | .parent = &core_96m_fck, | |
1404 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1405 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
333943ba | 1406 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1407 | .recalc = &followparent_recalc, |
1408 | }; | |
1409 | ||
1410 | /* | |
1411 | * MCBSP 1 & 5 get their 96MHz clock from core_96m_fck; | |
1412 | * MCBSP 2, 3, 4 get their 96MHz clock from per_96m_fck. | |
1413 | */ | |
1414 | static const struct clksel_rate common_mcbsp_96m_rates[] = { | |
1415 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1416 | { .div = 0 } | |
1417 | }; | |
1418 | ||
1419 | static const struct clksel_rate common_mcbsp_mcbsp_rates[] = { | |
1420 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1421 | { .div = 0 } | |
1422 | }; | |
1423 | ||
1424 | static const struct clksel mcbsp_15_clksel[] = { | |
1425 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, | |
1426 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
1427 | { .parent = NULL } | |
1428 | }; | |
1429 | ||
1430 | static struct clk mcbsp5_fck = { | |
78673bc8 | 1431 | .name = "mcbsp_fck", |
b36ee724 | 1432 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 1433 | .id = 5, |
b045d080 PW |
1434 | .init = &omap2_init_clksel_parent, |
1435 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1436 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
1437 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
1438 | .clksel_mask = OMAP2_MCBSP5_CLKS_MASK, | |
1439 | .clksel = mcbsp_15_clksel, | |
333943ba | 1440 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1441 | .recalc = &omap2_clksel_recalc, |
1442 | }; | |
1443 | ||
1444 | static struct clk mcbsp1_fck = { | |
78673bc8 | 1445 | .name = "mcbsp_fck", |
b36ee724 | 1446 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 1447 | .id = 1, |
b045d080 PW |
1448 | .init = &omap2_init_clksel_parent, |
1449 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1450 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
1451 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
1452 | .clksel_mask = OMAP2_MCBSP1_CLKS_MASK, | |
1453 | .clksel = mcbsp_15_clksel, | |
333943ba | 1454 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1455 | .recalc = &omap2_clksel_recalc, |
1456 | }; | |
1457 | ||
1458 | /* CORE_48M_FCK-derived clocks */ | |
1459 | ||
1460 | static struct clk core_48m_fck = { | |
1461 | .name = "core_48m_fck", | |
57137181 | 1462 | .ops = &clkops_null, |
b045d080 | 1463 | .parent = &omap_48m_fck, |
333943ba | 1464 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1465 | .recalc = &followparent_recalc, |
1466 | }; | |
1467 | ||
1468 | static struct clk mcspi4_fck = { | |
1469 | .name = "mcspi_fck", | |
b36ee724 | 1470 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1471 | .id = 4, |
1472 | .parent = &core_48m_fck, | |
1473 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1474 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
b045d080 PW |
1475 | .recalc = &followparent_recalc, |
1476 | }; | |
1477 | ||
1478 | static struct clk mcspi3_fck = { | |
1479 | .name = "mcspi_fck", | |
b36ee724 | 1480 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1481 | .id = 3, |
1482 | .parent = &core_48m_fck, | |
1483 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1484 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
b045d080 PW |
1485 | .recalc = &followparent_recalc, |
1486 | }; | |
1487 | ||
1488 | static struct clk mcspi2_fck = { | |
1489 | .name = "mcspi_fck", | |
b36ee724 | 1490 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1491 | .id = 2, |
1492 | .parent = &core_48m_fck, | |
1493 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1494 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
b045d080 PW |
1495 | .recalc = &followparent_recalc, |
1496 | }; | |
1497 | ||
1498 | static struct clk mcspi1_fck = { | |
1499 | .name = "mcspi_fck", | |
b36ee724 | 1500 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1501 | .id = 1, |
1502 | .parent = &core_48m_fck, | |
1503 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1504 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
b045d080 PW |
1505 | .recalc = &followparent_recalc, |
1506 | }; | |
1507 | ||
1508 | static struct clk uart2_fck = { | |
1509 | .name = "uart2_fck", | |
b36ee724 | 1510 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1511 | .parent = &core_48m_fck, |
1512 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1513 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
b045d080 PW |
1514 | .recalc = &followparent_recalc, |
1515 | }; | |
1516 | ||
1517 | static struct clk uart1_fck = { | |
1518 | .name = "uart1_fck", | |
b36ee724 | 1519 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1520 | .parent = &core_48m_fck, |
1521 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1522 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
b045d080 PW |
1523 | .recalc = &followparent_recalc, |
1524 | }; | |
1525 | ||
1526 | static struct clk fshostusb_fck = { | |
1527 | .name = "fshostusb_fck", | |
b36ee724 | 1528 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1529 | .parent = &core_48m_fck, |
1530 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1531 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
b045d080 PW |
1532 | .recalc = &followparent_recalc, |
1533 | }; | |
1534 | ||
1535 | /* CORE_12M_FCK based clocks */ | |
1536 | ||
1537 | static struct clk core_12m_fck = { | |
1538 | .name = "core_12m_fck", | |
57137181 | 1539 | .ops = &clkops_null, |
b045d080 | 1540 | .parent = &omap_12m_fck, |
333943ba | 1541 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1542 | .recalc = &followparent_recalc, |
1543 | }; | |
1544 | ||
1545 | static struct clk hdq_fck = { | |
1546 | .name = "hdq_fck", | |
b36ee724 | 1547 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1548 | .parent = &core_12m_fck, |
1549 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1550 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
b045d080 PW |
1551 | .recalc = &followparent_recalc, |
1552 | }; | |
1553 | ||
1554 | /* DPLL3-derived clock */ | |
1555 | ||
1556 | static const struct clksel_rate ssi_ssr_corex2_rates[] = { | |
1557 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
1558 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
1559 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
1560 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
1561 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
1562 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
1563 | { .div = 0 } | |
1564 | }; | |
1565 | ||
1566 | static const struct clksel ssi_ssr_clksel[] = { | |
1567 | { .parent = &corex2_fck, .rates = ssi_ssr_corex2_rates }, | |
1568 | { .parent = NULL } | |
1569 | }; | |
1570 | ||
3c82e229 | 1571 | static struct clk ssi_ssr_fck_3430es1 = { |
b045d080 | 1572 | .name = "ssi_ssr_fck", |
bc51da4e | 1573 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
1574 | .init = &omap2_init_clksel_parent, |
1575 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1576 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1577 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1578 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1579 | .clksel = ssi_ssr_clksel, | |
333943ba | 1580 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1581 | .recalc = &omap2_clksel_recalc, |
1582 | }; | |
1583 | ||
3c82e229 PW |
1584 | static struct clk ssi_ssr_fck_3430es2 = { |
1585 | .name = "ssi_ssr_fck", | |
1586 | .ops = &clkops_omap3430es2_ssi_wait, | |
1587 | .init = &omap2_init_clksel_parent, | |
1588 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1), | |
1589 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1590 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
1591 | .clksel_mask = OMAP3430_CLKSEL_SSI_MASK, | |
1592 | .clksel = ssi_ssr_clksel, | |
1593 | .clkdm_name = "core_l4_clkdm", | |
1594 | .recalc = &omap2_clksel_recalc, | |
1595 | }; | |
1596 | ||
1597 | static struct clk ssi_sst_fck_3430es1 = { | |
b045d080 | 1598 | .name = "ssi_sst_fck", |
57137181 | 1599 | .ops = &clkops_null, |
3c82e229 PW |
1600 | .parent = &ssi_ssr_fck_3430es1, |
1601 | .fixed_div = 2, | |
1602 | .recalc = &omap2_fixed_divisor_recalc, | |
1603 | }; | |
1604 | ||
1605 | static struct clk ssi_sst_fck_3430es2 = { | |
1606 | .name = "ssi_sst_fck", | |
1607 | .ops = &clkops_null, | |
1608 | .parent = &ssi_ssr_fck_3430es2, | |
b045d080 | 1609 | .fixed_div = 2, |
b045d080 PW |
1610 | .recalc = &omap2_fixed_divisor_recalc, |
1611 | }; | |
1612 | ||
1613 | ||
1614 | ||
1615 | /* CORE_L3_ICK based clocks */ | |
1616 | ||
333943ba PW |
1617 | /* |
1618 | * XXX must add clk_enable/clk_disable for these if standard code won't | |
1619 | * handle it | |
1620 | */ | |
b045d080 PW |
1621 | static struct clk core_l3_ick = { |
1622 | .name = "core_l3_ick", | |
57137181 | 1623 | .ops = &clkops_null, |
b045d080 | 1624 | .parent = &l3_ick, |
333943ba | 1625 | .init = &omap2_init_clk_clkdm, |
333943ba | 1626 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1627 | .recalc = &followparent_recalc, |
1628 | }; | |
1629 | ||
3c82e229 | 1630 | static struct clk hsotgusb_ick_3430es1 = { |
b045d080 | 1631 | .name = "hsotgusb_ick", |
3c82e229 PW |
1632 | .ops = &clkops_omap2_dflt, |
1633 | .parent = &core_l3_ick, | |
1634 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1635 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
1636 | .clkdm_name = "core_l3_clkdm", | |
1637 | .recalc = &followparent_recalc, | |
1638 | }; | |
1639 | ||
1640 | static struct clk hsotgusb_ick_3430es2 = { | |
1641 | .name = "hsotgusb_ick", | |
1642 | .ops = &clkops_omap3430es2_hsotgusb_wait, | |
b045d080 PW |
1643 | .parent = &core_l3_ick, |
1644 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1645 | .enable_bit = OMAP3430_EN_HSOTGUSB_SHIFT, | |
333943ba | 1646 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1647 | .recalc = &followparent_recalc, |
1648 | }; | |
1649 | ||
1650 | static struct clk sdrc_ick = { | |
1651 | .name = "sdrc_ick", | |
b36ee724 | 1652 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1653 | .parent = &core_l3_ick, |
1654 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1655 | .enable_bit = OMAP3430_EN_SDRC_SHIFT, | |
44dc9d02 | 1656 | .flags = ENABLE_ON_INIT, |
333943ba | 1657 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1658 | .recalc = &followparent_recalc, |
1659 | }; | |
1660 | ||
1661 | static struct clk gpmc_fck = { | |
1662 | .name = "gpmc_fck", | |
57137181 | 1663 | .ops = &clkops_null, |
b045d080 | 1664 | .parent = &core_l3_ick, |
44dc9d02 | 1665 | .flags = ENABLE_ON_INIT, /* huh? */ |
333943ba | 1666 | .clkdm_name = "core_l3_clkdm", |
b045d080 PW |
1667 | .recalc = &followparent_recalc, |
1668 | }; | |
1669 | ||
1670 | /* SECURITY_L3_ICK based clocks */ | |
1671 | ||
1672 | static struct clk security_l3_ick = { | |
1673 | .name = "security_l3_ick", | |
57137181 | 1674 | .ops = &clkops_null, |
b045d080 | 1675 | .parent = &l3_ick, |
b045d080 PW |
1676 | .recalc = &followparent_recalc, |
1677 | }; | |
1678 | ||
1679 | static struct clk pka_ick = { | |
1680 | .name = "pka_ick", | |
b36ee724 | 1681 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1682 | .parent = &security_l3_ick, |
1683 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
1684 | .enable_bit = OMAP3430_EN_PKA_SHIFT, | |
b045d080 PW |
1685 | .recalc = &followparent_recalc, |
1686 | }; | |
1687 | ||
1688 | /* CORE_L4_ICK based clocks */ | |
1689 | ||
1690 | static struct clk core_l4_ick = { | |
1691 | .name = "core_l4_ick", | |
57137181 | 1692 | .ops = &clkops_null, |
b045d080 | 1693 | .parent = &l4_ick, |
333943ba | 1694 | .init = &omap2_init_clk_clkdm, |
333943ba | 1695 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1696 | .recalc = &followparent_recalc, |
1697 | }; | |
1698 | ||
1699 | static struct clk usbtll_ick = { | |
1700 | .name = "usbtll_ick", | |
b36ee724 | 1701 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1702 | .parent = &core_l4_ick, |
1703 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3), | |
1704 | .enable_bit = OMAP3430ES2_EN_USBTLL_SHIFT, | |
333943ba | 1705 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1706 | .recalc = &followparent_recalc, |
1707 | }; | |
1708 | ||
1709 | static struct clk mmchs3_ick = { | |
1710 | .name = "mmchs_ick", | |
b36ee724 | 1711 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 1712 | .id = 2, |
b045d080 PW |
1713 | .parent = &core_l4_ick, |
1714 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1715 | .enable_bit = OMAP3430ES2_EN_MMC3_SHIFT, | |
333943ba | 1716 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1717 | .recalc = &followparent_recalc, |
1718 | }; | |
1719 | ||
1720 | /* Intersystem Communication Registers - chassis mode only */ | |
1721 | static struct clk icr_ick = { | |
1722 | .name = "icr_ick", | |
b36ee724 | 1723 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1724 | .parent = &core_l4_ick, |
1725 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1726 | .enable_bit = OMAP3430_EN_ICR_SHIFT, | |
333943ba | 1727 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1728 | .recalc = &followparent_recalc, |
1729 | }; | |
1730 | ||
1731 | static struct clk aes2_ick = { | |
1732 | .name = "aes2_ick", | |
b36ee724 | 1733 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1734 | .parent = &core_l4_ick, |
1735 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1736 | .enable_bit = OMAP3430_EN_AES2_SHIFT, | |
333943ba | 1737 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1738 | .recalc = &followparent_recalc, |
1739 | }; | |
1740 | ||
1741 | static struct clk sha12_ick = { | |
1742 | .name = "sha12_ick", | |
b36ee724 | 1743 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1744 | .parent = &core_l4_ick, |
1745 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1746 | .enable_bit = OMAP3430_EN_SHA12_SHIFT, | |
333943ba | 1747 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1748 | .recalc = &followparent_recalc, |
1749 | }; | |
1750 | ||
1751 | static struct clk des2_ick = { | |
1752 | .name = "des2_ick", | |
b36ee724 | 1753 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1754 | .parent = &core_l4_ick, |
1755 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1756 | .enable_bit = OMAP3430_EN_DES2_SHIFT, | |
333943ba | 1757 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1758 | .recalc = &followparent_recalc, |
1759 | }; | |
1760 | ||
1761 | static struct clk mmchs2_ick = { | |
1762 | .name = "mmchs_ick", | |
b36ee724 | 1763 | .ops = &clkops_omap2_dflt_wait, |
d8874665 | 1764 | .id = 1, |
b045d080 PW |
1765 | .parent = &core_l4_ick, |
1766 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1767 | .enable_bit = OMAP3430_EN_MMC2_SHIFT, | |
333943ba | 1768 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1769 | .recalc = &followparent_recalc, |
1770 | }; | |
1771 | ||
1772 | static struct clk mmchs1_ick = { | |
1773 | .name = "mmchs_ick", | |
b36ee724 | 1774 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1775 | .parent = &core_l4_ick, |
1776 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1777 | .enable_bit = OMAP3430_EN_MMC1_SHIFT, | |
333943ba | 1778 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1779 | .recalc = &followparent_recalc, |
1780 | }; | |
1781 | ||
1782 | static struct clk mspro_ick = { | |
1783 | .name = "mspro_ick", | |
b36ee724 | 1784 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1785 | .parent = &core_l4_ick, |
1786 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1787 | .enable_bit = OMAP3430_EN_MSPRO_SHIFT, | |
333943ba | 1788 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1789 | .recalc = &followparent_recalc, |
1790 | }; | |
1791 | ||
1792 | static struct clk hdq_ick = { | |
1793 | .name = "hdq_ick", | |
b36ee724 | 1794 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1795 | .parent = &core_l4_ick, |
1796 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1797 | .enable_bit = OMAP3430_EN_HDQ_SHIFT, | |
333943ba | 1798 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1799 | .recalc = &followparent_recalc, |
1800 | }; | |
1801 | ||
1802 | static struct clk mcspi4_ick = { | |
1803 | .name = "mcspi_ick", | |
b36ee724 | 1804 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1805 | .id = 4, |
1806 | .parent = &core_l4_ick, | |
1807 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1808 | .enable_bit = OMAP3430_EN_MCSPI4_SHIFT, | |
333943ba | 1809 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1810 | .recalc = &followparent_recalc, |
1811 | }; | |
1812 | ||
1813 | static struct clk mcspi3_ick = { | |
1814 | .name = "mcspi_ick", | |
b36ee724 | 1815 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1816 | .id = 3, |
1817 | .parent = &core_l4_ick, | |
1818 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1819 | .enable_bit = OMAP3430_EN_MCSPI3_SHIFT, | |
333943ba | 1820 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1821 | .recalc = &followparent_recalc, |
1822 | }; | |
1823 | ||
1824 | static struct clk mcspi2_ick = { | |
1825 | .name = "mcspi_ick", | |
b36ee724 | 1826 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1827 | .id = 2, |
1828 | .parent = &core_l4_ick, | |
1829 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1830 | .enable_bit = OMAP3430_EN_MCSPI2_SHIFT, | |
333943ba | 1831 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1832 | .recalc = &followparent_recalc, |
1833 | }; | |
1834 | ||
1835 | static struct clk mcspi1_ick = { | |
1836 | .name = "mcspi_ick", | |
b36ee724 | 1837 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1838 | .id = 1, |
1839 | .parent = &core_l4_ick, | |
1840 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1841 | .enable_bit = OMAP3430_EN_MCSPI1_SHIFT, | |
333943ba | 1842 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1843 | .recalc = &followparent_recalc, |
1844 | }; | |
1845 | ||
1846 | static struct clk i2c3_ick = { | |
1847 | .name = "i2c_ick", | |
b36ee724 | 1848 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1849 | .id = 3, |
1850 | .parent = &core_l4_ick, | |
1851 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1852 | .enable_bit = OMAP3430_EN_I2C3_SHIFT, | |
333943ba | 1853 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1854 | .recalc = &followparent_recalc, |
1855 | }; | |
1856 | ||
1857 | static struct clk i2c2_ick = { | |
1858 | .name = "i2c_ick", | |
b36ee724 | 1859 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1860 | .id = 2, |
1861 | .parent = &core_l4_ick, | |
1862 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1863 | .enable_bit = OMAP3430_EN_I2C2_SHIFT, | |
333943ba | 1864 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1865 | .recalc = &followparent_recalc, |
1866 | }; | |
1867 | ||
1868 | static struct clk i2c1_ick = { | |
1869 | .name = "i2c_ick", | |
b36ee724 | 1870 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1871 | .id = 1, |
1872 | .parent = &core_l4_ick, | |
1873 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1874 | .enable_bit = OMAP3430_EN_I2C1_SHIFT, | |
333943ba | 1875 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1876 | .recalc = &followparent_recalc, |
1877 | }; | |
1878 | ||
1879 | static struct clk uart2_ick = { | |
1880 | .name = "uart2_ick", | |
b36ee724 | 1881 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1882 | .parent = &core_l4_ick, |
1883 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1884 | .enable_bit = OMAP3430_EN_UART2_SHIFT, | |
333943ba | 1885 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1886 | .recalc = &followparent_recalc, |
1887 | }; | |
1888 | ||
1889 | static struct clk uart1_ick = { | |
1890 | .name = "uart1_ick", | |
b36ee724 | 1891 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1892 | .parent = &core_l4_ick, |
1893 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1894 | .enable_bit = OMAP3430_EN_UART1_SHIFT, | |
333943ba | 1895 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1896 | .recalc = &followparent_recalc, |
1897 | }; | |
1898 | ||
1899 | static struct clk gpt11_ick = { | |
1900 | .name = "gpt11_ick", | |
b36ee724 | 1901 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1902 | .parent = &core_l4_ick, |
1903 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1904 | .enable_bit = OMAP3430_EN_GPT11_SHIFT, | |
333943ba | 1905 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1906 | .recalc = &followparent_recalc, |
1907 | }; | |
1908 | ||
1909 | static struct clk gpt10_ick = { | |
1910 | .name = "gpt10_ick", | |
b36ee724 | 1911 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1912 | .parent = &core_l4_ick, |
1913 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1914 | .enable_bit = OMAP3430_EN_GPT10_SHIFT, | |
333943ba | 1915 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1916 | .recalc = &followparent_recalc, |
1917 | }; | |
1918 | ||
1919 | static struct clk mcbsp5_ick = { | |
78673bc8 | 1920 | .name = "mcbsp_ick", |
b36ee724 | 1921 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 1922 | .id = 5, |
b045d080 PW |
1923 | .parent = &core_l4_ick, |
1924 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1925 | .enable_bit = OMAP3430_EN_MCBSP5_SHIFT, | |
333943ba | 1926 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1927 | .recalc = &followparent_recalc, |
1928 | }; | |
1929 | ||
1930 | static struct clk mcbsp1_ick = { | |
78673bc8 | 1931 | .name = "mcbsp_ick", |
b36ee724 | 1932 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 1933 | .id = 1, |
b045d080 PW |
1934 | .parent = &core_l4_ick, |
1935 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1936 | .enable_bit = OMAP3430_EN_MCBSP1_SHIFT, | |
333943ba | 1937 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1938 | .recalc = &followparent_recalc, |
1939 | }; | |
1940 | ||
1941 | static struct clk fac_ick = { | |
1942 | .name = "fac_ick", | |
b36ee724 | 1943 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1944 | .parent = &core_l4_ick, |
1945 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1946 | .enable_bit = OMAP3430ES1_EN_FAC_SHIFT, | |
333943ba | 1947 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1948 | .recalc = &followparent_recalc, |
1949 | }; | |
1950 | ||
1951 | static struct clk mailboxes_ick = { | |
1952 | .name = "mailboxes_ick", | |
b36ee724 | 1953 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1954 | .parent = &core_l4_ick, |
1955 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1956 | .enable_bit = OMAP3430_EN_MAILBOXES_SHIFT, | |
333943ba | 1957 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1958 | .recalc = &followparent_recalc, |
1959 | }; | |
1960 | ||
1961 | static struct clk omapctrl_ick = { | |
1962 | .name = "omapctrl_ick", | |
b36ee724 | 1963 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
1964 | .parent = &core_l4_ick, |
1965 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1966 | .enable_bit = OMAP3430_EN_OMAPCTRL_SHIFT, | |
44dc9d02 | 1967 | .flags = ENABLE_ON_INIT, |
b045d080 PW |
1968 | .recalc = &followparent_recalc, |
1969 | }; | |
1970 | ||
1971 | /* SSI_L4_ICK based clocks */ | |
1972 | ||
1973 | static struct clk ssi_l4_ick = { | |
1974 | .name = "ssi_l4_ick", | |
57137181 | 1975 | .ops = &clkops_null, |
b045d080 | 1976 | .parent = &l4_ick, |
333943ba | 1977 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1978 | .recalc = &followparent_recalc, |
1979 | }; | |
1980 | ||
3c82e229 | 1981 | static struct clk ssi_ick_3430es1 = { |
b045d080 | 1982 | .name = "ssi_ick", |
bc51da4e | 1983 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
1984 | .parent = &ssi_l4_ick, |
1985 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1986 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
333943ba | 1987 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
1988 | .recalc = &followparent_recalc, |
1989 | }; | |
1990 | ||
3c82e229 PW |
1991 | static struct clk ssi_ick_3430es2 = { |
1992 | .name = "ssi_ick", | |
1993 | .ops = &clkops_omap3430es2_ssi_wait, | |
1994 | .parent = &ssi_l4_ick, | |
1995 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
1996 | .enable_bit = OMAP3430_EN_SSI_SHIFT, | |
1997 | .clkdm_name = "core_l4_clkdm", | |
1998 | .recalc = &followparent_recalc, | |
1999 | }; | |
2000 | ||
b045d080 PW |
2001 | /* REVISIT: Technically the TRM claims that this is CORE_CLK based, |
2002 | * but l4_ick makes more sense to me */ | |
2003 | ||
2004 | static const struct clksel usb_l4_clksel[] = { | |
2005 | { .parent = &l4_ick, .rates = div2_rates }, | |
2006 | { .parent = NULL }, | |
2007 | }; | |
2008 | ||
2009 | static struct clk usb_l4_ick = { | |
2010 | .name = "usb_l4_ick", | |
b36ee724 | 2011 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2012 | .parent = &l4_ick, |
2013 | .init = &omap2_init_clksel_parent, | |
2014 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1), | |
2015 | .enable_bit = OMAP3430ES1_EN_FSHOSTUSB_SHIFT, | |
2016 | .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL), | |
2017 | .clksel_mask = OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK, | |
2018 | .clksel = usb_l4_clksel, | |
b045d080 PW |
2019 | .recalc = &omap2_clksel_recalc, |
2020 | }; | |
2021 | ||
b045d080 PW |
2022 | /* SECURITY_L4_ICK2 based clocks */ |
2023 | ||
2024 | static struct clk security_l4_ick2 = { | |
2025 | .name = "security_l4_ick2", | |
57137181 | 2026 | .ops = &clkops_null, |
b045d080 | 2027 | .parent = &l4_ick, |
b045d080 PW |
2028 | .recalc = &followparent_recalc, |
2029 | }; | |
2030 | ||
2031 | static struct clk aes1_ick = { | |
2032 | .name = "aes1_ick", | |
b36ee724 | 2033 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2034 | .parent = &security_l4_ick2, |
2035 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2036 | .enable_bit = OMAP3430_EN_AES1_SHIFT, | |
b045d080 PW |
2037 | .recalc = &followparent_recalc, |
2038 | }; | |
2039 | ||
2040 | static struct clk rng_ick = { | |
2041 | .name = "rng_ick", | |
b36ee724 | 2042 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2043 | .parent = &security_l4_ick2, |
2044 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2045 | .enable_bit = OMAP3430_EN_RNG_SHIFT, | |
b045d080 PW |
2046 | .recalc = &followparent_recalc, |
2047 | }; | |
2048 | ||
2049 | static struct clk sha11_ick = { | |
2050 | .name = "sha11_ick", | |
b36ee724 | 2051 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2052 | .parent = &security_l4_ick2, |
2053 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2054 | .enable_bit = OMAP3430_EN_SHA11_SHIFT, | |
b045d080 PW |
2055 | .recalc = &followparent_recalc, |
2056 | }; | |
2057 | ||
2058 | static struct clk des1_ick = { | |
2059 | .name = "des1_ick", | |
b36ee724 | 2060 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2061 | .parent = &security_l4_ick2, |
2062 | .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2), | |
2063 | .enable_bit = OMAP3430_EN_DES1_SHIFT, | |
b045d080 PW |
2064 | .recalc = &followparent_recalc, |
2065 | }; | |
2066 | ||
2067 | /* DSS */ | |
3c82e229 | 2068 | static struct clk dss1_alwon_fck_3430es1 = { |
b045d080 | 2069 | .name = "dss1_alwon_fck", |
bc51da4e | 2070 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2071 | .parent = &dpll4_m4x2_ck, |
2072 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2073 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
333943ba | 2074 | .clkdm_name = "dss_clkdm", |
c0bf3132 | 2075 | .recalc = &followparent_recalc, |
b045d080 PW |
2076 | }; |
2077 | ||
3c82e229 PW |
2078 | static struct clk dss1_alwon_fck_3430es2 = { |
2079 | .name = "dss1_alwon_fck", | |
2080 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | |
2081 | .parent = &dpll4_m4x2_ck, | |
2082 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), | |
2083 | .enable_bit = OMAP3430_EN_DSS1_SHIFT, | |
2084 | .clkdm_name = "dss_clkdm", | |
2085 | .recalc = &followparent_recalc, | |
2086 | }; | |
2087 | ||
b045d080 PW |
2088 | static struct clk dss_tv_fck = { |
2089 | .name = "dss_tv_fck", | |
bc51da4e | 2090 | .ops = &clkops_omap2_dflt, |
b045d080 | 2091 | .parent = &omap_54m_fck, |
333943ba | 2092 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2093 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2094 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
333943ba | 2095 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2096 | .recalc = &followparent_recalc, |
2097 | }; | |
2098 | ||
2099 | static struct clk dss_96m_fck = { | |
2100 | .name = "dss_96m_fck", | |
bc51da4e | 2101 | .ops = &clkops_omap2_dflt, |
b045d080 | 2102 | .parent = &omap_96m_fck, |
333943ba | 2103 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2104 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2105 | .enable_bit = OMAP3430_EN_TV_SHIFT, | |
333943ba | 2106 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2107 | .recalc = &followparent_recalc, |
2108 | }; | |
2109 | ||
2110 | static struct clk dss2_alwon_fck = { | |
2111 | .name = "dss2_alwon_fck", | |
bc51da4e | 2112 | .ops = &clkops_omap2_dflt, |
b045d080 | 2113 | .parent = &sys_ck, |
333943ba | 2114 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2115 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_FCLKEN), |
2116 | .enable_bit = OMAP3430_EN_DSS2_SHIFT, | |
333943ba | 2117 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2118 | .recalc = &followparent_recalc, |
2119 | }; | |
2120 | ||
3c82e229 | 2121 | static struct clk dss_ick_3430es1 = { |
b045d080 PW |
2122 | /* Handles both L3 and L4 clocks */ |
2123 | .name = "dss_ick", | |
bc51da4e | 2124 | .ops = &clkops_omap2_dflt, |
b045d080 | 2125 | .parent = &l4_ick, |
333943ba | 2126 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2127 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), |
2128 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
333943ba | 2129 | .clkdm_name = "dss_clkdm", |
b045d080 PW |
2130 | .recalc = &followparent_recalc, |
2131 | }; | |
2132 | ||
3c82e229 PW |
2133 | static struct clk dss_ick_3430es2 = { |
2134 | /* Handles both L3 and L4 clocks */ | |
2135 | .name = "dss_ick", | |
2136 | .ops = &clkops_omap3430es2_dss_usbhost_wait, | |
2137 | .parent = &l4_ick, | |
2138 | .init = &omap2_init_clk_clkdm, | |
2139 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_DSS_MOD, CM_ICLKEN), | |
2140 | .enable_bit = OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT, | |
2141 | .clkdm_name = "dss_clkdm", | |
2142 | .recalc = &followparent_recalc, | |
2143 | }; | |
2144 | ||
b045d080 PW |
2145 | /* CAM */ |
2146 | ||
2147 | static struct clk cam_mclk = { | |
2148 | .name = "cam_mclk", | |
9e53dd71 | 2149 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2150 | .parent = &dpll4_m5x2_ck, |
2151 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | |
2152 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
333943ba | 2153 | .clkdm_name = "cam_clkdm", |
c0bf3132 | 2154 | .recalc = &followparent_recalc, |
b045d080 PW |
2155 | }; |
2156 | ||
5955902f HJ |
2157 | static struct clk cam_ick = { |
2158 | /* Handles both L3 and L4 clocks */ | |
2159 | .name = "cam_ick", | |
9e53dd71 | 2160 | .ops = &clkops_omap2_dflt, |
b045d080 | 2161 | .parent = &l4_ick, |
333943ba | 2162 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2163 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_ICLKEN), |
2164 | .enable_bit = OMAP3430_EN_CAM_SHIFT, | |
333943ba | 2165 | .clkdm_name = "cam_clkdm", |
b045d080 PW |
2166 | .recalc = &followparent_recalc, |
2167 | }; | |
2168 | ||
6c8fe0b9 SA |
2169 | static struct clk csi2_96m_fck = { |
2170 | .name = "csi2_96m_fck", | |
9e53dd71 | 2171 | .ops = &clkops_omap2_dflt, |
6c8fe0b9 SA |
2172 | .parent = &core_96m_fck, |
2173 | .init = &omap2_init_clk_clkdm, | |
2174 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_CAM_MOD, CM_FCLKEN), | |
2175 | .enable_bit = OMAP3430_EN_CSI2_SHIFT, | |
2176 | .clkdm_name = "cam_clkdm", | |
2177 | .recalc = &followparent_recalc, | |
2178 | }; | |
2179 | ||
b045d080 PW |
2180 | /* USBHOST - 3430ES2 only */ |
2181 | ||
2182 | static struct clk usbhost_120m_fck = { | |
2183 | .name = "usbhost_120m_fck", | |
3c82e229 | 2184 | .ops = &clkops_omap2_dflt, |
c0bf3132 | 2185 | .parent = &dpll5_m2_ck, |
333943ba | 2186 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2187 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2188 | .enable_bit = OMAP3430ES2_EN_USBHOST2_SHIFT, | |
333943ba | 2189 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2190 | .recalc = &followparent_recalc, |
2191 | }; | |
2192 | ||
2193 | static struct clk usbhost_48m_fck = { | |
2194 | .name = "usbhost_48m_fck", | |
3c82e229 | 2195 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
b045d080 | 2196 | .parent = &omap_48m_fck, |
333943ba | 2197 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2198 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN), |
2199 | .enable_bit = OMAP3430ES2_EN_USBHOST1_SHIFT, | |
333943ba | 2200 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2201 | .recalc = &followparent_recalc, |
2202 | }; | |
2203 | ||
5955902f HJ |
2204 | static struct clk usbhost_ick = { |
2205 | /* Handles both L3 and L4 clocks */ | |
2206 | .name = "usbhost_ick", | |
3c82e229 | 2207 | .ops = &clkops_omap3430es2_dss_usbhost_wait, |
b045d080 | 2208 | .parent = &l4_ick, |
333943ba | 2209 | .init = &omap2_init_clk_clkdm, |
b045d080 PW |
2210 | .enable_reg = OMAP_CM_REGADDR(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN), |
2211 | .enable_bit = OMAP3430ES2_EN_USBHOST_SHIFT, | |
333943ba | 2212 | .clkdm_name = "usbhost_clkdm", |
b045d080 PW |
2213 | .recalc = &followparent_recalc, |
2214 | }; | |
2215 | ||
b045d080 PW |
2216 | /* WKUP */ |
2217 | ||
2218 | static const struct clksel_rate usim_96m_rates[] = { | |
2219 | { .div = 2, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2220 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2221 | { .div = 8, .val = 5, .flags = RATE_IN_343X }, | |
2222 | { .div = 10, .val = 6, .flags = RATE_IN_343X }, | |
2223 | { .div = 0 }, | |
2224 | }; | |
2225 | ||
2226 | static const struct clksel_rate usim_120m_rates[] = { | |
2227 | { .div = 4, .val = 7, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2228 | { .div = 8, .val = 8, .flags = RATE_IN_343X }, | |
2229 | { .div = 16, .val = 9, .flags = RATE_IN_343X }, | |
2230 | { .div = 20, .val = 10, .flags = RATE_IN_343X }, | |
2231 | { .div = 0 }, | |
2232 | }; | |
2233 | ||
2234 | static const struct clksel usim_clksel[] = { | |
2235 | { .parent = &omap_96m_fck, .rates = usim_96m_rates }, | |
c0bf3132 | 2236 | { .parent = &dpll5_m2_ck, .rates = usim_120m_rates }, |
b045d080 PW |
2237 | { .parent = &sys_ck, .rates = div2_rates }, |
2238 | { .parent = NULL }, | |
2239 | }; | |
2240 | ||
2241 | /* 3430ES2 only */ | |
2242 | static struct clk usim_fck = { | |
2243 | .name = "usim_fck", | |
b36ee724 | 2244 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2245 | .init = &omap2_init_clksel_parent, |
2246 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2247 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
2248 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2249 | .clksel_mask = OMAP3430ES2_CLKSEL_USIMOCP_MASK, | |
2250 | .clksel = usim_clksel, | |
b045d080 PW |
2251 | .recalc = &omap2_clksel_recalc, |
2252 | }; | |
2253 | ||
333943ba | 2254 | /* XXX should gpt1's clksel have wkup_32k_fck as the 32k opt? */ |
b045d080 PW |
2255 | static struct clk gpt1_fck = { |
2256 | .name = "gpt1_fck", | |
b36ee724 | 2257 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2258 | .init = &omap2_init_clksel_parent, |
2259 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2260 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
2261 | .clksel_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL), | |
2262 | .clksel_mask = OMAP3430_CLKSEL_GPT1_MASK, | |
2263 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2264 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2265 | .recalc = &omap2_clksel_recalc, |
2266 | }; | |
2267 | ||
2268 | static struct clk wkup_32k_fck = { | |
2269 | .name = "wkup_32k_fck", | |
897dcded | 2270 | .ops = &clkops_null, |
333943ba | 2271 | .init = &omap2_init_clk_clkdm, |
b045d080 | 2272 | .parent = &omap_32k_fck, |
333943ba | 2273 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2274 | .recalc = &followparent_recalc, |
2275 | }; | |
2276 | ||
89db9482 JH |
2277 | static struct clk gpio1_dbck = { |
2278 | .name = "gpio1_dbck", | |
6f733a34 | 2279 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2280 | .parent = &wkup_32k_fck, |
2281 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2282 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
333943ba | 2283 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2284 | .recalc = &followparent_recalc, |
2285 | }; | |
2286 | ||
2287 | static struct clk wdt2_fck = { | |
2288 | .name = "wdt2_fck", | |
b36ee724 | 2289 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2290 | .parent = &wkup_32k_fck, |
2291 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2292 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
333943ba | 2293 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2294 | .recalc = &followparent_recalc, |
2295 | }; | |
2296 | ||
2297 | static struct clk wkup_l4_ick = { | |
2298 | .name = "wkup_l4_ick", | |
897dcded | 2299 | .ops = &clkops_null, |
b045d080 | 2300 | .parent = &sys_ck, |
333943ba | 2301 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2302 | .recalc = &followparent_recalc, |
2303 | }; | |
2304 | ||
2305 | /* 3430ES2 only */ | |
2306 | /* Never specifically named in the TRM, so we have to infer a likely name */ | |
2307 | static struct clk usim_ick = { | |
2308 | .name = "usim_ick", | |
b36ee724 | 2309 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2310 | .parent = &wkup_l4_ick, |
2311 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2312 | .enable_bit = OMAP3430ES2_EN_USIMOCP_SHIFT, | |
333943ba | 2313 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2314 | .recalc = &followparent_recalc, |
2315 | }; | |
2316 | ||
2317 | static struct clk wdt2_ick = { | |
2318 | .name = "wdt2_ick", | |
b36ee724 | 2319 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2320 | .parent = &wkup_l4_ick, |
2321 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2322 | .enable_bit = OMAP3430_EN_WDT2_SHIFT, | |
333943ba | 2323 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2324 | .recalc = &followparent_recalc, |
2325 | }; | |
2326 | ||
2327 | static struct clk wdt1_ick = { | |
2328 | .name = "wdt1_ick", | |
b36ee724 | 2329 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2330 | .parent = &wkup_l4_ick, |
2331 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2332 | .enable_bit = OMAP3430_EN_WDT1_SHIFT, | |
333943ba | 2333 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2334 | .recalc = &followparent_recalc, |
2335 | }; | |
2336 | ||
2337 | static struct clk gpio1_ick = { | |
2338 | .name = "gpio1_ick", | |
b36ee724 | 2339 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2340 | .parent = &wkup_l4_ick, |
2341 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2342 | .enable_bit = OMAP3430_EN_GPIO1_SHIFT, | |
333943ba | 2343 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2344 | .recalc = &followparent_recalc, |
2345 | }; | |
2346 | ||
2347 | static struct clk omap_32ksync_ick = { | |
2348 | .name = "omap_32ksync_ick", | |
b36ee724 | 2349 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2350 | .parent = &wkup_l4_ick, |
2351 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2352 | .enable_bit = OMAP3430_EN_32KSYNC_SHIFT, | |
333943ba | 2353 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2354 | .recalc = &followparent_recalc, |
2355 | }; | |
2356 | ||
333943ba | 2357 | /* XXX This clock no longer exists in 3430 TRM rev F */ |
b045d080 PW |
2358 | static struct clk gpt12_ick = { |
2359 | .name = "gpt12_ick", | |
b36ee724 | 2360 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2361 | .parent = &wkup_l4_ick, |
2362 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2363 | .enable_bit = OMAP3430_EN_GPT12_SHIFT, | |
333943ba | 2364 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2365 | .recalc = &followparent_recalc, |
2366 | }; | |
2367 | ||
2368 | static struct clk gpt1_ick = { | |
2369 | .name = "gpt1_ick", | |
b36ee724 | 2370 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2371 | .parent = &wkup_l4_ick, |
2372 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN), | |
2373 | .enable_bit = OMAP3430_EN_GPT1_SHIFT, | |
333943ba | 2374 | .clkdm_name = "wkup_clkdm", |
b045d080 PW |
2375 | .recalc = &followparent_recalc, |
2376 | }; | |
2377 | ||
2378 | ||
2379 | ||
2380 | /* PER clock domain */ | |
2381 | ||
2382 | static struct clk per_96m_fck = { | |
2383 | .name = "per_96m_fck", | |
57137181 | 2384 | .ops = &clkops_null, |
b045d080 | 2385 | .parent = &omap_96m_alwon_fck, |
333943ba | 2386 | .init = &omap2_init_clk_clkdm, |
333943ba | 2387 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2388 | .recalc = &followparent_recalc, |
2389 | }; | |
2390 | ||
2391 | static struct clk per_48m_fck = { | |
2392 | .name = "per_48m_fck", | |
57137181 | 2393 | .ops = &clkops_null, |
b045d080 | 2394 | .parent = &omap_48m_fck, |
333943ba | 2395 | .init = &omap2_init_clk_clkdm, |
333943ba | 2396 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2397 | .recalc = &followparent_recalc, |
2398 | }; | |
2399 | ||
2400 | static struct clk uart3_fck = { | |
2401 | .name = "uart3_fck", | |
b36ee724 | 2402 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2403 | .parent = &per_48m_fck, |
2404 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2405 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
333943ba | 2406 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2407 | .recalc = &followparent_recalc, |
2408 | }; | |
2409 | ||
2410 | static struct clk gpt2_fck = { | |
2411 | .name = "gpt2_fck", | |
b36ee724 | 2412 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2413 | .init = &omap2_init_clksel_parent, |
2414 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2415 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
2416 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2417 | .clksel_mask = OMAP3430_CLKSEL_GPT2_MASK, | |
2418 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2419 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2420 | .recalc = &omap2_clksel_recalc, |
2421 | }; | |
2422 | ||
2423 | static struct clk gpt3_fck = { | |
2424 | .name = "gpt3_fck", | |
b36ee724 | 2425 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2426 | .init = &omap2_init_clksel_parent, |
2427 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2428 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
2429 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2430 | .clksel_mask = OMAP3430_CLKSEL_GPT3_MASK, | |
2431 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2432 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2433 | .recalc = &omap2_clksel_recalc, |
2434 | }; | |
2435 | ||
2436 | static struct clk gpt4_fck = { | |
2437 | .name = "gpt4_fck", | |
b36ee724 | 2438 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2439 | .init = &omap2_init_clksel_parent, |
2440 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2441 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
2442 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2443 | .clksel_mask = OMAP3430_CLKSEL_GPT4_MASK, | |
2444 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2445 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2446 | .recalc = &omap2_clksel_recalc, |
2447 | }; | |
2448 | ||
2449 | static struct clk gpt5_fck = { | |
2450 | .name = "gpt5_fck", | |
b36ee724 | 2451 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2452 | .init = &omap2_init_clksel_parent, |
2453 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2454 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
2455 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2456 | .clksel_mask = OMAP3430_CLKSEL_GPT5_MASK, | |
2457 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2458 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2459 | .recalc = &omap2_clksel_recalc, |
2460 | }; | |
2461 | ||
2462 | static struct clk gpt6_fck = { | |
2463 | .name = "gpt6_fck", | |
b36ee724 | 2464 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2465 | .init = &omap2_init_clksel_parent, |
2466 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2467 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
2468 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2469 | .clksel_mask = OMAP3430_CLKSEL_GPT6_MASK, | |
2470 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2471 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2472 | .recalc = &omap2_clksel_recalc, |
2473 | }; | |
2474 | ||
2475 | static struct clk gpt7_fck = { | |
2476 | .name = "gpt7_fck", | |
b36ee724 | 2477 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2478 | .init = &omap2_init_clksel_parent, |
2479 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2480 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
2481 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2482 | .clksel_mask = OMAP3430_CLKSEL_GPT7_MASK, | |
2483 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2484 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2485 | .recalc = &omap2_clksel_recalc, |
2486 | }; | |
2487 | ||
2488 | static struct clk gpt8_fck = { | |
2489 | .name = "gpt8_fck", | |
b36ee724 | 2490 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2491 | .init = &omap2_init_clksel_parent, |
2492 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2493 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
2494 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2495 | .clksel_mask = OMAP3430_CLKSEL_GPT8_MASK, | |
2496 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2497 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2498 | .recalc = &omap2_clksel_recalc, |
2499 | }; | |
2500 | ||
2501 | static struct clk gpt9_fck = { | |
2502 | .name = "gpt9_fck", | |
b36ee724 | 2503 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2504 | .init = &omap2_init_clksel_parent, |
2505 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2506 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
2507 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_CLKSEL), | |
2508 | .clksel_mask = OMAP3430_CLKSEL_GPT9_MASK, | |
2509 | .clksel = omap343x_gpt_clksel, | |
333943ba | 2510 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2511 | .recalc = &omap2_clksel_recalc, |
2512 | }; | |
2513 | ||
2514 | static struct clk per_32k_alwon_fck = { | |
2515 | .name = "per_32k_alwon_fck", | |
897dcded | 2516 | .ops = &clkops_null, |
b045d080 | 2517 | .parent = &omap_32k_fck, |
333943ba | 2518 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2519 | .recalc = &followparent_recalc, |
2520 | }; | |
2521 | ||
89db9482 JH |
2522 | static struct clk gpio6_dbck = { |
2523 | .name = "gpio6_dbck", | |
6f733a34 | 2524 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2525 | .parent = &per_32k_alwon_fck, |
2526 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2527 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, |
333943ba | 2528 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2529 | .recalc = &followparent_recalc, |
2530 | }; | |
2531 | ||
89db9482 JH |
2532 | static struct clk gpio5_dbck = { |
2533 | .name = "gpio5_dbck", | |
6f733a34 | 2534 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2535 | .parent = &per_32k_alwon_fck, |
2536 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2537 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, |
333943ba | 2538 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2539 | .recalc = &followparent_recalc, |
2540 | }; | |
2541 | ||
89db9482 JH |
2542 | static struct clk gpio4_dbck = { |
2543 | .name = "gpio4_dbck", | |
6f733a34 | 2544 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2545 | .parent = &per_32k_alwon_fck, |
2546 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2547 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, |
333943ba | 2548 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2549 | .recalc = &followparent_recalc, |
2550 | }; | |
2551 | ||
89db9482 JH |
2552 | static struct clk gpio3_dbck = { |
2553 | .name = "gpio3_dbck", | |
6f733a34 | 2554 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2555 | .parent = &per_32k_alwon_fck, |
2556 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2557 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, |
333943ba | 2558 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2559 | .recalc = &followparent_recalc, |
2560 | }; | |
2561 | ||
89db9482 JH |
2562 | static struct clk gpio2_dbck = { |
2563 | .name = "gpio2_dbck", | |
6f733a34 | 2564 | .ops = &clkops_omap2_dflt, |
b045d080 PW |
2565 | .parent = &per_32k_alwon_fck, |
2566 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
c3aa044a | 2567 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, |
333943ba | 2568 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2569 | .recalc = &followparent_recalc, |
2570 | }; | |
2571 | ||
2572 | static struct clk wdt3_fck = { | |
2573 | .name = "wdt3_fck", | |
b36ee724 | 2574 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2575 | .parent = &per_32k_alwon_fck, |
2576 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2577 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
333943ba | 2578 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2579 | .recalc = &followparent_recalc, |
2580 | }; | |
2581 | ||
2582 | static struct clk per_l4_ick = { | |
2583 | .name = "per_l4_ick", | |
57137181 | 2584 | .ops = &clkops_null, |
b045d080 | 2585 | .parent = &l4_ick, |
333943ba | 2586 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2587 | .recalc = &followparent_recalc, |
2588 | }; | |
2589 | ||
2590 | static struct clk gpio6_ick = { | |
2591 | .name = "gpio6_ick", | |
b36ee724 | 2592 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2593 | .parent = &per_l4_ick, |
2594 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2595 | .enable_bit = OMAP3430_EN_GPIO6_SHIFT, | |
333943ba | 2596 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2597 | .recalc = &followparent_recalc, |
2598 | }; | |
2599 | ||
2600 | static struct clk gpio5_ick = { | |
2601 | .name = "gpio5_ick", | |
b36ee724 | 2602 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2603 | .parent = &per_l4_ick, |
2604 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2605 | .enable_bit = OMAP3430_EN_GPIO5_SHIFT, | |
333943ba | 2606 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2607 | .recalc = &followparent_recalc, |
2608 | }; | |
2609 | ||
2610 | static struct clk gpio4_ick = { | |
2611 | .name = "gpio4_ick", | |
b36ee724 | 2612 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2613 | .parent = &per_l4_ick, |
2614 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2615 | .enable_bit = OMAP3430_EN_GPIO4_SHIFT, | |
333943ba | 2616 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2617 | .recalc = &followparent_recalc, |
2618 | }; | |
2619 | ||
2620 | static struct clk gpio3_ick = { | |
2621 | .name = "gpio3_ick", | |
b36ee724 | 2622 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2623 | .parent = &per_l4_ick, |
2624 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2625 | .enable_bit = OMAP3430_EN_GPIO3_SHIFT, | |
333943ba | 2626 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2627 | .recalc = &followparent_recalc, |
2628 | }; | |
2629 | ||
2630 | static struct clk gpio2_ick = { | |
2631 | .name = "gpio2_ick", | |
b36ee724 | 2632 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2633 | .parent = &per_l4_ick, |
2634 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2635 | .enable_bit = OMAP3430_EN_GPIO2_SHIFT, | |
333943ba | 2636 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2637 | .recalc = &followparent_recalc, |
2638 | }; | |
2639 | ||
2640 | static struct clk wdt3_ick = { | |
2641 | .name = "wdt3_ick", | |
b36ee724 | 2642 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2643 | .parent = &per_l4_ick, |
2644 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2645 | .enable_bit = OMAP3430_EN_WDT3_SHIFT, | |
333943ba | 2646 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2647 | .recalc = &followparent_recalc, |
2648 | }; | |
2649 | ||
2650 | static struct clk uart3_ick = { | |
2651 | .name = "uart3_ick", | |
b36ee724 | 2652 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2653 | .parent = &per_l4_ick, |
2654 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2655 | .enable_bit = OMAP3430_EN_UART3_SHIFT, | |
333943ba | 2656 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2657 | .recalc = &followparent_recalc, |
2658 | }; | |
2659 | ||
2660 | static struct clk gpt9_ick = { | |
2661 | .name = "gpt9_ick", | |
b36ee724 | 2662 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2663 | .parent = &per_l4_ick, |
2664 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2665 | .enable_bit = OMAP3430_EN_GPT9_SHIFT, | |
333943ba | 2666 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2667 | .recalc = &followparent_recalc, |
2668 | }; | |
2669 | ||
2670 | static struct clk gpt8_ick = { | |
2671 | .name = "gpt8_ick", | |
b36ee724 | 2672 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2673 | .parent = &per_l4_ick, |
2674 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2675 | .enable_bit = OMAP3430_EN_GPT8_SHIFT, | |
333943ba | 2676 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2677 | .recalc = &followparent_recalc, |
2678 | }; | |
2679 | ||
2680 | static struct clk gpt7_ick = { | |
2681 | .name = "gpt7_ick", | |
b36ee724 | 2682 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2683 | .parent = &per_l4_ick, |
2684 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2685 | .enable_bit = OMAP3430_EN_GPT7_SHIFT, | |
333943ba | 2686 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2687 | .recalc = &followparent_recalc, |
2688 | }; | |
2689 | ||
2690 | static struct clk gpt6_ick = { | |
2691 | .name = "gpt6_ick", | |
b36ee724 | 2692 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2693 | .parent = &per_l4_ick, |
2694 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2695 | .enable_bit = OMAP3430_EN_GPT6_SHIFT, | |
333943ba | 2696 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2697 | .recalc = &followparent_recalc, |
2698 | }; | |
2699 | ||
2700 | static struct clk gpt5_ick = { | |
2701 | .name = "gpt5_ick", | |
b36ee724 | 2702 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2703 | .parent = &per_l4_ick, |
2704 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2705 | .enable_bit = OMAP3430_EN_GPT5_SHIFT, | |
333943ba | 2706 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2707 | .recalc = &followparent_recalc, |
2708 | }; | |
2709 | ||
2710 | static struct clk gpt4_ick = { | |
2711 | .name = "gpt4_ick", | |
b36ee724 | 2712 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2713 | .parent = &per_l4_ick, |
2714 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2715 | .enable_bit = OMAP3430_EN_GPT4_SHIFT, | |
333943ba | 2716 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2717 | .recalc = &followparent_recalc, |
2718 | }; | |
2719 | ||
2720 | static struct clk gpt3_ick = { | |
2721 | .name = "gpt3_ick", | |
b36ee724 | 2722 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2723 | .parent = &per_l4_ick, |
2724 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2725 | .enable_bit = OMAP3430_EN_GPT3_SHIFT, | |
333943ba | 2726 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2727 | .recalc = &followparent_recalc, |
2728 | }; | |
2729 | ||
2730 | static struct clk gpt2_ick = { | |
2731 | .name = "gpt2_ick", | |
b36ee724 | 2732 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2733 | .parent = &per_l4_ick, |
2734 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2735 | .enable_bit = OMAP3430_EN_GPT2_SHIFT, | |
333943ba | 2736 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2737 | .recalc = &followparent_recalc, |
2738 | }; | |
2739 | ||
2740 | static struct clk mcbsp2_ick = { | |
78673bc8 | 2741 | .name = "mcbsp_ick", |
b36ee724 | 2742 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 2743 | .id = 2, |
b045d080 PW |
2744 | .parent = &per_l4_ick, |
2745 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2746 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
333943ba | 2747 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2748 | .recalc = &followparent_recalc, |
2749 | }; | |
2750 | ||
2751 | static struct clk mcbsp3_ick = { | |
78673bc8 | 2752 | .name = "mcbsp_ick", |
b36ee724 | 2753 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 2754 | .id = 3, |
b045d080 PW |
2755 | .parent = &per_l4_ick, |
2756 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2757 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
333943ba | 2758 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2759 | .recalc = &followparent_recalc, |
2760 | }; | |
2761 | ||
2762 | static struct clk mcbsp4_ick = { | |
78673bc8 | 2763 | .name = "mcbsp_ick", |
b36ee724 | 2764 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 2765 | .id = 4, |
b045d080 PW |
2766 | .parent = &per_l4_ick, |
2767 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_ICLKEN), | |
2768 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
333943ba | 2769 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2770 | .recalc = &followparent_recalc, |
2771 | }; | |
2772 | ||
2773 | static const struct clksel mcbsp_234_clksel[] = { | |
9cfd985e PW |
2774 | { .parent = &core_96m_fck, .rates = common_mcbsp_96m_rates }, |
2775 | { .parent = &mcbsp_clks, .rates = common_mcbsp_mcbsp_rates }, | |
b045d080 PW |
2776 | { .parent = NULL } |
2777 | }; | |
2778 | ||
2779 | static struct clk mcbsp2_fck = { | |
78673bc8 | 2780 | .name = "mcbsp_fck", |
b36ee724 | 2781 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 2782 | .id = 2, |
b045d080 PW |
2783 | .init = &omap2_init_clksel_parent, |
2784 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2785 | .enable_bit = OMAP3430_EN_MCBSP2_SHIFT, | |
2786 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0), | |
2787 | .clksel_mask = OMAP2_MCBSP2_CLKS_MASK, | |
2788 | .clksel = mcbsp_234_clksel, | |
333943ba | 2789 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2790 | .recalc = &omap2_clksel_recalc, |
2791 | }; | |
2792 | ||
2793 | static struct clk mcbsp3_fck = { | |
78673bc8 | 2794 | .name = "mcbsp_fck", |
b36ee724 | 2795 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 2796 | .id = 3, |
b045d080 PW |
2797 | .init = &omap2_init_clksel_parent, |
2798 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2799 | .enable_bit = OMAP3430_EN_MCBSP3_SHIFT, | |
2800 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2801 | .clksel_mask = OMAP2_MCBSP3_CLKS_MASK, | |
2802 | .clksel = mcbsp_234_clksel, | |
333943ba | 2803 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2804 | .recalc = &omap2_clksel_recalc, |
2805 | }; | |
2806 | ||
2807 | static struct clk mcbsp4_fck = { | |
78673bc8 | 2808 | .name = "mcbsp_fck", |
b36ee724 | 2809 | .ops = &clkops_omap2_dflt_wait, |
78673bc8 | 2810 | .id = 4, |
b045d080 PW |
2811 | .init = &omap2_init_clksel_parent, |
2812 | .enable_reg = OMAP_CM_REGADDR(OMAP3430_PER_MOD, CM_FCLKEN), | |
2813 | .enable_bit = OMAP3430_EN_MCBSP4_SHIFT, | |
2814 | .clksel_reg = OMAP343X_CTRL_REGADDR(OMAP343X_CONTROL_DEVCONF1), | |
2815 | .clksel_mask = OMAP2_MCBSP4_CLKS_MASK, | |
2816 | .clksel = mcbsp_234_clksel, | |
333943ba | 2817 | .clkdm_name = "per_clkdm", |
b045d080 PW |
2818 | .recalc = &omap2_clksel_recalc, |
2819 | }; | |
2820 | ||
2821 | /* EMU clocks */ | |
2822 | ||
2823 | /* More information: ARM Cortex-A8 Technical Reference Manual, sect 10.1 */ | |
2824 | ||
2825 | static const struct clksel_rate emu_src_sys_rates[] = { | |
2826 | { .div = 1, .val = 0, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2827 | { .div = 0 }, | |
2828 | }; | |
2829 | ||
2830 | static const struct clksel_rate emu_src_core_rates[] = { | |
2831 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2832 | { .div = 0 }, | |
2833 | }; | |
2834 | ||
2835 | static const struct clksel_rate emu_src_per_rates[] = { | |
2836 | { .div = 1, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2837 | { .div = 0 }, | |
2838 | }; | |
2839 | ||
2840 | static const struct clksel_rate emu_src_mpu_rates[] = { | |
2841 | { .div = 1, .val = 3, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2842 | { .div = 0 }, | |
2843 | }; | |
2844 | ||
2845 | static const struct clksel emu_src_clksel[] = { | |
2846 | { .parent = &sys_ck, .rates = emu_src_sys_rates }, | |
2847 | { .parent = &emu_core_alwon_ck, .rates = emu_src_core_rates }, | |
2848 | { .parent = &emu_per_alwon_ck, .rates = emu_src_per_rates }, | |
2849 | { .parent = &emu_mpu_alwon_ck, .rates = emu_src_mpu_rates }, | |
2850 | { .parent = NULL }, | |
2851 | }; | |
2852 | ||
2853 | /* | |
2854 | * Like the clkout_src clocks, emu_src_clk is a virtual clock, existing only | |
2855 | * to switch the source of some of the EMU clocks. | |
2856 | * XXX Are there CLKEN bits for these EMU clks? | |
2857 | */ | |
2858 | static struct clk emu_src_ck = { | |
2859 | .name = "emu_src_ck", | |
897dcded | 2860 | .ops = &clkops_null, |
b045d080 PW |
2861 | .init = &omap2_init_clksel_parent, |
2862 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2863 | .clksel_mask = OMAP3430_MUX_CTRL_MASK, | |
2864 | .clksel = emu_src_clksel, | |
333943ba | 2865 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2866 | .recalc = &omap2_clksel_recalc, |
2867 | }; | |
2868 | ||
2869 | static const struct clksel_rate pclk_emu_rates[] = { | |
2870 | { .div = 2, .val = 2, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2871 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2872 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2873 | { .div = 6, .val = 6, .flags = RATE_IN_343X }, | |
2874 | { .div = 0 }, | |
2875 | }; | |
2876 | ||
2877 | static const struct clksel pclk_emu_clksel[] = { | |
2878 | { .parent = &emu_src_ck, .rates = pclk_emu_rates }, | |
2879 | { .parent = NULL }, | |
2880 | }; | |
2881 | ||
2882 | static struct clk pclk_fck = { | |
2883 | .name = "pclk_fck", | |
897dcded | 2884 | .ops = &clkops_null, |
b045d080 PW |
2885 | .init = &omap2_init_clksel_parent, |
2886 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2887 | .clksel_mask = OMAP3430_CLKSEL_PCLK_MASK, | |
2888 | .clksel = pclk_emu_clksel, | |
333943ba | 2889 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2890 | .recalc = &omap2_clksel_recalc, |
2891 | }; | |
2892 | ||
2893 | static const struct clksel_rate pclkx2_emu_rates[] = { | |
2894 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2895 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2896 | { .div = 3, .val = 3, .flags = RATE_IN_343X }, | |
2897 | { .div = 0 }, | |
2898 | }; | |
2899 | ||
2900 | static const struct clksel pclkx2_emu_clksel[] = { | |
2901 | { .parent = &emu_src_ck, .rates = pclkx2_emu_rates }, | |
2902 | { .parent = NULL }, | |
2903 | }; | |
2904 | ||
2905 | static struct clk pclkx2_fck = { | |
2906 | .name = "pclkx2_fck", | |
897dcded | 2907 | .ops = &clkops_null, |
b045d080 PW |
2908 | .init = &omap2_init_clksel_parent, |
2909 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2910 | .clksel_mask = OMAP3430_CLKSEL_PCLKX2_MASK, | |
2911 | .clksel = pclkx2_emu_clksel, | |
333943ba | 2912 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2913 | .recalc = &omap2_clksel_recalc, |
2914 | }; | |
2915 | ||
2916 | static const struct clksel atclk_emu_clksel[] = { | |
2917 | { .parent = &emu_src_ck, .rates = div2_rates }, | |
2918 | { .parent = NULL }, | |
2919 | }; | |
2920 | ||
2921 | static struct clk atclk_fck = { | |
2922 | .name = "atclk_fck", | |
897dcded | 2923 | .ops = &clkops_null, |
b045d080 PW |
2924 | .init = &omap2_init_clksel_parent, |
2925 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2926 | .clksel_mask = OMAP3430_CLKSEL_ATCLK_MASK, | |
2927 | .clksel = atclk_emu_clksel, | |
333943ba | 2928 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2929 | .recalc = &omap2_clksel_recalc, |
2930 | }; | |
2931 | ||
2932 | static struct clk traceclk_src_fck = { | |
2933 | .name = "traceclk_src_fck", | |
897dcded | 2934 | .ops = &clkops_null, |
b045d080 PW |
2935 | .init = &omap2_init_clksel_parent, |
2936 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2937 | .clksel_mask = OMAP3430_TRACE_MUX_CTRL_MASK, | |
2938 | .clksel = emu_src_clksel, | |
333943ba | 2939 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2940 | .recalc = &omap2_clksel_recalc, |
2941 | }; | |
2942 | ||
2943 | static const struct clksel_rate traceclk_rates[] = { | |
2944 | { .div = 1, .val = 1, .flags = RATE_IN_343X | DEFAULT_RATE }, | |
2945 | { .div = 2, .val = 2, .flags = RATE_IN_343X }, | |
2946 | { .div = 4, .val = 4, .flags = RATE_IN_343X }, | |
2947 | { .div = 0 }, | |
2948 | }; | |
2949 | ||
2950 | static const struct clksel traceclk_clksel[] = { | |
2951 | { .parent = &traceclk_src_fck, .rates = traceclk_rates }, | |
2952 | { .parent = NULL }, | |
2953 | }; | |
2954 | ||
2955 | static struct clk traceclk_fck = { | |
2956 | .name = "traceclk_fck", | |
897dcded | 2957 | .ops = &clkops_null, |
b045d080 PW |
2958 | .init = &omap2_init_clksel_parent, |
2959 | .clksel_reg = OMAP_CM_REGADDR(OMAP3430_EMU_MOD, CM_CLKSEL1), | |
2960 | .clksel_mask = OMAP3430_CLKSEL_TRACECLK_MASK, | |
2961 | .clksel = traceclk_clksel, | |
333943ba | 2962 | .clkdm_name = "emu_clkdm", |
b045d080 PW |
2963 | .recalc = &omap2_clksel_recalc, |
2964 | }; | |
2965 | ||
2966 | /* SR clocks */ | |
2967 | ||
2968 | /* SmartReflex fclk (VDD1) */ | |
2969 | static struct clk sr1_fck = { | |
2970 | .name = "sr1_fck", | |
b36ee724 | 2971 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2972 | .parent = &sys_ck, |
2973 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2974 | .enable_bit = OMAP3430_EN_SR1_SHIFT, | |
b045d080 PW |
2975 | .recalc = &followparent_recalc, |
2976 | }; | |
2977 | ||
2978 | /* SmartReflex fclk (VDD2) */ | |
2979 | static struct clk sr2_fck = { | |
2980 | .name = "sr2_fck", | |
b36ee724 | 2981 | .ops = &clkops_omap2_dflt_wait, |
b045d080 PW |
2982 | .parent = &sys_ck, |
2983 | .enable_reg = OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN), | |
2984 | .enable_bit = OMAP3430_EN_SR2_SHIFT, | |
b045d080 PW |
2985 | .recalc = &followparent_recalc, |
2986 | }; | |
2987 | ||
2988 | static struct clk sr_l4_ick = { | |
2989 | .name = "sr_l4_ick", | |
897dcded | 2990 | .ops = &clkops_null, /* RMK: missing? */ |
b045d080 | 2991 | .parent = &l4_ick, |
333943ba | 2992 | .clkdm_name = "core_l4_clkdm", |
b045d080 PW |
2993 | .recalc = &followparent_recalc, |
2994 | }; | |
2995 | ||
2996 | /* SECURE_32K_FCK clocks */ | |
2997 | ||
2998 | static struct clk gpt12_fck = { | |
2999 | .name = "gpt12_fck", | |
897dcded | 3000 | .ops = &clkops_null, |
b045d080 | 3001 | .parent = &secure_32k_fck, |
b045d080 PW |
3002 | .recalc = &followparent_recalc, |
3003 | }; | |
3004 | ||
3005 | static struct clk wdt1_fck = { | |
3006 | .name = "wdt1_fck", | |
897dcded | 3007 | .ops = &clkops_null, |
b045d080 | 3008 | .parent = &secure_32k_fck, |
44dc9d02 | 3009 | .recalc = &followparent_recalc, |
b045d080 PW |
3010 | }; |
3011 | ||
3012 | #endif |