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046d6b28 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.c | |
3 | * | |
a16e9703 TL |
4 | * Copyright (C) 2005-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2008 Nokia Corporation | |
046d6b28 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
9 | * Paul Walmsley | |
046d6b28 | 10 | * |
a16e9703 TL |
11 | * Based on earlier work by Tuukka Tikkanen, Tony Lindgren, |
12 | * Gordon McNutt and RidgeRun, Inc. | |
046d6b28 TL |
13 | * |
14 | * This program is free software; you can redistribute it and/or modify | |
15 | * it under the terms of the GNU General Public License version 2 as | |
16 | * published by the Free Software Foundation. | |
17 | */ | |
6b8858a9 PW |
18 | #undef DEBUG |
19 | ||
046d6b28 TL |
20 | #include <linux/module.h> |
21 | #include <linux/kernel.h> | |
22 | #include <linux/device.h> | |
23 | #include <linux/list.h> | |
24 | #include <linux/errno.h> | |
25 | #include <linux/delay.h> | |
f8ce2547 | 26 | #include <linux/clk.h> |
6b8858a9 PW |
27 | #include <linux/io.h> |
28 | #include <linux/cpufreq.h> | |
fbd3bdb2 | 29 | #include <linux/bitops.h> |
046d6b28 | 30 | |
a09e64fb RK |
31 | #include <mach/clock.h> |
32 | #include <mach/sram.h> | |
3dc21975 | 33 | #include <mach/prcm.h> |
76631486 | 34 | #include <asm/div64.h> |
8ad8ff65 | 35 | #include <asm/clkdev.h> |
046d6b28 | 36 | |
f8de9b2c | 37 | #include <mach/sdrc.h> |
6b8858a9 | 38 | #include "clock.h" |
6b8858a9 PW |
39 | #include "prm.h" |
40 | #include "prm-regbits-24xx.h" | |
41 | #include "cm.h" | |
42 | #include "cm-regbits-24xx.h" | |
046d6b28 | 43 | |
548d8495 RK |
44 | static const struct clkops clkops_oscck; |
45 | static const struct clkops clkops_fixed; | |
46 | ||
3dc21975 PW |
47 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, |
48 | void __iomem **idlest_reg, | |
49 | u8 *idlest_bit); | |
50 | ||
51 | /* 2430 I2CHS has non-standard IDLEST register */ | |
52 | static const struct clkops clkops_omap2430_i2chs_wait = { | |
53 | .enable = omap2_dflt_clk_enable, | |
54 | .disable = omap2_dflt_clk_disable, | |
55 | .find_idlest = omap2430_clk_i2chs_find_idlest, | |
56 | .find_companion = omap2_clk_dflt_find_companion, | |
57 | }; | |
58 | ||
548d8495 RK |
59 | #include "clock24xx.h" |
60 | ||
8ad8ff65 RK |
61 | struct omap_clk { |
62 | u32 cpu; | |
63 | struct clk_lookup lk; | |
64 | }; | |
65 | ||
66 | #define CLK(dev, con, ck, cp) \ | |
67 | { \ | |
68 | .cpu = cp, \ | |
69 | .lk = { \ | |
70 | .dev_id = dev, \ | |
71 | .con_id = con, \ | |
72 | .clk = ck, \ | |
73 | }, \ | |
74 | } | |
75 | ||
15ca78f7 PW |
76 | #define CK_243X RATE_IN_243X |
77 | #define CK_242X RATE_IN_242X | |
8ad8ff65 RK |
78 | |
79 | static struct omap_clk omap24xx_clks[] = { | |
80 | /* external root sources */ | |
81 | CLK(NULL, "func_32k_ck", &func_32k_ck, CK_243X | CK_242X), | |
f248076c | 82 | CLK(NULL, "secure_32k_ck", &secure_32k_ck, CK_243X | CK_242X), |
8ad8ff65 RK |
83 | CLK(NULL, "osc_ck", &osc_ck, CK_243X | CK_242X), |
84 | CLK(NULL, "sys_ck", &sys_ck, CK_243X | CK_242X), | |
85 | CLK(NULL, "alt_ck", &alt_ck, CK_243X | CK_242X), | |
86 | /* internal analog sources */ | |
87 | CLK(NULL, "dpll_ck", &dpll_ck, CK_243X | CK_242X), | |
88 | CLK(NULL, "apll96_ck", &apll96_ck, CK_243X | CK_242X), | |
89 | CLK(NULL, "apll54_ck", &apll54_ck, CK_243X | CK_242X), | |
90 | /* internal prcm root sources */ | |
91 | CLK(NULL, "func_54m_ck", &func_54m_ck, CK_243X | CK_242X), | |
92 | CLK(NULL, "core_ck", &core_ck, CK_243X | CK_242X), | |
93 | CLK(NULL, "func_96m_ck", &func_96m_ck, CK_243X | CK_242X), | |
94 | CLK(NULL, "func_48m_ck", &func_48m_ck, CK_243X | CK_242X), | |
95 | CLK(NULL, "func_12m_ck", &func_12m_ck, CK_243X | CK_242X), | |
96 | CLK(NULL, "ck_wdt1_osc", &wdt1_osc_ck, CK_243X | CK_242X), | |
97 | CLK(NULL, "sys_clkout_src", &sys_clkout_src, CK_243X | CK_242X), | |
98 | CLK(NULL, "sys_clkout", &sys_clkout, CK_243X | CK_242X), | |
99 | CLK(NULL, "sys_clkout2_src", &sys_clkout2_src, CK_242X), | |
100 | CLK(NULL, "sys_clkout2", &sys_clkout2, CK_242X), | |
101 | CLK(NULL, "emul_ck", &emul_ck, CK_242X), | |
102 | /* mpu domain clocks */ | |
103 | CLK(NULL, "mpu_ck", &mpu_ck, CK_243X | CK_242X), | |
104 | /* dsp domain clocks */ | |
105 | CLK(NULL, "dsp_fck", &dsp_fck, CK_243X | CK_242X), | |
106 | CLK(NULL, "dsp_irate_ick", &dsp_irate_ick, CK_243X | CK_242X), | |
107 | CLK(NULL, "dsp_ick", &dsp_ick, CK_242X), | |
108 | CLK(NULL, "iva2_1_ick", &iva2_1_ick, CK_243X), | |
109 | CLK(NULL, "iva1_ifck", &iva1_ifck, CK_242X), | |
110 | CLK(NULL, "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X), | |
111 | /* GFX domain clocks */ | |
112 | CLK(NULL, "gfx_3d_fck", &gfx_3d_fck, CK_243X | CK_242X), | |
113 | CLK(NULL, "gfx_2d_fck", &gfx_2d_fck, CK_243X | CK_242X), | |
114 | CLK(NULL, "gfx_ick", &gfx_ick, CK_243X | CK_242X), | |
115 | /* Modem domain clocks */ | |
116 | CLK(NULL, "mdm_ick", &mdm_ick, CK_243X), | |
117 | CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X), | |
118 | /* DSS domain clocks */ | |
005187ee TL |
119 | CLK("omapfb", "ick", &dss_ick, CK_243X | CK_242X), |
120 | CLK("omapfb", "dss1_fck", &dss1_fck, CK_243X | CK_242X), | |
121 | CLK("omapfb", "dss2_fck", &dss2_fck, CK_243X | CK_242X), | |
122 | CLK("omapfb", "tv_fck", &dss_54m_fck, CK_243X | CK_242X), | |
8ad8ff65 RK |
123 | /* L3 domain clocks */ |
124 | CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X | CK_242X), | |
125 | CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X | CK_242X), | |
126 | CLK(NULL, "usb_l4_ick", &usb_l4_ick, CK_243X | CK_242X), | |
127 | /* L4 domain clocks */ | |
128 | CLK(NULL, "l4_ck", &l4_ck, CK_243X | CK_242X), | |
9299fd85 | 129 | CLK(NULL, "ssi_l4_ick", &ssi_l4_ick, CK_243X | CK_242X), |
8ad8ff65 RK |
130 | /* virtual meta-group clock */ |
131 | CLK(NULL, "virt_prcm_set", &virt_prcm_set, CK_243X | CK_242X), | |
132 | /* general l4 interface ck, multi-parent functional clk */ | |
133 | CLK(NULL, "gpt1_ick", &gpt1_ick, CK_243X | CK_242X), | |
134 | CLK(NULL, "gpt1_fck", &gpt1_fck, CK_243X | CK_242X), | |
135 | CLK(NULL, "gpt2_ick", &gpt2_ick, CK_243X | CK_242X), | |
136 | CLK(NULL, "gpt2_fck", &gpt2_fck, CK_243X | CK_242X), | |
137 | CLK(NULL, "gpt3_ick", &gpt3_ick, CK_243X | CK_242X), | |
138 | CLK(NULL, "gpt3_fck", &gpt3_fck, CK_243X | CK_242X), | |
139 | CLK(NULL, "gpt4_ick", &gpt4_ick, CK_243X | CK_242X), | |
140 | CLK(NULL, "gpt4_fck", &gpt4_fck, CK_243X | CK_242X), | |
141 | CLK(NULL, "gpt5_ick", &gpt5_ick, CK_243X | CK_242X), | |
142 | CLK(NULL, "gpt5_fck", &gpt5_fck, CK_243X | CK_242X), | |
143 | CLK(NULL, "gpt6_ick", &gpt6_ick, CK_243X | CK_242X), | |
144 | CLK(NULL, "gpt6_fck", &gpt6_fck, CK_243X | CK_242X), | |
145 | CLK(NULL, "gpt7_ick", &gpt7_ick, CK_243X | CK_242X), | |
146 | CLK(NULL, "gpt7_fck", &gpt7_fck, CK_243X | CK_242X), | |
147 | CLK(NULL, "gpt8_ick", &gpt8_ick, CK_243X | CK_242X), | |
148 | CLK(NULL, "gpt8_fck", &gpt8_fck, CK_243X | CK_242X), | |
149 | CLK(NULL, "gpt9_ick", &gpt9_ick, CK_243X | CK_242X), | |
150 | CLK(NULL, "gpt9_fck", &gpt9_fck, CK_243X | CK_242X), | |
151 | CLK(NULL, "gpt10_ick", &gpt10_ick, CK_243X | CK_242X), | |
152 | CLK(NULL, "gpt10_fck", &gpt10_fck, CK_243X | CK_242X), | |
153 | CLK(NULL, "gpt11_ick", &gpt11_ick, CK_243X | CK_242X), | |
154 | CLK(NULL, "gpt11_fck", &gpt11_fck, CK_243X | CK_242X), | |
155 | CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X | CK_242X), | |
156 | CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X | CK_242X), | |
b820ce4e RK |
157 | CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X | CK_242X), |
158 | CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X | CK_242X), | |
159 | CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X | CK_242X), | |
160 | CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X | CK_242X), | |
161 | CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X), | |
162 | CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X), | |
163 | CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X), | |
164 | CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X), | |
165 | CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X), | |
166 | CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X), | |
1b5715ec RK |
167 | CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X | CK_242X), |
168 | CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X | CK_242X), | |
169 | CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X | CK_242X), | |
170 | CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X | CK_242X), | |
171 | CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X), | |
172 | CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X), | |
8ad8ff65 RK |
173 | CLK(NULL, "uart1_ick", &uart1_ick, CK_243X | CK_242X), |
174 | CLK(NULL, "uart1_fck", &uart1_fck, CK_243X | CK_242X), | |
175 | CLK(NULL, "uart2_ick", &uart2_ick, CK_243X | CK_242X), | |
176 | CLK(NULL, "uart2_fck", &uart2_fck, CK_243X | CK_242X), | |
177 | CLK(NULL, "uart3_ick", &uart3_ick, CK_243X | CK_242X), | |
178 | CLK(NULL, "uart3_fck", &uart3_fck, CK_243X | CK_242X), | |
179 | CLK(NULL, "gpios_ick", &gpios_ick, CK_243X | CK_242X), | |
180 | CLK(NULL, "gpios_fck", &gpios_fck, CK_243X | CK_242X), | |
39a80c7f RK |
181 | CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X | CK_242X), |
182 | CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X | CK_242X), | |
8ad8ff65 RK |
183 | CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X | CK_242X), |
184 | CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X | CK_242X), | |
185 | CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X | CK_242X), | |
186 | CLK(NULL, "icr_ick", &icr_ick, CK_243X), | |
6c5dbb40 RK |
187 | CLK("omap24xxcam", "fck", &cam_fck, CK_243X | CK_242X), |
188 | CLK("omap24xxcam", "ick", &cam_ick, CK_243X | CK_242X), | |
8ad8ff65 RK |
189 | CLK(NULL, "mailboxes_ick", &mailboxes_ick, CK_243X | CK_242X), |
190 | CLK(NULL, "wdt4_ick", &wdt4_ick, CK_243X | CK_242X), | |
191 | CLK(NULL, "wdt4_fck", &wdt4_fck, CK_243X | CK_242X), | |
192 | CLK(NULL, "wdt3_ick", &wdt3_ick, CK_242X), | |
193 | CLK(NULL, "wdt3_fck", &wdt3_fck, CK_242X), | |
194 | CLK(NULL, "mspro_ick", &mspro_ick, CK_243X | CK_242X), | |
195 | CLK(NULL, "mspro_fck", &mspro_fck, CK_243X | CK_242X), | |
5c9e02b1 RK |
196 | CLK("mmci-omap.0", "ick", &mmc_ick, CK_242X), |
197 | CLK("mmci-omap.0", "fck", &mmc_fck, CK_242X), | |
8ad8ff65 RK |
198 | CLK(NULL, "fac_ick", &fac_ick, CK_243X | CK_242X), |
199 | CLK(NULL, "fac_fck", &fac_fck, CK_243X | CK_242X), | |
200 | CLK(NULL, "eac_ick", &eac_ick, CK_242X), | |
201 | CLK(NULL, "eac_fck", &eac_fck, CK_242X), | |
cc51c9d4 RK |
202 | CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X | CK_242X), |
203 | CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X | CK_242X), | |
1d14de08 RK |
204 | CLK("i2c_omap.1", "ick", &i2c1_ick, CK_243X | CK_242X), |
205 | CLK("i2c_omap.1", "fck", &i2c1_fck, CK_242X), | |
206 | CLK("i2c_omap.1", "fck", &i2chs1_fck, CK_243X), | |
207 | CLK("i2c_omap.2", "ick", &i2c2_ick, CK_243X | CK_242X), | |
208 | CLK("i2c_omap.2", "fck", &i2c2_fck, CK_242X), | |
209 | CLK("i2c_omap.2", "fck", &i2chs2_fck, CK_243X), | |
8ad8ff65 RK |
210 | CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X | CK_242X), |
211 | CLK(NULL, "sdma_fck", &sdma_fck, CK_243X | CK_242X), | |
212 | CLK(NULL, "sdma_ick", &sdma_ick, CK_243X | CK_242X), | |
213 | CLK(NULL, "vlynq_ick", &vlynq_ick, CK_242X), | |
214 | CLK(NULL, "vlynq_fck", &vlynq_fck, CK_242X), | |
215 | CLK(NULL, "sdrc_ick", &sdrc_ick, CK_243X), | |
216 | CLK(NULL, "des_ick", &des_ick, CK_243X | CK_242X), | |
217 | CLK(NULL, "sha_ick", &sha_ick, CK_243X | CK_242X), | |
eeec7c8d | 218 | CLK("omap_rng", "ick", &rng_ick, CK_243X | CK_242X), |
8ad8ff65 RK |
219 | CLK(NULL, "aes_ick", &aes_ick, CK_243X | CK_242X), |
220 | CLK(NULL, "pka_ick", &pka_ick, CK_243X | CK_242X), | |
221 | CLK(NULL, "usb_fck", &usb_fck, CK_243X | CK_242X), | |
4ea60b0c | 222 | CLK("musb_hdrc", "ick", &usbhs_ick, CK_243X), |
6f7607cc RK |
223 | CLK("mmci-omap-hs.0", "ick", &mmchs1_ick, CK_243X), |
224 | CLK("mmci-omap-hs.0", "fck", &mmchs1_fck, CK_243X), | |
225 | CLK("mmci-omap-hs.1", "ick", &mmchs2_ick, CK_243X), | |
226 | CLK("mmci-omap-hs.1", "fck", &mmchs2_fck, CK_243X), | |
8ad8ff65 RK |
227 | CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X), |
228 | CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X), | |
229 | CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X), | |
230 | CLK("mmci-omap-hs.0", "mmchsdb_fck", &mmchsdb1_fck, CK_243X), | |
231 | CLK("mmci-omap-hs.1", "mmchsdb_fck", &mmchsdb2_fck, CK_243X), | |
232 | }; | |
233 | ||
6b8858a9 PW |
234 | /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ |
235 | #define EN_APLL_STOPPED 0 | |
236 | #define EN_APLL_LOCKED 3 | |
ddc32a87 | 237 | |
6b8858a9 PW |
238 | /* CM_CLKSEL1_PLL.APLLS_CLKIN options (24XX) */ |
239 | #define APLLS_CLKIN_19_2MHZ 0 | |
240 | #define APLLS_CLKIN_13MHZ 2 | |
241 | #define APLLS_CLKIN_12MHZ 3 | |
242 | ||
243 | /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ | |
046d6b28 TL |
244 | |
245 | static struct prcm_config *curr_prcm_set; | |
ae78dcf7 TL |
246 | static struct clk *vclk; |
247 | static struct clk *sclk; | |
046d6b28 | 248 | |
8e3bd351 TL |
249 | static void __iomem *prcm_clksrc_ctrl; |
250 | ||
046d6b28 | 251 | /*------------------------------------------------------------------------- |
6b8858a9 | 252 | * Omap24xx specific clock functions |
046d6b28 TL |
253 | *-------------------------------------------------------------------------*/ |
254 | ||
3dc21975 PW |
255 | /** |
256 | * omap2430_clk_i2chs_find_idlest - return CM_IDLEST info for 2430 I2CHS | |
257 | * @clk: struct clk * being enabled | |
258 | * @idlest_reg: void __iomem ** to store CM_IDLEST reg address into | |
259 | * @idlest_bit: pointer to a u8 to store the CM_IDLEST bit shift into | |
260 | * | |
261 | * OMAP2430 I2CHS CM_IDLEST bits are in CM_IDLEST1_CORE, but the | |
262 | * CM_*CLKEN bits are in CM_{I,F}CLKEN2_CORE. This custom function | |
263 | * passes back the correct CM_IDLEST register address for I2CHS | |
264 | * modules. No return value. | |
265 | */ | |
266 | static void omap2430_clk_i2chs_find_idlest(struct clk *clk, | |
267 | void __iomem **idlest_reg, | |
268 | u8 *idlest_bit) | |
269 | { | |
270 | *idlest_reg = OMAP_CM_REGADDR(CORE_MOD, CM_IDLEST); | |
271 | *idlest_bit = clk->enable_bit; | |
272 | } | |
273 | ||
274 | ||
c0bf3132 RK |
275 | /** |
276 | * omap2xxx_clk_get_core_rate - return the CORE_CLK rate | |
277 | * @clk: pointer to the combined dpll_ck + core_ck (currently "dpll_ck") | |
278 | * | |
279 | * Returns the CORE_CLK rate. CORE_CLK can have one of three rate | |
280 | * sources on OMAP2xxx: the DPLL CLKOUT rate, DPLL CLKOUTX2, or 32KHz | |
281 | * (the latter is unusual). This currently should be called with | |
282 | * struct clk *dpll_ck, which is a composite clock of dpll_ck and | |
283 | * core_ck. | |
284 | */ | |
285 | static unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) | |
a16e9703 | 286 | { |
c0bf3132 RK |
287 | long long core_clk; |
288 | u32 v; | |
a16e9703 | 289 | |
c0bf3132 | 290 | core_clk = omap2_get_dpll_rate(clk); |
a16e9703 | 291 | |
c0bf3132 RK |
292 | v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
293 | v &= OMAP24XX_CORE_CLK_SRC_MASK; | |
294 | ||
295 | if (v == CORE_CLK_SRC_32K) | |
296 | core_clk = 32768; | |
297 | else | |
298 | core_clk *= v; | |
a16e9703 | 299 | |
c0bf3132 | 300 | return core_clk; |
a16e9703 TL |
301 | } |
302 | ||
6b8858a9 PW |
303 | static int omap2_enable_osc_ck(struct clk *clk) |
304 | { | |
305 | u32 pcc; | |
306 | ||
8e3bd351 | 307 | pcc = __raw_readl(prcm_clksrc_ctrl); |
6b8858a9 | 308 | |
8e3bd351 | 309 | __raw_writel(pcc & ~OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); |
6b8858a9 PW |
310 | |
311 | return 0; | |
312 | } | |
313 | ||
314 | static void omap2_disable_osc_ck(struct clk *clk) | |
315 | { | |
316 | u32 pcc; | |
317 | ||
8e3bd351 | 318 | pcc = __raw_readl(prcm_clksrc_ctrl); |
6b8858a9 | 319 | |
8e3bd351 | 320 | __raw_writel(pcc | OMAP_AUTOEXTCLKMODE_MASK, prcm_clksrc_ctrl); |
6b8858a9 PW |
321 | } |
322 | ||
548d8495 RK |
323 | static const struct clkops clkops_oscck = { |
324 | .enable = &omap2_enable_osc_ck, | |
325 | .disable = &omap2_disable_osc_ck, | |
326 | }; | |
327 | ||
6b8858a9 | 328 | #ifdef OLD_CK |
046d6b28 TL |
329 | /* Recalculate SYST_CLK */ |
330 | static void omap2_sys_clk_recalc(struct clk * clk) | |
331 | { | |
332 | u32 div = PRCM_CLKSRC_CTRL; | |
333 | div &= (1 << 7) | (1 << 6); /* Test if ext clk divided by 1 or 2 */ | |
334 | div >>= clk->rate_offset; | |
335 | clk->rate = (clk->parent->rate / div); | |
336 | propagate_rate(clk); | |
337 | } | |
6b8858a9 | 338 | #endif /* OLD_CK */ |
046d6b28 | 339 | |
046d6b28 | 340 | /* Enable an APLL if off */ |
6b8858a9 | 341 | static int omap2_clk_fixed_enable(struct clk *clk) |
046d6b28 | 342 | { |
6b8858a9 | 343 | u32 cval, apll_mask; |
046d6b28 | 344 | |
6b8858a9 | 345 | apll_mask = EN_APLL_LOCKED << clk->enable_bit; |
046d6b28 | 346 | |
6b8858a9 | 347 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
046d6b28 | 348 | |
6b8858a9 PW |
349 | if ((cval & apll_mask) == apll_mask) |
350 | return 0; /* apll already enabled */ | |
046d6b28 | 351 | |
6b8858a9 PW |
352 | cval &= ~apll_mask; |
353 | cval |= apll_mask; | |
354 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | |
046d6b28 TL |
355 | |
356 | if (clk == &apll96_ck) | |
6b8858a9 | 357 | cval = OMAP24XX_ST_96M_APLL; |
046d6b28 | 358 | else if (clk == &apll54_ck) |
6b8858a9 | 359 | cval = OMAP24XX_ST_54M_APLL; |
046d6b28 | 360 | |
3dc21975 PW |
361 | omap2_cm_wait_idlest(OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST), cval, |
362 | clk->name); | |
6b8858a9 PW |
363 | |
364 | /* | |
365 | * REVISIT: Should we return an error code if omap2_wait_clock_ready() | |
366 | * fails? | |
367 | */ | |
368 | return 0; | |
046d6b28 TL |
369 | } |
370 | ||
046d6b28 TL |
371 | /* Stop APLL */ |
372 | static void omap2_clk_fixed_disable(struct clk *clk) | |
373 | { | |
374 | u32 cval; | |
375 | ||
6b8858a9 PW |
376 | cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); |
377 | cval &= ~(EN_APLL_LOCKED << clk->enable_bit); | |
378 | cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); | |
046d6b28 TL |
379 | } |
380 | ||
548d8495 RK |
381 | static const struct clkops clkops_fixed = { |
382 | .enable = &omap2_clk_fixed_enable, | |
383 | .disable = &omap2_clk_fixed_disable, | |
384 | }; | |
385 | ||
046d6b28 TL |
386 | /* |
387 | * Uses the current prcm set to tell if a rate is valid. | |
388 | * You can go slower, but not faster within a given rate set. | |
389 | */ | |
fecb494b | 390 | static long omap2_dpllcore_round_rate(unsigned long target_rate) |
046d6b28 | 391 | { |
6b8858a9 | 392 | u32 high, low, core_clk_src; |
046d6b28 | 393 | |
6b8858a9 PW |
394 | core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
395 | core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; | |
396 | ||
397 | if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ | |
046d6b28 TL |
398 | high = curr_prcm_set->dpll_speed * 2; |
399 | low = curr_prcm_set->dpll_speed; | |
400 | } else { /* DPLL clockout x 2 */ | |
401 | high = curr_prcm_set->dpll_speed; | |
402 | low = curr_prcm_set->dpll_speed / 2; | |
403 | } | |
404 | ||
405 | #ifdef DOWN_VARIABLE_DPLL | |
406 | if (target_rate > high) | |
407 | return high; | |
408 | else | |
409 | return target_rate; | |
410 | #else | |
411 | if (target_rate > low) | |
412 | return high; | |
413 | else | |
414 | return low; | |
415 | #endif | |
416 | ||
417 | } | |
418 | ||
8b9dbc16 | 419 | static unsigned long omap2_dpllcore_recalc(struct clk *clk) |
6b8858a9 | 420 | { |
c0bf3132 | 421 | return omap2xxx_clk_get_core_rate(clk); |
6b8858a9 | 422 | } |
046d6b28 | 423 | |
88b8ba90 | 424 | static int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) |
046d6b28 | 425 | { |
6b8858a9 | 426 | u32 cur_rate, low, mult, div, valid_rate, done_rate; |
046d6b28 TL |
427 | u32 bypass = 0; |
428 | struct prcm_config tmpset; | |
6b8858a9 | 429 | const struct dpll_data *dd; |
046d6b28 | 430 | |
c0bf3132 | 431 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); |
6b8858a9 PW |
432 | mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
433 | mult &= OMAP24XX_CORE_CLK_SRC_MASK; | |
046d6b28 TL |
434 | |
435 | if ((rate == (cur_rate / 2)) && (mult == 2)) { | |
f2ab9977 | 436 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
046d6b28 | 437 | } else if ((rate == (cur_rate * 2)) && (mult == 1)) { |
f2ab9977 | 438 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
046d6b28 | 439 | } else if (rate != cur_rate) { |
88b8ba90 | 440 | valid_rate = omap2_dpllcore_round_rate(rate); |
046d6b28 | 441 | if (valid_rate != rate) |
883992bd | 442 | return -EINVAL; |
046d6b28 | 443 | |
6b8858a9 | 444 | if (mult == 1) |
046d6b28 TL |
445 | low = curr_prcm_set->dpll_speed; |
446 | else | |
447 | low = curr_prcm_set->dpll_speed / 2; | |
448 | ||
6b8858a9 PW |
449 | dd = clk->dpll_data; |
450 | if (!dd) | |
883992bd | 451 | return -EINVAL; |
6b8858a9 PW |
452 | |
453 | tmpset.cm_clksel1_pll = __raw_readl(dd->mult_div1_reg); | |
454 | tmpset.cm_clksel1_pll &= ~(dd->mult_mask | | |
455 | dd->div1_mask); | |
046d6b28 | 456 | div = ((curr_prcm_set->xtal_speed / 1000000) - 1); |
6b8858a9 PW |
457 | tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); |
458 | tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; | |
046d6b28 | 459 | if (rate > low) { |
6b8858a9 | 460 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; |
046d6b28 | 461 | mult = ((rate / 2) / 1000000); |
6b8858a9 | 462 | done_rate = CORE_CLK_SRC_DPLL_X2; |
046d6b28 | 463 | } else { |
6b8858a9 | 464 | tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL; |
046d6b28 | 465 | mult = (rate / 1000000); |
6b8858a9 | 466 | done_rate = CORE_CLK_SRC_DPLL; |
046d6b28 | 467 | } |
6b8858a9 PW |
468 | tmpset.cm_clksel1_pll |= (div << __ffs(dd->mult_mask)); |
469 | tmpset.cm_clksel1_pll |= (mult << __ffs(dd->div1_mask)); | |
046d6b28 TL |
470 | |
471 | /* Worst case */ | |
6b8858a9 | 472 | tmpset.base_sdrc_rfr = SDRC_RFR_CTRL_BYPASS; |
046d6b28 TL |
473 | |
474 | if (rate == curr_prcm_set->xtal_speed) /* If asking for 1-1 */ | |
475 | bypass = 1; | |
476 | ||
f2ab9977 PW |
477 | /* For omap2xxx_sdrc_init_params() */ |
478 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | |
046d6b28 TL |
479 | |
480 | /* Force dll lock mode */ | |
481 | omap2_set_prcm(tmpset.cm_clksel1_pll, tmpset.base_sdrc_rfr, | |
482 | bypass); | |
483 | ||
484 | /* Errata: ret dll entry state */ | |
f2ab9977 PW |
485 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
486 | omap2xxx_sdrc_reprogram(done_rate, 0); | |
046d6b28 | 487 | } |
046d6b28 | 488 | |
883992bd | 489 | return 0; |
046d6b28 TL |
490 | } |
491 | ||
6b8858a9 PW |
492 | /** |
493 | * omap2_table_mpu_recalc - just return the MPU speed | |
494 | * @clk: virt_prcm_set struct clk | |
495 | * | |
496 | * Set virt_prcm_set's rate to the mpu_speed field of the current PRCM set. | |
497 | */ | |
8b9dbc16 | 498 | static unsigned long omap2_table_mpu_recalc(struct clk *clk) |
046d6b28 | 499 | { |
8b9dbc16 | 500 | return curr_prcm_set->mpu_speed; |
046d6b28 TL |
501 | } |
502 | ||
503 | /* | |
504 | * Look for a rate equal or less than the target rate given a configuration set. | |
505 | * | |
506 | * What's not entirely clear is "which" field represents the key field. | |
507 | * Some might argue L3-DDR, others ARM, others IVA. This code is simple and | |
508 | * just uses the ARM rates. | |
509 | */ | |
6b8858a9 | 510 | static long omap2_round_to_table_rate(struct clk *clk, unsigned long rate) |
046d6b28 | 511 | { |
6b8858a9 | 512 | struct prcm_config *ptr; |
046d6b28 TL |
513 | long highest_rate; |
514 | ||
515 | if (clk != &virt_prcm_set) | |
516 | return -EINVAL; | |
517 | ||
518 | highest_rate = -EINVAL; | |
519 | ||
520 | for (ptr = rate_table; ptr->mpu_speed; ptr++) { | |
6b8858a9 PW |
521 | if (!(ptr->flags & cpu_mask)) |
522 | continue; | |
046d6b28 TL |
523 | if (ptr->xtal_speed != sys_ck.rate) |
524 | continue; | |
525 | ||
526 | highest_rate = ptr->mpu_speed; | |
527 | ||
528 | /* Can check only after xtal frequency check */ | |
529 | if (ptr->mpu_speed <= rate) | |
530 | break; | |
531 | } | |
532 | return highest_rate; | |
533 | } | |
534 | ||
046d6b28 | 535 | /* Sets basic clocks based on the specified rate */ |
6b8858a9 | 536 | static int omap2_select_table_rate(struct clk *clk, unsigned long rate) |
046d6b28 | 537 | { |
6b8858a9 | 538 | u32 cur_rate, done_rate, bypass = 0, tmp; |
046d6b28 TL |
539 | struct prcm_config *prcm; |
540 | unsigned long found_speed = 0; | |
6b8858a9 | 541 | unsigned long flags; |
046d6b28 TL |
542 | |
543 | if (clk != &virt_prcm_set) | |
544 | return -EINVAL; | |
545 | ||
046d6b28 TL |
546 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
547 | if (!(prcm->flags & cpu_mask)) | |
548 | continue; | |
549 | ||
550 | if (prcm->xtal_speed != sys_ck.rate) | |
551 | continue; | |
552 | ||
553 | if (prcm->mpu_speed <= rate) { | |
554 | found_speed = prcm->mpu_speed; | |
555 | break; | |
556 | } | |
557 | } | |
558 | ||
559 | if (!found_speed) { | |
560 | printk(KERN_INFO "Could not set MPU rate to %luMHz\n", | |
a16e9703 | 561 | rate / 1000000); |
046d6b28 TL |
562 | return -EINVAL; |
563 | } | |
564 | ||
565 | curr_prcm_set = prcm; | |
c0bf3132 | 566 | cur_rate = omap2xxx_clk_get_core_rate(&dpll_ck); |
046d6b28 TL |
567 | |
568 | if (prcm->dpll_speed == cur_rate / 2) { | |
f2ab9977 | 569 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL, 1); |
046d6b28 | 570 | } else if (prcm->dpll_speed == cur_rate * 2) { |
f2ab9977 | 571 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); |
046d6b28 TL |
572 | } else if (prcm->dpll_speed != cur_rate) { |
573 | local_irq_save(flags); | |
574 | ||
575 | if (prcm->dpll_speed == prcm->xtal_speed) | |
576 | bypass = 1; | |
577 | ||
6b8858a9 PW |
578 | if ((prcm->cm_clksel2_pll & OMAP24XX_CORE_CLK_SRC_MASK) == |
579 | CORE_CLK_SRC_DPLL_X2) | |
580 | done_rate = CORE_CLK_SRC_DPLL_X2; | |
046d6b28 | 581 | else |
6b8858a9 | 582 | done_rate = CORE_CLK_SRC_DPLL; |
046d6b28 TL |
583 | |
584 | /* MPU divider */ | |
6b8858a9 | 585 | cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); |
046d6b28 TL |
586 | |
587 | /* dsp + iva1 div(2420), iva2.1(2430) */ | |
6b8858a9 PW |
588 | cm_write_mod_reg(prcm->cm_clksel_dsp, |
589 | OMAP24XX_DSP_MOD, CM_CLKSEL); | |
046d6b28 | 590 | |
6b8858a9 | 591 | cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); |
046d6b28 TL |
592 | |
593 | /* Major subsystem dividers */ | |
6b8858a9 | 594 | tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; |
fecb494b PW |
595 | cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, |
596 | CM_CLKSEL1); | |
597 | ||
046d6b28 | 598 | if (cpu_is_omap2430()) |
6b8858a9 PW |
599 | cm_write_mod_reg(prcm->cm_clksel_mdm, |
600 | OMAP2430_MDM_MOD, CM_CLKSEL); | |
046d6b28 | 601 | |
f2ab9977 PW |
602 | /* x2 to enter omap2xxx_sdrc_init_params() */ |
603 | omap2xxx_sdrc_reprogram(CORE_CLK_SRC_DPLL_X2, 1); | |
046d6b28 TL |
604 | |
605 | omap2_set_prcm(prcm->cm_clksel1_pll, prcm->base_sdrc_rfr, | |
606 | bypass); | |
607 | ||
f2ab9977 PW |
608 | omap2xxx_sdrc_init_params(omap2xxx_sdrc_dll_is_unlocked()); |
609 | omap2xxx_sdrc_reprogram(done_rate, 0); | |
046d6b28 TL |
610 | |
611 | local_irq_restore(flags); | |
612 | } | |
046d6b28 TL |
613 | |
614 | return 0; | |
615 | } | |
616 | ||
aeec2990 KH |
617 | #ifdef CONFIG_CPU_FREQ |
618 | /* | |
619 | * Walk PRCM rate table and fillout cpufreq freq_table | |
620 | */ | |
621 | static struct cpufreq_frequency_table freq_table[ARRAY_SIZE(rate_table)]; | |
622 | ||
623 | void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table) | |
624 | { | |
625 | struct prcm_config *prcm; | |
626 | int i = 0; | |
627 | ||
628 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { | |
629 | if (!(prcm->flags & cpu_mask)) | |
630 | continue; | |
631 | if (prcm->xtal_speed != sys_ck.rate) | |
632 | continue; | |
633 | ||
634 | /* don't put bypass rates in table */ | |
635 | if (prcm->dpll_speed == prcm->xtal_speed) | |
636 | continue; | |
637 | ||
638 | freq_table[i].index = i; | |
639 | freq_table[i].frequency = prcm->mpu_speed / 1000; | |
640 | i++; | |
641 | } | |
642 | ||
643 | if (i == 0) { | |
644 | printk(KERN_WARNING "%s: failed to initialize frequency " | |
645 | "table\n", __func__); | |
646 | return; | |
647 | } | |
648 | ||
649 | freq_table[i].index = i; | |
650 | freq_table[i].frequency = CPUFREQ_TABLE_END; | |
651 | ||
652 | *table = &freq_table[0]; | |
653 | } | |
654 | #endif | |
655 | ||
046d6b28 TL |
656 | static struct clk_functions omap2_clk_functions = { |
657 | .clk_enable = omap2_clk_enable, | |
658 | .clk_disable = omap2_clk_disable, | |
046d6b28 TL |
659 | .clk_round_rate = omap2_clk_round_rate, |
660 | .clk_set_rate = omap2_clk_set_rate, | |
661 | .clk_set_parent = omap2_clk_set_parent, | |
90afd5cb | 662 | .clk_disable_unused = omap2_clk_disable_unused, |
aeec2990 KH |
663 | #ifdef CONFIG_CPU_FREQ |
664 | .clk_init_cpufreq_table = omap2_clk_init_cpufreq_table, | |
665 | #endif | |
046d6b28 TL |
666 | }; |
667 | ||
6b8858a9 | 668 | static u32 omap2_get_apll_clkin(void) |
046d6b28 | 669 | { |
fecb494b | 670 | u32 aplls, srate = 0; |
046d6b28 | 671 | |
6b8858a9 PW |
672 | aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); |
673 | aplls &= OMAP24XX_APLLS_CLKIN_MASK; | |
674 | aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; | |
046d6b28 | 675 | |
6b8858a9 | 676 | if (aplls == APLLS_CLKIN_19_2MHZ) |
fecb494b | 677 | srate = 19200000; |
6b8858a9 | 678 | else if (aplls == APLLS_CLKIN_13MHZ) |
fecb494b | 679 | srate = 13000000; |
6b8858a9 | 680 | else if (aplls == APLLS_CLKIN_12MHZ) |
fecb494b | 681 | srate = 12000000; |
046d6b28 | 682 | |
fecb494b | 683 | return srate; |
6b8858a9 PW |
684 | } |
685 | ||
686 | static u32 omap2_get_sysclkdiv(void) | |
687 | { | |
688 | u32 div; | |
689 | ||
8e3bd351 | 690 | div = __raw_readl(prcm_clksrc_ctrl); |
6b8858a9 PW |
691 | div &= OMAP_SYSCLKDIV_MASK; |
692 | div >>= OMAP_SYSCLKDIV_SHIFT; | |
046d6b28 | 693 | |
6b8858a9 PW |
694 | return div; |
695 | } | |
696 | ||
8b9dbc16 | 697 | static unsigned long omap2_osc_clk_recalc(struct clk *clk) |
6b8858a9 | 698 | { |
8b9dbc16 | 699 | return omap2_get_apll_clkin() * omap2_get_sysclkdiv(); |
6b8858a9 PW |
700 | } |
701 | ||
8b9dbc16 | 702 | static unsigned long omap2_sys_clk_recalc(struct clk *clk) |
6b8858a9 | 703 | { |
8b9dbc16 | 704 | return clk->parent->rate / omap2_get_sysclkdiv(); |
046d6b28 TL |
705 | } |
706 | ||
ae78dcf7 TL |
707 | /* |
708 | * Set clocks for bypass mode for reboot to work. | |
709 | */ | |
710 | void omap2_clk_prepare_for_reboot(void) | |
711 | { | |
712 | u32 rate; | |
713 | ||
714 | if (vclk == NULL || sclk == NULL) | |
715 | return; | |
716 | ||
717 | rate = clk_get_rate(sclk); | |
718 | clk_set_rate(vclk, rate); | |
719 | } | |
720 | ||
046d6b28 TL |
721 | /* |
722 | * Switch the MPU rate if specified on cmdline. | |
723 | * We cannot do this early until cmdline is parsed. | |
724 | */ | |
725 | static int __init omap2_clk_arch_init(void) | |
726 | { | |
727 | if (!mpurate) | |
728 | return -EINVAL; | |
729 | ||
7b0f89d7 | 730 | if (clk_set_rate(&virt_prcm_set, mpurate)) |
046d6b28 TL |
731 | printk(KERN_ERR "Could not find matching MPU rate\n"); |
732 | ||
6b8858a9 | 733 | recalculate_root_clocks(); |
046d6b28 TL |
734 | |
735 | printk(KERN_INFO "Switched to new clocking rate (Crystal/DPLL/MPU): " | |
736 | "%ld.%01ld/%ld/%ld MHz\n", | |
737 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
738 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
739 | ||
740 | return 0; | |
741 | } | |
742 | arch_initcall(omap2_clk_arch_init); | |
743 | ||
744 | int __init omap2_clk_init(void) | |
745 | { | |
746 | struct prcm_config *prcm; | |
8ad8ff65 | 747 | struct omap_clk *c; |
15ca78f7 | 748 | u32 clkrate; |
046d6b28 | 749 | |
8e3bd351 TL |
750 | if (cpu_is_omap242x()) { |
751 | prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL; | |
6b8858a9 | 752 | cpu_mask = RATE_IN_242X; |
8e3bd351 TL |
753 | } else if (cpu_is_omap2430()) { |
754 | prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL; | |
6b8858a9 | 755 | cpu_mask = RATE_IN_243X; |
8e3bd351 | 756 | } |
6b8858a9 | 757 | |
046d6b28 | 758 | clk_init(&omap2_clk_functions); |
046d6b28 | 759 | |
c8088112 | 760 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
79716870 | 761 | clk_preinit(c->lk.clk); |
c8088112 | 762 | |
8b9dbc16 | 763 | osc_ck.rate = omap2_osc_clk_recalc(&osc_ck); |
9a5fedac | 764 | propagate_rate(&osc_ck); |
8b9dbc16 | 765 | sys_ck.rate = omap2_sys_clk_recalc(&sys_ck); |
9a5fedac | 766 | propagate_rate(&sys_ck); |
6b8858a9 | 767 | |
8ad8ff65 RK |
768 | for (c = omap24xx_clks; c < omap24xx_clks + ARRAY_SIZE(omap24xx_clks); c++) |
769 | if (c->cpu & cpu_mask) { | |
770 | clkdev_add(&c->lk); | |
771 | clk_register(c->lk.clk); | |
046d6b28 TL |
772 | } |
773 | ||
046d6b28 | 774 | /* Check the MPU rate set by bootloader */ |
c0bf3132 | 775 | clkrate = omap2xxx_clk_get_core_rate(&dpll_ck); |
046d6b28 | 776 | for (prcm = rate_table; prcm->mpu_speed; prcm++) { |
6b8858a9 PW |
777 | if (!(prcm->flags & cpu_mask)) |
778 | continue; | |
046d6b28 TL |
779 | if (prcm->xtal_speed != sys_ck.rate) |
780 | continue; | |
781 | if (prcm->dpll_speed <= clkrate) | |
782 | break; | |
783 | } | |
784 | curr_prcm_set = prcm; | |
785 | ||
6b8858a9 | 786 | recalculate_root_clocks(); |
046d6b28 TL |
787 | |
788 | printk(KERN_INFO "Clocking rate (Crystal/DPLL/MPU): " | |
789 | "%ld.%01ld/%ld/%ld MHz\n", | |
790 | (sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10, | |
791 | (dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ; | |
792 | ||
793 | /* | |
794 | * Only enable those clocks we will need, let the drivers | |
795 | * enable other clocks as necessary | |
796 | */ | |
6b8858a9 | 797 | clk_enable_init_clocks(); |
046d6b28 | 798 | |
ae78dcf7 TL |
799 | /* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */ |
800 | vclk = clk_get(NULL, "virt_prcm_set"); | |
801 | sclk = clk_get(NULL, "sys_ck"); | |
802 | ||
046d6b28 TL |
803 | return 0; |
804 | } |