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1 | /* |
2 | * linux/arch/arm/mach-omap2/clock.h | |
3 | * | |
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4 | * Copyright (C) 2005-2009 Texas Instruments, Inc. |
5 | * Copyright (C) 2004-2009 Nokia Corporation | |
543d9378 | 6 | * |
a16e9703 TL |
7 | * Contacts: |
8 | * Richard Woodruff <r-woodruff2@ti.com> | |
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9 | * Paul Walmsley |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
17 | #define __ARCH_ARM_MACH_OMAP2_CLOCK_H | |
18 | ||
ce491cf8 | 19 | #include <plat/clock.h> |
543d9378 | 20 | |
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21 | /* The maximum error between a target DPLL rate and the rounded rate in Hz */ |
22 | #define DEFAULT_DPLL_RATE_TOLERANCE 50000 | |
23 | ||
c0bf3132 RK |
24 | /* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */ |
25 | #define CORE_CLK_SRC_32K 0x0 | |
26 | #define CORE_CLK_SRC_DPLL 0x1 | |
27 | #define CORE_CLK_SRC_DPLL_X2 0x2 | |
28 | ||
29 | /* OMAP2xxx CM_CLKEN_PLL.EN_DPLL bits - for omap2_get_dpll_rate() */ | |
30 | #define OMAP2XXX_EN_DPLL_LPBYPASS 0x1 | |
31 | #define OMAP2XXX_EN_DPLL_FRBYPASS 0x2 | |
32 | #define OMAP2XXX_EN_DPLL_LOCKED 0x3 | |
33 | ||
34 | /* OMAP3xxx CM_CLKEN_PLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ | |
35 | #define OMAP3XXX_EN_DPLL_LPBYPASS 0x5 | |
36 | #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 | |
37 | #define OMAP3XXX_EN_DPLL_LOCKED 0x7 | |
38 | ||
16975a79 RN |
39 | /* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */ |
40 | #define OMAP4XXX_EN_DPLL_MNBYPASS 0x4 | |
41 | #define OMAP4XXX_EN_DPLL_LPBYPASS 0x5 | |
42 | #define OMAP4XXX_EN_DPLL_FRBYPASS 0x6 | |
43 | #define OMAP4XXX_EN_DPLL_LOCKED 0x7 | |
44 | ||
a1391d27 RN |
45 | /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */ |
46 | #define DPLL_LOW_POWER_STOP 0x1 | |
47 | #define DPLL_LOW_POWER_BYPASS 0x5 | |
48 | #define DPLL_LOCKED 0x7 | |
49 | ||
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50 | int omap2_clk_enable(struct clk *clk); |
51 | void omap2_clk_disable(struct clk *clk); | |
52 | long omap2_clk_round_rate(struct clk *clk, unsigned long rate); | |
53 | int omap2_clk_set_rate(struct clk *clk, unsigned long rate); | |
54 | int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); | |
fecb494b | 55 | int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); |
88b8ba90 | 56 | long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); |
a1391d27 RN |
57 | unsigned long omap3_dpll_recalc(struct clk *clk); |
58 | unsigned long omap3_clkoutx2_recalc(struct clk *clk); | |
59 | void omap3_dpll_allow_idle(struct clk *clk); | |
60 | void omap3_dpll_deny_idle(struct clk *clk); | |
61 | u32 omap3_dpll_autoidle_read(struct clk *clk); | |
62 | int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate); | |
63 | int omap3_noncore_dpll_enable(struct clk *clk); | |
64 | void omap3_noncore_dpll_disable(struct clk *clk); | |
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65 | |
66 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
67 | void omap2_clk_disable_unused(struct clk *clk); | |
68 | #else | |
69 | #define omap2_clk_disable_unused NULL | |
70 | #endif | |
71 | ||
8b9dbc16 | 72 | unsigned long omap2_clksel_recalc(struct clk *clk); |
333943ba | 73 | void omap2_init_clk_clkdm(struct clk *clk); |
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74 | void omap2_init_clksel_parent(struct clk *clk); |
75 | u32 omap2_clksel_get_divisor(struct clk *clk); | |
76 | u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate, | |
77 | u32 *new_div); | |
78 | u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val); | |
79 | u32 omap2_divisor_to_clksel(struct clk *clk, u32 div); | |
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80 | long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); |
81 | int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); | |
df791b3e | 82 | int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent); |
543d9378 | 83 | u32 omap2_get_dpll_rate(struct clk *clk); |
911bd739 | 84 | void omap2_init_dpll_parent(struct clk *clk); |
543d9378 | 85 | int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); |
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86 | |
87 | ||
88 | #ifdef CONFIG_ARCH_OMAP2 | |
89 | void omap2xxx_clk_prepare_for_reboot(void); | |
90 | #else | |
91 | static inline void omap2xxx_clk_prepare_for_reboot(void) | |
92 | { | |
93 | } | |
94 | #endif | |
95 | ||
96 | #ifdef CONFIG_ARCH_OMAP3 | |
97 | void omap3_clk_prepare_for_reboot(void); | |
98 | #else | |
99 | static inline void omap3_clk_prepare_for_reboot(void) | |
100 | { | |
101 | } | |
102 | #endif | |
103 | ||
104 | #ifdef CONFIG_ARCH_OMAP4 | |
105 | void omap4_clk_prepare_for_reboot(void); | |
106 | #else | |
107 | static inline void omap4_clk_prepare_for_reboot(void) | |
108 | { | |
109 | } | |
110 | #endif | |
111 | ||
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112 | int omap2_dflt_clk_enable(struct clk *clk); |
113 | void omap2_dflt_clk_disable(struct clk *clk); | |
114 | void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, | |
115 | u8 *other_bit); | |
116 | void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, | |
419cc97d | 117 | u8 *idlest_bit, u8 *idlest_val); |
df791b3e | 118 | void omap2xxx_clk_commit(struct clk *clk); |
543d9378 | 119 | |
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120 | extern u8 cpu_mask; |
121 | ||
b36ee724 | 122 | extern const struct clkops clkops_omap2_dflt_wait; |
bc51da4e | 123 | extern const struct clkops clkops_omap2_dflt; |
b36ee724 | 124 | |
82e9bd58 | 125 | extern struct clk_functions omap2_clk_functions; |
d8a94458 | 126 | extern struct clk *vclk, *sclk; |
82e9bd58 | 127 | |
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128 | extern const struct clksel_rate gpt_32k_rates[]; |
129 | extern const struct clksel_rate gpt_sys_rates[]; | |
130 | extern const struct clksel_rate gfx_l3_rates[]; | |
543d9378 | 131 | |
088ef950 | 132 | #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_CPU_FREQ) |
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133 | extern void omap2_clk_init_cpufreq_table(struct cpufreq_frequency_table **table); |
134 | extern void omap2_clk_exit_cpufreq_table(struct cpufreq_frequency_table **table); | |
135 | #else | |
136 | #define omap2_clk_init_cpufreq_table 0 | |
137 | #define omap2_clk_exit_cpufreq_table 0 | |
138 | #endif | |
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139 | |
140 | #endif |