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ARM: OMAP2+: Remove legacy support for zoom platforms
[linux-2.6-block.git] / arch / arm / mach-omap2 / board-igep0020.c
CommitLineData
58e11162
EBS		 1/*
2 * Copyright (C) 2009 Integration Software and Electronic Engineering.
3 *
4 * Modified from mach-omap2/board-generic.c
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/platform_device.h>
14#include <linux/delay.h>
15#include <linux/err.h>
16#include <linux/clk.h>
17#include <linux/io.h>
18#include <linux/gpio.h>
19#include <linux/interrupt.h>
18cbc7d9 20#include <linux/input.h>
51482be9 21#include <linux/usb/phy.h>
58e11162
EBS		 22
23#include <linux/regulator/machine.h>
da07c0cf 24#include <linux/regulator/fixed.h>
ebeb53e1 25#include <linux/i2c/twl.h>
3a63833e 26#include <linux/mmc/host.h>
58e11162 27
a42cf2c6
JMC		 28#include <linux/mtd/nand.h>
29
58e11162
EBS		 30#include <asm/mach-types.h>
31#include <asm/mach/arch.h>
32
a0b38cc4 33#include <video/omapdss.h>
a0d8dde9 34#include <video/omap-panel-data.h>
2203747c 35#include <linux/platform_data/mtd-onenand-omap2.h>
58e11162 36
6d02643d
TL		 37#include "common.h"
38#include "gpmc.h"
ca5742bd 39#include "mux.h"
d02a900b 40#include "hsmmc.h"
22f1baac 41#include "sdram-numonyx-m65kxxxxam.h"
fbd8071c 42#include "common-board-devices.h"
a42cf2c6
JMC		 43#include "board-flash.h"
44#include "control.h"
b6ab13e7 45#include "gpmc-onenand.h"
68a531a1 46#include "dss-common.h"
58e11162
EBS		 47
48#define IGEP2_SMSC911X_CS 5
49#define IGEP2_SMSC911X_GPIO 176
50#define IGEP2_GPIO_USBH_NRESET 24
5a9fcc99
EBS		 51#define IGEP2_GPIO_LED0_GREEN 26
52#define IGEP2_GPIO_LED0_RED 27
53#define IGEP2_GPIO_LED1_RED 28
5a9fcc99
EBS		 54
55#define IGEP2_RB_GPIO_WIFI_NPD 94
56#define IGEP2_RB_GPIO_WIFI_NRESET 95
57#define IGEP2_RB_GPIO_BT_NRESET 137
58#define IGEP2_RC_GPIO_WIFI_NPD 138
59#define IGEP2_RC_GPIO_WIFI_NRESET 139
60#define IGEP2_RC_GPIO_BT_NRESET 137
58e11162 61
2a60997a
MR		 62#define IGEP3_GPIO_LED0_GREEN 54
63#define IGEP3_GPIO_LED0_RED 53
64#define IGEP3_GPIO_LED1_RED 16
65#define IGEP3_GPIO_USBH_NRESET 183
66
a42cf2c6
JMC		 67#define IGEP_SYSBOOT_MASK 0x1f
68#define IGEP_SYSBOOT_NAND 0x0f
69#define IGEP_SYSBOOT_ONENAND 0x10
70
3f8c48d9
EBS		 71/*
72 * IGEP2 Hardware Revision Table
73 *
5a9fcc99
EBS		 74 * --------------------------------------------------------------------------
75 * | Id. | Hw Rev. | HW0 (28) | WIFI_NPD | WIFI_NRESET | BT_NRESET |
76 * --------------------------------------------------------------------------
77 * | 0 | B | high | gpio94 | gpio95 | - |
78 * | 0 | B/C (B-compatible) | high | gpio94 | gpio95 | gpio137 |
79 * | 1 | C | low | gpio138 | gpio139 | gpio137 |
80 * --------------------------------------------------------------------------
3f8c48d9
EBS		 81 */
82
83#define IGEP2_BOARD_HWREV_B 0
84#define IGEP2_BOARD_HWREV_C 1
2a60997a 85#define IGEP3_BOARD_HWREV 2
3f8c48d9
EBS		 86
87static u8 hwrev;
88
89static void __init igep2_get_revision(void)
90{
91 u8 ret;
92
2a60997a
MR		 93 if (machine_is_igep0030()) {
94 hwrev = IGEP3_BOARD_HWREV;
95 return;
96 }
97
3f8c48d9
EBS		 98 omap_mux_init_gpio(IGEP2_GPIO_LED1_RED, OMAP_PIN_INPUT);
99
bc593f5d 100 if (gpio_request_one(IGEP2_GPIO_LED1_RED, GPIOF_IN, "GPIO_HW0_REV")) {
3f8c48d9
EBS		 101 pr_warning("IGEP2: Could not obtain gpio GPIO_HW0_REV\n");
102 pr_err("IGEP2: Unknown Hardware Revision\n");
bc593f5d
IG		 103 return;
104 }
105
106 ret = gpio_get_value(IGEP2_GPIO_LED1_RED);
107 if (ret == 0) {
108 pr_info("IGEP2: Hardware Revision C (B-NON compatible)\n");
109 hwrev = IGEP2_BOARD_HWREV_C;
110 } else if (ret == 1) {
111 pr_info("IGEP2: Hardware Revision B/C (B compatible)\n");
112 hwrev = IGEP2_BOARD_HWREV_B;
113 } else {
114 pr_err("IGEP2: Unknown Hardware Revision\n");
115 hwrev = -1;
3f8c48d9
EBS		 116 }
117
118 gpio_free(IGEP2_GPIO_LED1_RED);
119}
58e11162 120
a42cf2c6
JMC		 121#if defined(CONFIG_MTD_ONENAND_OMAP2) || \
122 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE) || \
123 defined(CONFIG_MTD_NAND_OMAP2) || \
124 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
cddb483a
EBS		 125
126#define ONENAND_MAP 0x20000000
127
128/* NAND04GR4E1A ( x2 Flash built-in COMBO POP MEMORY )
129 * Since the device is equipped with two DataRAMs, and two-plane NAND
130 * Flash memory array, these two component enables simultaneous program
131 * of 4KiB. Plane1 has only even blocks such as block0, block2, block4
132 * while Plane2 has only odd blocks such as block1, block3, block5.
133 * So MTD regards it as 4KiB page size and 256KiB block size 64*(2*2048)
134 */
135
a42cf2c6 136static struct mtd_partition igep_flash_partitions[] = {
cddb483a
EBS		 137 {
138 .name = "X-Loader",
139 .offset = 0,
140 .size = 2 * (64*(2*2048))
141 },
142 {
143 .name = "U-Boot",
144 .offset = MTDPART_OFS_APPEND,
145 .size = 6 * (64*(2*2048)),
146 },
147 {
148 .name = "Environment",
149 .offset = MTDPART_OFS_APPEND,
150 .size = 2 * (64*(2*2048)),
151 },
152 {
153 .name = "Kernel",
154 .offset = MTDPART_OFS_APPEND,
155 .size = 12 * (64*(2*2048)),
156 },
157 {
158 .name = "File System",
159 .offset = MTDPART_OFS_APPEND,
160 .size = MTDPART_SIZ_FULL,
161 },
162};
163
a42cf2c6
JMC		 164static inline u32 igep_get_sysboot_value(void)
165{
166 return omap_ctrl_readl(OMAP343X_CONTROL_STATUS) & IGEP_SYSBOOT_MASK;
167}
cddb483a 168
fdfb03ba 169static void __init igep_flash_init(void)
cddb483a 170{
a42cf2c6
JMC		 171 u32 mux;
172 mux = igep_get_sysboot_value();
173
174 if (mux == IGEP_SYSBOOT_NAND) {
175 pr_info("IGEP: initializing NAND memory device\n");
176 board_nand_init(igep_flash_partitions,
177 ARRAY_SIZE(igep_flash_partitions),
2e618261 178 0, NAND_BUSWIDTH_16, nand_default_timings);
a42cf2c6
JMC		 179 } else if (mux == IGEP_SYSBOOT_ONENAND) {
180 pr_info("IGEP: initializing OneNAND memory device\n");
181 board_onenand_init(igep_flash_partitions,
182 ARRAY_SIZE(igep_flash_partitions), 0);
183 } else {
184 pr_err("IGEP: Flash: unsupported sysboot sequence found\n");
cddb483a 185 }
cddb483a
EBS		 186}
187
188#else
fdfb03ba 189static void __init igep_flash_init(void) {}
cddb483a
EBS		 190#endif
191
58e11162
EBS		 192#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
193
194#include <linux/smsc911x.h>
ac839b3c 195#include "gpmc-smsc911x.h"
58e11162 196
21b42731
MR		 197static struct omap_smsc911x_platform_data smsc911x_cfg = {
198 .cs = IGEP2_SMSC911X_CS,
199 .gpio_irq = IGEP2_SMSC911X_GPIO,
200 .gpio_reset = -EINVAL,
201 .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
58e11162
EBS		 202};
203
204static inline void __init igep2_init_smsc911x(void)
205{
21b42731 206 gpmc_smsc911x_init(&smsc911x_cfg);
58e11162
EBS		 207}
208
209#else
210static inline void __init igep2_init_smsc911x(void) { }
211#endif
212
786b01a8
OD		 213static struct regulator_consumer_supply igep_vmmc1_supply[] = {
214 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
215};
58e11162
EBS		 216
217/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
fdfb03ba 218static struct regulator_init_data igep_vmmc1 = {
58e11162
EBS		 219 .constraints = {
220 .min_uV = 1850000,
221 .max_uV = 3150000,
222 .valid_modes_mask = REGULATOR_MODE_NORMAL
223 | REGULATOR_MODE_STANDBY,
224 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
225 | REGULATOR_CHANGE_MODE
226 | REGULATOR_CHANGE_STATUS,
227 },
786b01a8
OD		 228 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
229 .consumer_supplies = igep_vmmc1_supply,
58e11162
EBS		 230};
231
786b01a8
OD		 232static struct regulator_consumer_supply igep_vio_supply[] = {
233 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
234};
da07c0cf 235
fdfb03ba 236static struct regulator_init_data igep_vio = {
da07c0cf
MZ		 237 .constraints = {
238 .min_uV = 1800000,
239 .max_uV = 1800000,
240 .apply_uV = 1,
241 .valid_modes_mask = REGULATOR_MODE_NORMAL
242 | REGULATOR_MODE_STANDBY,
243 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
244 | REGULATOR_CHANGE_MODE
245 | REGULATOR_CHANGE_STATUS,
246 },
786b01a8
OD		 247 .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
248 .consumer_supplies = igep_vio_supply,
da07c0cf
MZ		 249};
250
786b01a8
OD		 251static struct regulator_consumer_supply igep_vmmc2_supply[] = {
252 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
253};
da07c0cf 254
fdfb03ba 255static struct regulator_init_data igep_vmmc2 = {
da07c0cf
MZ		 256 .constraints = {
257 .valid_modes_mask = REGULATOR_MODE_NORMAL,
258 .always_on = 1,
259 },
786b01a8
OD		 260 .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
261 .consumer_supplies = igep_vmmc2_supply,
da07c0cf
MZ		 262};
263
fdfb03ba 264static struct fixed_voltage_config igep_vwlan = {
da07c0cf
MZ		 265 .supply_name = "vwlan",
266 .microvolts = 3300000,
267 .gpio = -EINVAL,
268 .enabled_at_boot = 1,
fdfb03ba 269 .init_data = &igep_vmmc2,
da07c0cf
MZ		 270};
271
fdfb03ba 272static struct platform_device igep_vwlan_device = {
da07c0cf
MZ		 273 .name = "reg-fixed-voltage",
274 .id = 0,
275 .dev = {
fdfb03ba 276 .platform_data = &igep_vwlan,
da07c0cf
MZ		 277 },
278};
279
68ff0423 280static struct omap2_hsmmc_info mmc[] = {
58e11162
EBS		 281 {
282 .mmc = 1,
3a63833e 283 .caps = MMC_CAP_4_BIT_DATA,
58e11162
EBS		 284 .gpio_cd = -EINVAL,
285 .gpio_wp = -EINVAL,
3b972bf0 286 .deferred = true,
58e11162 287 },
5a9fcc99 288#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
58e11162
EBS		 289 {
290 .mmc = 2,
3a63833e 291 .caps = MMC_CAP_4_BIT_DATA,
58e11162
EBS		 292 .gpio_cd = -EINVAL,
293 .gpio_wp = -EINVAL,
294 },
5a9fcc99 295#endif
58e11162
EBS		 296 {} /* Terminator */
297};
298
bee15390
EBS		 299#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
300#include <linux/leds.h>
301
fdfb03ba 302static struct gpio_led igep_gpio_leds[] = {
bee15390 303 [0] = {
8310f9d2
JMC		 304 .name = "omap3:red:user0",
305 .default_state = 0,
bee15390
EBS		 306 },
307 [1] = {
8310f9d2
JMC		 308 .name = "omap3:green:boot",
309 .default_state = 1,
bee15390
EBS		 310 },
311 [2] = {
8310f9d2
JMC		 312 .name = "omap3:red:user1",
313 .default_state = 0,
bee15390
EBS		 314 },
315 [3] = {
8310f9d2
JMC		 316 .name = "omap3:green:user1",
317 .default_state = 0,
bee15390 318 .gpio = -EINVAL, /* gets replaced */
70e77760 319 .active_low = 1,
bee15390
EBS		 320 },
321};
322
fdfb03ba
MR		 323static struct gpio_led_platform_data igep_led_pdata = {
324 .leds = igep_gpio_leds,
325 .num_leds = ARRAY_SIZE(igep_gpio_leds),
bee15390
EBS		 326};
327
fdfb03ba 328static struct platform_device igep_led_device = {
bee15390
EBS		 329 .name = "leds-gpio",
330 .id = -1,
331 .dev = {
fdfb03ba 332 .platform_data = &igep_led_pdata,
bee15390
EBS		 333 },
334};
335
fdfb03ba 336static void __init igep_leds_init(void)
bee15390 337{
2a60997a
MR		 338 if (machine_is_igep0020()) {
339 igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
340 igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
341 igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
342 } else {
343 igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
344 igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
345 igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
346 }
0d4ab9a5 347
fdfb03ba 348 platform_device_register(&igep_led_device);
bee15390
EBS		 349}
350
351#else
fdfb03ba 352static struct gpio igep_gpio_leds[] __initdata = {
2a60997a
MR		 353 { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:red:d0" },
354 { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:green:d0" },
355 { -EINVAL, GPIOF_OUT_INIT_LOW, "gpio-led:red:d1" },
bc593f5d
IG		 356};
357
fdfb03ba 358static inline void igep_leds_init(void)
bee15390 359{
0d4ab9a5 360 int i;
bee15390 361
2a60997a
MR		 362 if (machine_is_igep0020()) {
363 igep_gpio_leds[0].gpio = IGEP2_GPIO_LED0_RED;
364 igep_gpio_leds[1].gpio = IGEP2_GPIO_LED0_GREEN;
365 igep_gpio_leds[2].gpio = IGEP2_GPIO_LED1_RED;
366 } else {
367 igep_gpio_leds[0].gpio = IGEP3_GPIO_LED0_RED;
368 igep_gpio_leds[1].gpio = IGEP3_GPIO_LED0_GREEN;
369 igep_gpio_leds[2].gpio = IGEP3_GPIO_LED1_RED;
370 }
bee15390 371
fdfb03ba 372 if (gpio_request_array(igep_gpio_leds, ARRAY_SIZE(igep_gpio_leds))) {
bc593f5d
IG		 373 pr_warning("IGEP v2: Could not obtain leds gpios\n");
374 return;
375 }
bee15390 376
0d4ab9a5
MR		 377 for (i = 0; i < ARRAY_SIZE(igep_gpio_leds); i++)
378 gpio_export(igep_gpio_leds[i].gpio, 0);
bee15390
EBS		 379}
380#endif
381
bc593f5d
IG		 382static struct gpio igep2_twl_gpios[] = {
383 { -EINVAL, GPIOF_IN, "GPIO_EHCI_NOC" },
384 { -EINVAL, GPIOF_OUT_INIT_LOW, "GPIO_USBH_CPEN" },
385};
386
fdfb03ba 387static int igep_twl_gpio_setup(struct device *dev,
58e11162
EBS		 388 unsigned gpio, unsigned ngpio)
389{
bc593f5d
IG		 390 int ret;
391
58e11162
EBS		 392 /* gpio + 0 is "mmc0_cd" (input/IRQ) */
393 mmc[0].gpio_cd = gpio + 0;
3b972bf0 394 omap_hsmmc_late_init(mmc);
58e11162 395
bee15390
EBS		 396 /* TWL4030_GPIO_MAX + 1 == ledB (out, active low LED) */
397#if !defined(CONFIG_LEDS_GPIO) && !defined(CONFIG_LEDS_GPIO_MODULE)
0d4ab9a5
MR		 398 ret = gpio_request_one(gpio + TWL4030_GPIO_MAX + 1, GPIOF_OUT_INIT_HIGH,
399 "gpio-led:green:d1");
400 if (ret == 0)
bee15390 401 gpio_export(gpio + TWL4030_GPIO_MAX + 1, 0);
62d8e9e2 402 else
0d4ab9a5 403 pr_warning("IGEP: Could not obtain gpio GPIO_LED1_GREEN\n");
bee15390 404#else
0d4ab9a5 405 igep_gpio_leds[3].gpio = gpio + TWL4030_GPIO_MAX + 1;
bee15390 406#endif
58e11162 407
2a60997a
MR		 408 if (machine_is_igep0030())
409 return 0;
410
61e118dd
EBS		 411 /*
412 * REVISIT: need ehci-omap hooks for external VBUS
413 * power switch and overcurrent detect
414 */
bc593f5d 415 igep2_twl_gpios[0].gpio = gpio + 1;
61e118dd 416
bc593f5d
IG		 417 /* TWL4030_GPIO_MAX + 0 == ledA, GPIO_USBH_CPEN (out, active low) */
418 igep2_twl_gpios[1].gpio = gpio + TWL4030_GPIO_MAX;
419
420 ret = gpio_request_array(igep2_twl_gpios, ARRAY_SIZE(igep2_twl_gpios));
421 if (ret < 0)
61e118dd
EBS		 422 pr_err("IGEP2: Could not obtain gpio for USBH_CPEN");
423
58e11162
EBS		 424 return 0;
425};
426
fdfb03ba 427static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
bee15390 428 .use_leds = true,
fdfb03ba 429 .setup = igep_twl_gpio_setup,
58e11162
EBS		 430};
431
18cbc7d9
EBS		 432static int igep2_keymap[] = {
433 KEY(0, 0, KEY_LEFT),
434 KEY(0, 1, KEY_RIGHT),
435 KEY(0, 2, KEY_A),
436 KEY(0, 3, KEY_B),
437 KEY(1, 0, KEY_DOWN),
438 KEY(1, 1, KEY_UP),
439 KEY(1, 2, KEY_E),
440 KEY(1, 3, KEY_F),
441 KEY(2, 0, KEY_ENTER),
442 KEY(2, 1, KEY_I),
443 KEY(2, 2, KEY_J),
444 KEY(2, 3, KEY_K),
445 KEY(3, 0, KEY_M),
446 KEY(3, 1, KEY_N),
447 KEY(3, 2, KEY_O),
448 KEY(3, 3, KEY_P)
449};
450
451static struct matrix_keymap_data igep2_keymap_data = {
452 .keymap = igep2_keymap,
453 .keymap_size = ARRAY_SIZE(igep2_keymap),
454};
455
456static struct twl4030_keypad_data igep2_keypad_pdata = {
457 .keymap_data = &igep2_keymap_data,
458 .rows = 4,
459 .cols = 4,
460 .rep = 1,
461};
462
fdfb03ba 463static struct twl4030_platform_data igep_twldata = {
58e11162 464 /* platform_data for children goes here */
fdfb03ba 465 .gpio = &igep_twl4030_gpio_pdata,
fdfb03ba 466 .vmmc1 = &igep_vmmc1,
fdfb03ba 467 .vio = &igep_vio,
58e11162
EBS		 468};
469
91d139cf
EBS		 470static struct i2c_board_info __initdata igep2_i2c3_boardinfo[] = {
471 {
472 I2C_BOARD_INFO("eeprom", 0x50),
473 },
474};
475
fdfb03ba 476static void __init igep_i2c_init(void)
58e11162 477{
91d139cf
EBS		 478 int ret;
479
b2f44dc2
LP		 480 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB,
481 TWL_COMMON_REGULATOR_VPLL2);
482 igep_twldata.vpll2->constraints.apply_uV = true;
483 igep_twldata.vpll2->constraints.name = "VDVI";
827ed9ae 484
2a60997a
MR		 485 if (machine_is_igep0020()) {
486 /*
487 * Bus 3 is attached to the DVI port where devices like the
488 * pico DLP projector don't work reliably with 400kHz
489 */
490 ret = omap_register_i2c_bus(3, 100, igep2_i2c3_boardinfo,
491 ARRAY_SIZE(igep2_i2c3_boardinfo));
492 if (ret)
493 pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
494
2a60997a 495 igep_twldata.keypad = &igep2_keypad_pdata;
b252b0ef 496 /* Get common pmic data */
b2f44dc2 497 omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO, 0);
2a60997a 498 }
91d139cf 499
0d4ab9a5 500 omap3_pmic_init("twl4030", &igep_twldata);
58e11162
EBS		 501}
502
9c4d678e
RQ		 503static struct usbhs_phy_data igep2_phy_data[] __initdata = {
504 {
505 .port = 1,
506 .reset_gpio = IGEP2_GPIO_USBH_NRESET,
507 .vcc_gpio = -EINVAL,
508 },
509};
510
511static struct usbhs_phy_data igep3_phy_data[] __initdata = {
512 {
513 .port = 2,
514 .reset_gpio = IGEP3_GPIO_USBH_NRESET,
515 .vcc_gpio = -EINVAL,
516 },
517};
518
42973159 519static struct usbhs_omap_platform_data igep2_usbhs_bdata __initdata = {
181b250c 520 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
d0885486
EBS		 521};
522
42973159 523static struct usbhs_omap_platform_data igep3_usbhs_bdata __initdata = {
2a60997a 524 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
2a60997a
MR		 525};
526
ca5742bd
TL		 527#ifdef CONFIG_OMAP_MUX
528static struct omap_board_mux board_mux[] __initdata = {
e94eb1ac
EBS		 529 /* Display Sub System */
530 OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
531 OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
532 OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
533 OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
534 OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
535 OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
536 OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
537 OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
538 OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
539 OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
540 OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
541 OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
542 OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
543 OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
544 OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
545 OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
546 OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
547 OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
548 OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
549 OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
550 OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
551 OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
552 OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
553 OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
554 OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
555 OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
556 OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
557 OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
558 /* TFP410 PanelBus DVI Transmitte (GPIO_170) */
559 OMAP3_MUX(HDQ_SIO, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
a71eb61c
JMC		 560 /* SMSC9221 LAN Controller ETH IRQ (GPIO_176) */
561 OMAP3_MUX(MCSPI1_CS2, OMAP_MUX_MODE4 | OMAP_PIN_INPUT),
ca5742bd
TL		 562 { .reg_offset = OMAP_MUX_TERMINATOR },
563};
ca5742bd
TL		 564#endif
565
5a9fcc99 566#if defined(CONFIG_LIBERTAS_SDIO) || defined(CONFIG_LIBERTAS_SDIO_MODULE)
fdfb03ba 567static struct gpio igep_wlan_bt_gpios[] __initdata = {
bc593f5d
IG		 568 { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NPD" },
569 { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_WIFI_NRESET" },
570 { -EINVAL, GPIOF_OUT_INIT_HIGH, "GPIO_BT_NRESET" },
571};
5a9fcc99 572
fdfb03ba 573static void __init igep_wlan_bt_init(void)
5a9fcc99 574{
bc593f5d 575 int err;
5a9fcc99
EBS		 576
577 /* GPIO's for WLAN-BT combo depends on hardware revision */
578 if (hwrev == IGEP2_BOARD_HWREV_B) {
fdfb03ba
MR		 579 igep_wlan_bt_gpios[0].gpio = IGEP2_RB_GPIO_WIFI_NPD;
580 igep_wlan_bt_gpios[1].gpio = IGEP2_RB_GPIO_WIFI_NRESET;
581 igep_wlan_bt_gpios[2].gpio = IGEP2_RB_GPIO_BT_NRESET;
2a60997a 582 } else if (hwrev == IGEP2_BOARD_HWREV_C || machine_is_igep0030()) {
fdfb03ba
MR		 583 igep_wlan_bt_gpios[0].gpio = IGEP2_RC_GPIO_WIFI_NPD;
584 igep_wlan_bt_gpios[1].gpio = IGEP2_RC_GPIO_WIFI_NRESET;
585 igep_wlan_bt_gpios[2].gpio = IGEP2_RC_GPIO_BT_NRESET;
5a9fcc99
EBS		 586 } else
587 return;
588
cbf6bae1
AH		 589 /* Make sure that the GPIO pins are muxed correctly */
590 omap_mux_init_gpio(igep_wlan_bt_gpios[0].gpio, OMAP_PIN_OUTPUT);
591 omap_mux_init_gpio(igep_wlan_bt_gpios[1].gpio, OMAP_PIN_OUTPUT);
592 omap_mux_init_gpio(igep_wlan_bt_gpios[2].gpio, OMAP_PIN_OUTPUT);
593
fdfb03ba
MR		 594 err = gpio_request_array(igep_wlan_bt_gpios,
595 ARRAY_SIZE(igep_wlan_bt_gpios));
bc593f5d
IG		 596 if (err) {
597 pr_warning("IGEP2: Could not obtain WIFI/BT gpios\n");
598 return;
599 }
600
fdfb03ba
MR		 601 gpio_export(igep_wlan_bt_gpios[0].gpio, 0);
602 gpio_export(igep_wlan_bt_gpios[1].gpio, 0);
603 gpio_export(igep_wlan_bt_gpios[2].gpio, 0);
bc593f5d 604
fdfb03ba 605 gpio_set_value(igep_wlan_bt_gpios[1].gpio, 0);
bc593f5d 606 udelay(10);
fdfb03ba 607 gpio_set_value(igep_wlan_bt_gpios[1].gpio, 1);
5a9fcc99 608
5a9fcc99
EBS		 609}
610#else
fdfb03ba 611static inline void __init igep_wlan_bt_init(void) { }
5a9fcc99
EBS		 612#endif
613
5b3689f4
RD		 614static struct regulator_consumer_supply dummy_supplies[] = {
615 REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
616 REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
617};
618
fdfb03ba 619static void __init igep_init(void)
58e11162 620{
1a21932e 621 regulator_register_fixed(1, dummy_supplies, ARRAY_SIZE(dummy_supplies));
ca5742bd 622 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
3f8c48d9
EBS		 623
624 /* Get IGEP2 hardware revision */
625 igep2_get_revision();
3b972bf0
TL		 626
627 omap_hsmmc_init(mmc);
628
91d139cf 629 /* Register I2C busses and drivers */
fdfb03ba 630 igep_i2c_init();
68a531a1
JMC		 631 platform_device_register(&igep_vwlan_device);
632 omap3_igep2_display_init_of();
58e11162 633 omap_serial_init();
a4ca9dbe
TL		 634 omap_sdrc_init(m65kxxxxam_sdrc_params,
635 m65kxxxxam_sdrc_params);
51482be9 636 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
9e18630b 637 usb_musb_init(NULL);
58e11162 638
fdfb03ba
MR		 639 igep_flash_init();
640 igep_leds_init();
40234bf7 641 omap_twl4030_audio_init("igep2", NULL);
58e11162 642
5a9fcc99 643 /*
25985edc 644 * WLAN-BT combo module from MuRata which has a Marvell WLAN
5a9fcc99
EBS		 645 * (88W8686) + CSR Bluetooth chipset. Uses SDIO interface.
646 */
fdfb03ba 647 igep_wlan_bt_init();
c67b0d98 648
2a60997a 649 if (machine_is_igep0020()) {
2a60997a 650 igep2_init_smsc911x();
9c4d678e 651 usbhs_init_phys(igep2_phy_data, ARRAY_SIZE(igep2_phy_data));
2a60997a
MR		 652 usbhs_init(&igep2_usbhs_bdata);
653 } else {
9c4d678e 654 usbhs_init_phys(igep3_phy_data, ARRAY_SIZE(igep3_phy_data));
2a60997a
MR		 655 usbhs_init(&igep3_usbhs_bdata);
656 }
58e11162
EBS		 657}
658
58e11162 659MACHINE_START(IGEP0020, "IGEP v2 board")
5e52b435 660 .atag_offset = 0x100,
71ee7dad 661 .reserve = omap_reserve,
3dc3bad6 662 .map_io = omap3_map_io,
8f5b5a41 663 .init_early = omap35xx_init_early,
741e3a89 664 .init_irq = omap3_init_irq,
6b2f55d7 665 .handle_irq = omap3_intc_handle_irq,
fdfb03ba 666 .init_machine = igep_init,
bbd707ac 667 .init_late = omap35xx_init_late,
6bb27d73 668 .init_time = omap3_sync32k_timer_init,
187e3e06 669 .restart = omap3xxx_restart,
58e11162 670MACHINE_END
2a60997a
MR		 671
672MACHINE_START(IGEP0030, "IGEP OMAP3 module")
5e52b435 673 .atag_offset = 0x100,
2a60997a
MR		 674 .reserve = omap_reserve,
675 .map_io = omap3_map_io,
8f5b5a41 676 .init_early = omap35xx_init_early,
741e3a89 677 .init_irq = omap3_init_irq,
6b2f55d7 678 .handle_irq = omap3_intc_handle_irq,
2a60997a 679 .init_machine = igep_init,
bbd707ac 680 .init_late = omap35xx_init_late,
6bb27d73 681 .init_time = omap3_sync32k_timer_init,
187e3e06 682 .restart = omap3xxx_restart,
58e11162 683MACHINE_END
Linux 6.x block layer and io_uring tree(s)