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2886d128 MR |
1 | /* |
2 | * board-cm-t35.c (CompuLab CM-T35 module) | |
3 | * | |
4 | * Copyright (C) 2009 CompuLab, Ltd. | |
5 | * Author: Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License | |
9 | * version 2 as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, but | |
12 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA | |
19 | * 02110-1301 USA | |
20 | * | |
21 | */ | |
22 | ||
23 | #include <linux/kernel.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/input.h> | |
27 | #include <linux/input/matrix_keypad.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/gpio.h> | |
30 | ||
31 | #include <linux/i2c/at24.h> | |
ebeb53e1 | 32 | #include <linux/i2c/twl.h> |
2886d128 MR |
33 | #include <linux/regulator/machine.h> |
34 | ||
7f049ad1 MR |
35 | #include <linux/spi/spi.h> |
36 | #include <linux/spi/tdo24m.h> | |
37 | ||
2886d128 MR |
38 | #include <asm/mach-types.h> |
39 | #include <asm/mach/arch.h> | |
40 | #include <asm/mach/map.h> | |
41 | ||
42 | #include <plat/board.h> | |
43 | #include <plat/common.h> | |
2886d128 MR |
44 | #include <plat/nand.h> |
45 | #include <plat/gpmc.h> | |
46 | #include <plat/usb.h> | |
7f049ad1 | 47 | #include <plat/display.h> |
609c9ba2 | 48 | #include <plat/mcspi.h> |
2886d128 MR |
49 | |
50 | #include <mach/hardware.h> | |
51 | ||
ca5742bd | 52 | #include "mux.h" |
2886d128 | 53 | #include "sdram-micron-mt46h32m32lf-6.h" |
d02a900b | 54 | #include "hsmmc.h" |
2886d128 MR |
55 | |
56 | #define CM_T35_GPIO_PENDOWN 57 | |
57 | ||
58 | #define CM_T35_SMSC911X_CS 5 | |
59 | #define CM_T35_SMSC911X_GPIO 163 | |
60 | #define SB_T35_SMSC911X_CS 4 | |
61 | #define SB_T35_SMSC911X_GPIO 65 | |
62 | ||
63 | #define NAND_BLOCK_SIZE SZ_128K | |
64 | #define GPMC_CS0_BASE 0x60 | |
65 | #define GPMC_CS0_BASE_ADDR (OMAP34XX_GPMC_VIRT + GPMC_CS0_BASE) | |
66 | ||
67 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) | |
68 | #include <linux/smsc911x.h> | |
69 | ||
70 | static struct smsc911x_platform_config cm_t35_smsc911x_config = { | |
71 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
72 | .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN, | |
73 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
74 | .phy_interface = PHY_INTERFACE_MODE_MII, | |
75 | }; | |
76 | ||
77 | static struct resource cm_t35_smsc911x_resources[] = { | |
78 | { | |
79 | .flags = IORESOURCE_MEM, | |
80 | }, | |
81 | { | |
82 | .start = OMAP_GPIO_IRQ(CM_T35_SMSC911X_GPIO), | |
83 | .end = OMAP_GPIO_IRQ(CM_T35_SMSC911X_GPIO), | |
84 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
85 | }, | |
86 | }; | |
87 | ||
88 | static struct platform_device cm_t35_smsc911x_device = { | |
89 | .name = "smsc911x", | |
90 | .id = 0, | |
91 | .num_resources = ARRAY_SIZE(cm_t35_smsc911x_resources), | |
92 | .resource = cm_t35_smsc911x_resources, | |
93 | .dev = { | |
94 | .platform_data = &cm_t35_smsc911x_config, | |
95 | }, | |
96 | }; | |
97 | ||
98 | static struct resource sb_t35_smsc911x_resources[] = { | |
99 | { | |
100 | .flags = IORESOURCE_MEM, | |
101 | }, | |
102 | { | |
103 | .start = OMAP_GPIO_IRQ(SB_T35_SMSC911X_GPIO), | |
104 | .end = OMAP_GPIO_IRQ(SB_T35_SMSC911X_GPIO), | |
105 | .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL, | |
106 | }, | |
107 | }; | |
108 | ||
109 | static struct platform_device sb_t35_smsc911x_device = { | |
110 | .name = "smsc911x", | |
111 | .id = 1, | |
112 | .num_resources = ARRAY_SIZE(sb_t35_smsc911x_resources), | |
113 | .resource = sb_t35_smsc911x_resources, | |
114 | .dev = { | |
115 | .platform_data = &cm_t35_smsc911x_config, | |
116 | }, | |
117 | }; | |
118 | ||
119 | static void __init cm_t35_init_smsc911x(struct platform_device *dev, | |
120 | int cs, int irq_gpio) | |
121 | { | |
122 | unsigned long cs_mem_base; | |
123 | ||
124 | if (gpmc_cs_request(cs, SZ_16M, &cs_mem_base) < 0) { | |
125 | pr_err("CM-T35: Failed request for GPMC mem for smsc911x\n"); | |
126 | return; | |
127 | } | |
128 | ||
129 | dev->resource[0].start = cs_mem_base + 0x0; | |
130 | dev->resource[0].end = cs_mem_base + 0xff; | |
131 | ||
132 | if ((gpio_request(irq_gpio, "ETH IRQ") == 0) && | |
133 | (gpio_direction_input(irq_gpio) == 0)) { | |
134 | gpio_export(irq_gpio, 0); | |
135 | } else { | |
136 | pr_err("CM-T35: could not obtain gpio for SMSC911X IRQ\n"); | |
137 | return; | |
138 | } | |
139 | ||
140 | platform_device_register(dev); | |
141 | } | |
142 | ||
143 | static void __init cm_t35_init_ethernet(void) | |
144 | { | |
145 | cm_t35_init_smsc911x(&cm_t35_smsc911x_device, | |
146 | CM_T35_SMSC911X_CS, CM_T35_SMSC911X_GPIO); | |
147 | cm_t35_init_smsc911x(&sb_t35_smsc911x_device, | |
148 | SB_T35_SMSC911X_CS, SB_T35_SMSC911X_GPIO); | |
149 | } | |
150 | #else | |
151 | static inline void __init cm_t35_init_ethernet(void) { return; } | |
152 | #endif | |
153 | ||
154 | #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) | |
155 | #include <linux/leds.h> | |
156 | ||
157 | static struct gpio_led cm_t35_leds[] = { | |
158 | [0] = { | |
159 | .gpio = 186, | |
160 | .name = "cm-t35:green", | |
161 | .default_trigger = "heartbeat", | |
162 | .active_low = 0, | |
163 | }, | |
164 | }; | |
165 | ||
166 | static struct gpio_led_platform_data cm_t35_led_pdata = { | |
167 | .num_leds = ARRAY_SIZE(cm_t35_leds), | |
168 | .leds = cm_t35_leds, | |
169 | }; | |
170 | ||
171 | static struct platform_device cm_t35_led_device = { | |
172 | .name = "leds-gpio", | |
173 | .id = -1, | |
174 | .dev = { | |
175 | .platform_data = &cm_t35_led_pdata, | |
176 | }, | |
177 | }; | |
178 | ||
179 | static void __init cm_t35_init_led(void) | |
180 | { | |
181 | platform_device_register(&cm_t35_led_device); | |
182 | } | |
183 | #else | |
184 | static inline void cm_t35_init_led(void) {} | |
185 | #endif | |
186 | ||
187 | #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) | |
188 | #include <linux/mtd/mtd.h> | |
189 | #include <linux/mtd/nand.h> | |
190 | #include <linux/mtd/partitions.h> | |
191 | ||
192 | static struct mtd_partition cm_t35_nand_partitions[] = { | |
193 | { | |
194 | .name = "xloader", | |
195 | .offset = 0, /* Offset = 0x00000 */ | |
196 | .size = 4 * NAND_BLOCK_SIZE, | |
197 | .mask_flags = MTD_WRITEABLE | |
198 | }, | |
199 | { | |
200 | .name = "uboot", | |
201 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
202 | .size = 15 * NAND_BLOCK_SIZE, | |
203 | }, | |
204 | { | |
205 | .name = "uboot environment", | |
206 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | |
207 | .size = 2 * NAND_BLOCK_SIZE, | |
208 | }, | |
209 | { | |
210 | .name = "linux", | |
211 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */ | |
212 | .size = 32 * NAND_BLOCK_SIZE, | |
213 | }, | |
214 | { | |
215 | .name = "rootfs", | |
216 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */ | |
217 | .size = MTDPART_SIZ_FULL, | |
218 | }, | |
219 | }; | |
220 | ||
221 | static struct omap_nand_platform_data cm_t35_nand_data = { | |
222 | .parts = cm_t35_nand_partitions, | |
223 | .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), | |
224 | .dma_channel = -1, /* disable DMA in OMAP NAND driver */ | |
225 | .cs = 0, | |
226 | .gpmc_cs_baseaddr = (void __iomem *)GPMC_CS0_BASE_ADDR, | |
227 | .gpmc_baseaddr = (void __iomem *)OMAP34XX_GPMC_VIRT, | |
228 | ||
229 | }; | |
230 | ||
231 | static struct resource cm_t35_nand_resource = { | |
232 | .flags = IORESOURCE_MEM, | |
233 | }; | |
234 | ||
235 | static struct platform_device cm_t35_nand_device = { | |
236 | .name = "omap2-nand", | |
237 | .id = -1, | |
238 | .num_resources = 1, | |
239 | .resource = &cm_t35_nand_resource, | |
240 | .dev = { | |
241 | .platform_data = &cm_t35_nand_data, | |
242 | }, | |
243 | }; | |
244 | ||
245 | static void __init cm_t35_init_nand(void) | |
246 | { | |
247 | if (platform_device_register(&cm_t35_nand_device) < 0) | |
248 | pr_err("CM-T35: Unable to register NAND device\n"); | |
249 | } | |
250 | #else | |
251 | static inline void cm_t35_init_nand(void) {} | |
252 | #endif | |
253 | ||
254 | #if defined(CONFIG_TOUCHSCREEN_ADS7846) || \ | |
255 | defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE) | |
2886d128 MR |
256 | #include <linux/spi/ads7846.h> |
257 | ||
258 | #include <plat/mcspi.h> | |
259 | ||
260 | static struct omap2_mcspi_device_config ads7846_mcspi_config = { | |
261 | .turbo_mode = 0, | |
262 | .single_channel = 1, /* 0: slave, 1: master */ | |
263 | }; | |
264 | ||
265 | static int ads7846_get_pendown_state(void) | |
266 | { | |
267 | return !gpio_get_value(CM_T35_GPIO_PENDOWN); | |
268 | } | |
269 | ||
270 | static struct ads7846_platform_data ads7846_config = { | |
271 | .x_max = 0x0fff, | |
272 | .y_max = 0x0fff, | |
273 | .x_plate_ohms = 180, | |
274 | .pressure_max = 255, | |
275 | .debounce_max = 10, | |
276 | .debounce_tol = 3, | |
277 | .debounce_rep = 1, | |
278 | .get_pendown_state = ads7846_get_pendown_state, | |
279 | .keep_vref_on = 1, | |
280 | }; | |
281 | ||
282 | static struct spi_board_info cm_t35_spi_board_info[] __initdata = { | |
283 | { | |
284 | .modalias = "ads7846", | |
285 | .bus_num = 1, | |
286 | .chip_select = 0, | |
287 | .max_speed_hz = 1500000, | |
288 | .controller_data = &ads7846_mcspi_config, | |
289 | .irq = OMAP_GPIO_IRQ(CM_T35_GPIO_PENDOWN), | |
290 | .platform_data = &ads7846_config, | |
291 | }, | |
292 | }; | |
293 | ||
294 | static void __init cm_t35_init_ads7846(void) | |
295 | { | |
296 | if ((gpio_request(CM_T35_GPIO_PENDOWN, "ADS7846_PENDOWN") == 0) && | |
297 | (gpio_direction_input(CM_T35_GPIO_PENDOWN) == 0)) { | |
298 | gpio_export(CM_T35_GPIO_PENDOWN, 0); | |
299 | } else { | |
300 | pr_err("CM-T35: could not obtain gpio for ADS7846_PENDOWN\n"); | |
301 | return; | |
302 | } | |
303 | ||
304 | spi_register_board_info(cm_t35_spi_board_info, | |
305 | ARRAY_SIZE(cm_t35_spi_board_info)); | |
306 | } | |
307 | #else | |
308 | static inline void cm_t35_init_ads7846(void) {} | |
309 | #endif | |
310 | ||
7f049ad1 MR |
311 | #define CM_T35_LCD_EN_GPIO 157 |
312 | #define CM_T35_LCD_BL_GPIO 58 | |
313 | #define CM_T35_DVI_EN_GPIO 54 | |
314 | ||
315 | static int lcd_bl_gpio; | |
316 | static int lcd_en_gpio; | |
317 | static int dvi_en_gpio; | |
318 | ||
319 | static int lcd_enabled; | |
320 | static int dvi_enabled; | |
321 | ||
322 | static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) | |
323 | { | |
324 | if (dvi_enabled) { | |
325 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | |
326 | return -EINVAL; | |
327 | } | |
328 | ||
329 | gpio_set_value(lcd_en_gpio, 1); | |
330 | gpio_set_value(lcd_bl_gpio, 1); | |
331 | ||
332 | lcd_enabled = 1; | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) | |
338 | { | |
339 | lcd_enabled = 0; | |
340 | ||
341 | gpio_set_value(lcd_bl_gpio, 0); | |
342 | gpio_set_value(lcd_en_gpio, 0); | |
343 | } | |
344 | ||
345 | static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) | |
346 | { | |
347 | if (lcd_enabled) { | |
348 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | |
349 | return -EINVAL; | |
350 | } | |
351 | ||
352 | gpio_set_value(dvi_en_gpio, 0); | |
353 | dvi_enabled = 1; | |
354 | ||
355 | return 0; | |
356 | } | |
357 | ||
358 | static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) | |
359 | { | |
360 | gpio_set_value(dvi_en_gpio, 1); | |
361 | dvi_enabled = 0; | |
362 | } | |
363 | ||
364 | static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) | |
365 | { | |
366 | return 0; | |
367 | } | |
368 | ||
369 | static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) | |
370 | { | |
371 | } | |
372 | ||
373 | static struct omap_dss_device cm_t35_lcd_device = { | |
374 | .name = "lcd", | |
375 | .driver_name = "toppoly_tdo35s_panel", | |
376 | .type = OMAP_DISPLAY_TYPE_DPI, | |
377 | .phy.dpi.data_lines = 18, | |
378 | .platform_enable = cm_t35_panel_enable_lcd, | |
379 | .platform_disable = cm_t35_panel_disable_lcd, | |
380 | }; | |
381 | ||
382 | static struct omap_dss_device cm_t35_dvi_device = { | |
383 | .name = "dvi", | |
384 | .driver_name = "generic_panel", | |
385 | .type = OMAP_DISPLAY_TYPE_DPI, | |
386 | .phy.dpi.data_lines = 24, | |
387 | .platform_enable = cm_t35_panel_enable_dvi, | |
388 | .platform_disable = cm_t35_panel_disable_dvi, | |
389 | }; | |
390 | ||
391 | static struct omap_dss_device cm_t35_tv_device = { | |
392 | .name = "tv", | |
393 | .driver_name = "venc", | |
394 | .type = OMAP_DISPLAY_TYPE_VENC, | |
395 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
396 | .platform_enable = cm_t35_panel_enable_tv, | |
397 | .platform_disable = cm_t35_panel_disable_tv, | |
398 | }; | |
399 | ||
400 | static struct omap_dss_device *cm_t35_dss_devices[] = { | |
401 | &cm_t35_lcd_device, | |
402 | &cm_t35_dvi_device, | |
403 | &cm_t35_tv_device, | |
404 | }; | |
405 | ||
406 | static struct omap_dss_board_info cm_t35_dss_data = { | |
407 | .num_devices = ARRAY_SIZE(cm_t35_dss_devices), | |
408 | .devices = cm_t35_dss_devices, | |
409 | .default_device = &cm_t35_dvi_device, | |
410 | }; | |
411 | ||
412 | static struct platform_device cm_t35_dss_device = { | |
413 | .name = "omapdss", | |
414 | .id = -1, | |
415 | .dev = { | |
416 | .platform_data = &cm_t35_dss_data, | |
417 | }, | |
418 | }; | |
419 | ||
420 | static struct omap2_mcspi_device_config tdo24m_mcspi_config = { | |
421 | .turbo_mode = 0, | |
422 | .single_channel = 1, /* 0: slave, 1: master */ | |
423 | }; | |
424 | ||
425 | static struct tdo24m_platform_data tdo24m_config = { | |
426 | .model = TDO35S, | |
427 | }; | |
428 | ||
429 | static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { | |
430 | { | |
431 | .modalias = "tdo24m", | |
432 | .bus_num = 4, | |
433 | .chip_select = 0, | |
434 | .max_speed_hz = 1000000, | |
435 | .controller_data = &tdo24m_mcspi_config, | |
436 | .platform_data = &tdo24m_config, | |
437 | }, | |
438 | }; | |
439 | ||
440 | static void __init cm_t35_init_display(void) | |
441 | { | |
442 | int err; | |
443 | ||
444 | lcd_en_gpio = CM_T35_LCD_EN_GPIO; | |
445 | lcd_bl_gpio = CM_T35_LCD_BL_GPIO; | |
446 | dvi_en_gpio = CM_T35_DVI_EN_GPIO; | |
447 | ||
448 | spi_register_board_info(cm_t35_lcd_spi_board_info, | |
449 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); | |
450 | ||
451 | err = gpio_request(lcd_en_gpio, "LCD RST"); | |
452 | if (err) { | |
453 | pr_err("CM-T35: failed to get LCD reset GPIO\n"); | |
454 | goto out; | |
455 | } | |
456 | ||
457 | err = gpio_request(lcd_bl_gpio, "LCD BL"); | |
458 | if (err) { | |
459 | pr_err("CM-T35: failed to get LCD backlight control GPIO\n"); | |
460 | goto err_lcd_bl; | |
461 | } | |
462 | ||
463 | err = gpio_request(dvi_en_gpio, "DVI EN"); | |
464 | if (err) { | |
465 | pr_err("CM-T35: failed to get DVI reset GPIO\n"); | |
466 | goto err_dvi_en; | |
467 | } | |
468 | ||
469 | gpio_export(lcd_en_gpio, 0); | |
470 | gpio_export(lcd_bl_gpio, 0); | |
471 | gpio_export(dvi_en_gpio, 0); | |
472 | gpio_direction_output(lcd_en_gpio, 0); | |
473 | gpio_direction_output(lcd_bl_gpio, 0); | |
474 | gpio_direction_output(dvi_en_gpio, 1); | |
475 | ||
476 | msleep(50); | |
477 | gpio_set_value(lcd_en_gpio, 1); | |
478 | ||
479 | err = platform_device_register(&cm_t35_dss_device); | |
480 | if (err) { | |
481 | pr_err("CM-T35: failed to register DSS device\n"); | |
482 | goto err_dev_reg; | |
483 | } | |
484 | ||
485 | return; | |
486 | ||
487 | err_dev_reg: | |
488 | gpio_free(dvi_en_gpio); | |
489 | err_dvi_en: | |
490 | gpio_free(lcd_bl_gpio); | |
491 | err_lcd_bl: | |
492 | gpio_free(lcd_en_gpio); | |
493 | out: | |
494 | ||
495 | return; | |
496 | } | |
497 | ||
2886d128 MR |
498 | static struct regulator_consumer_supply cm_t35_vmmc1_supply = { |
499 | .supply = "vmmc", | |
500 | }; | |
501 | ||
502 | static struct regulator_consumer_supply cm_t35_vsim_supply = { | |
503 | .supply = "vmmc_aux", | |
504 | }; | |
505 | ||
7f049ad1 MR |
506 | static struct regulator_consumer_supply cm_t35_vdac_supply = { |
507 | .supply = "vdda_dac", | |
508 | .dev = &cm_t35_dss_device.dev, | |
509 | }; | |
510 | ||
511 | static struct regulator_consumer_supply cm_t35_vdvi_supply = { | |
512 | .supply = "vdvi", | |
513 | .dev = &cm_t35_dss_device.dev, | |
514 | }; | |
515 | ||
2886d128 MR |
516 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
517 | static struct regulator_init_data cm_t35_vmmc1 = { | |
518 | .constraints = { | |
519 | .min_uV = 1850000, | |
520 | .max_uV = 3150000, | |
521 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
522 | | REGULATOR_MODE_STANDBY, | |
523 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
524 | | REGULATOR_CHANGE_MODE | |
525 | | REGULATOR_CHANGE_STATUS, | |
526 | }, | |
527 | .num_consumer_supplies = 1, | |
528 | .consumer_supplies = &cm_t35_vmmc1_supply, | |
529 | }; | |
530 | ||
531 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | |
532 | static struct regulator_init_data cm_t35_vsim = { | |
533 | .constraints = { | |
534 | .min_uV = 1800000, | |
535 | .max_uV = 3000000, | |
536 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
537 | | REGULATOR_MODE_STANDBY, | |
538 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
539 | | REGULATOR_CHANGE_MODE | |
540 | | REGULATOR_CHANGE_STATUS, | |
541 | }, | |
542 | .num_consumer_supplies = 1, | |
543 | .consumer_supplies = &cm_t35_vsim_supply, | |
544 | }; | |
545 | ||
7f049ad1 MR |
546 | /* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */ |
547 | static struct regulator_init_data cm_t35_vdac = { | |
548 | .constraints = { | |
549 | .min_uV = 1800000, | |
550 | .max_uV = 1800000, | |
551 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
552 | | REGULATOR_MODE_STANDBY, | |
553 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
554 | | REGULATOR_CHANGE_STATUS, | |
555 | }, | |
556 | .num_consumer_supplies = 1, | |
557 | .consumer_supplies = &cm_t35_vdac_supply, | |
558 | }; | |
559 | ||
560 | /* VPLL2 for digital video outputs */ | |
561 | static struct regulator_init_data cm_t35_vpll2 = { | |
562 | .constraints = { | |
563 | .name = "VDVI", | |
564 | .min_uV = 1800000, | |
565 | .max_uV = 1800000, | |
566 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
567 | | REGULATOR_MODE_STANDBY, | |
568 | .valid_ops_mask = REGULATOR_CHANGE_MODE | |
569 | | REGULATOR_CHANGE_STATUS, | |
570 | }, | |
571 | .num_consumer_supplies = 1, | |
572 | .consumer_supplies = &cm_t35_vdvi_supply, | |
573 | }; | |
574 | ||
2886d128 MR |
575 | static struct twl4030_usb_data cm_t35_usb_data = { |
576 | .usb_mode = T2_USB_MODE_ULPI, | |
577 | }; | |
578 | ||
579 | static int cm_t35_keymap[] = { | |
580 | KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), | |
581 | KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), | |
582 | KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), | |
583 | }; | |
584 | ||
585 | static struct matrix_keymap_data cm_t35_keymap_data = { | |
586 | .keymap = cm_t35_keymap, | |
587 | .keymap_size = ARRAY_SIZE(cm_t35_keymap), | |
588 | }; | |
589 | ||
590 | static struct twl4030_keypad_data cm_t35_kp_data = { | |
591 | .keymap_data = &cm_t35_keymap_data, | |
592 | .rows = 3, | |
593 | .cols = 3, | |
594 | .rep = 1, | |
595 | }; | |
596 | ||
68ff0423 | 597 | static struct omap2_hsmmc_info mmc[] = { |
2886d128 MR |
598 | { |
599 | .mmc = 1, | |
600 | .wires = 4, | |
601 | .gpio_cd = -EINVAL, | |
602 | .gpio_wp = -EINVAL, | |
603 | ||
604 | }, | |
605 | { | |
606 | .mmc = 2, | |
607 | .wires = 4, | |
608 | .transceiver = 1, | |
609 | .gpio_cd = -EINVAL, | |
610 | .gpio_wp = -EINVAL, | |
611 | .ocr_mask = 0x00100000, /* 3.3V */ | |
612 | }, | |
613 | {} /* Terminator */ | |
614 | }; | |
615 | ||
6f69a181 | 616 | static struct ehci_hcd_omap_platform_data ehci_pdata __initdata = { |
2886d128 MR |
617 | .port_mode[0] = EHCI_HCD_OMAP_MODE_PHY, |
618 | .port_mode[1] = EHCI_HCD_OMAP_MODE_PHY, | |
619 | .port_mode[2] = EHCI_HCD_OMAP_MODE_UNKNOWN, | |
620 | ||
621 | .phy_reset = true, | |
622 | .reset_gpio_port[0] = -EINVAL, | |
623 | .reset_gpio_port[1] = -EINVAL, | |
624 | .reset_gpio_port[2] = -EINVAL | |
625 | }; | |
626 | ||
627 | static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, | |
628 | unsigned ngpio) | |
629 | { | |
630 | int wlan_rst = gpio + 2; | |
631 | ||
632 | if ((gpio_request(wlan_rst, "WLAN RST") == 0) && | |
633 | (gpio_direction_output(wlan_rst, 1) == 0)) { | |
634 | gpio_export(wlan_rst, 0); | |
635 | ||
636 | udelay(10); | |
637 | gpio_set_value(wlan_rst, 0); | |
638 | udelay(10); | |
639 | gpio_set_value(wlan_rst, 1); | |
640 | } else { | |
641 | pr_err("CM-T35: could not obtain gpio for WiFi reset\n"); | |
642 | } | |
643 | ||
644 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | |
645 | mmc[0].gpio_cd = gpio + 0; | |
68ff0423 | 646 | omap2_hsmmc_init(mmc); |
2886d128 MR |
647 | |
648 | /* link regulators to MMC adapters */ | |
649 | cm_t35_vmmc1_supply.dev = mmc[0].dev; | |
650 | cm_t35_vsim_supply.dev = mmc[0].dev; | |
651 | ||
652 | /* setup USB with proper PHY reset GPIOs */ | |
653 | ehci_pdata.reset_gpio_port[0] = gpio + 6; | |
654 | ehci_pdata.reset_gpio_port[1] = gpio + 7; | |
655 | ||
656 | usb_ehci_init(&ehci_pdata); | |
657 | ||
658 | return 0; | |
659 | } | |
660 | ||
661 | static struct twl4030_gpio_platform_data cm_t35_gpio_data = { | |
662 | .gpio_base = OMAP_MAX_GPIO_LINES, | |
663 | .irq_base = TWL4030_GPIO_IRQ_BASE, | |
664 | .irq_end = TWL4030_GPIO_IRQ_END, | |
665 | .setup = cm_t35_twl_gpio_setup, | |
666 | }; | |
667 | ||
668 | static struct twl4030_platform_data cm_t35_twldata = { | |
669 | .irq_base = TWL4030_IRQ_BASE, | |
670 | .irq_end = TWL4030_IRQ_END, | |
671 | ||
672 | /* platform_data for children goes here */ | |
673 | .keypad = &cm_t35_kp_data, | |
674 | .usb = &cm_t35_usb_data, | |
675 | .gpio = &cm_t35_gpio_data, | |
676 | .vmmc1 = &cm_t35_vmmc1, | |
677 | .vsim = &cm_t35_vsim, | |
7f049ad1 MR |
678 | .vdac = &cm_t35_vdac, |
679 | .vpll2 = &cm_t35_vpll2, | |
2886d128 MR |
680 | }; |
681 | ||
682 | static struct i2c_board_info __initdata cm_t35_i2c_boardinfo[] = { | |
683 | { | |
684 | I2C_BOARD_INFO("tps65930", 0x48), | |
685 | .flags = I2C_CLIENT_WAKE, | |
686 | .irq = INT_34XX_SYS_NIRQ, | |
687 | .platform_data = &cm_t35_twldata, | |
688 | }, | |
689 | }; | |
690 | ||
691 | static void __init cm_t35_init_i2c(void) | |
692 | { | |
693 | omap_register_i2c_bus(1, 2600, cm_t35_i2c_boardinfo, | |
694 | ARRAY_SIZE(cm_t35_i2c_boardinfo)); | |
695 | } | |
696 | ||
697 | static struct omap_board_config_kernel cm_t35_config[] __initdata = { | |
698 | }; | |
699 | ||
700 | static void __init cm_t35_init_irq(void) | |
701 | { | |
702 | omap_board_config = cm_t35_config; | |
703 | omap_board_config_size = ARRAY_SIZE(cm_t35_config); | |
704 | ||
705 | omap2_init_common_hw(mt46h32m32lf6_sdrc_params, | |
706 | mt46h32m32lf6_sdrc_params); | |
707 | omap_init_irq(); | |
708 | omap_gpio_init(); | |
709 | } | |
710 | ||
711 | static void __init cm_t35_map_io(void) | |
712 | { | |
c573bcf9 | 713 | omap2_set_globals_3xxx(); |
6fbd55d0 | 714 | omap34xx_map_common_io(); |
2886d128 MR |
715 | } |
716 | ||
ca5742bd | 717 | static struct omap_board_mux board_mux[] __initdata = { |
edc961a2 MR |
718 | /* nCS and IRQ for CM-T35 ethernet */ |
719 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), | |
720 | OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
721 | ||
722 | /* nCS and IRQ for SB-T35 ethernet */ | |
723 | OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0), | |
724 | OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
725 | ||
726 | /* PENDOWN GPIO */ | |
727 | OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), | |
728 | ||
729 | /* mUSB */ | |
730 | OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
731 | OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
732 | OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
733 | OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
734 | OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
735 | OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
736 | OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
737 | OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
738 | OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
739 | OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
740 | OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
741 | OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
742 | ||
743 | /* MMC 2 */ | |
744 | OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
745 | OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
746 | OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
747 | OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
748 | ||
749 | /* McSPI 1 */ | |
750 | OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
751 | OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
752 | OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
753 | OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | |
754 | ||
755 | /* McSPI 4 */ | |
756 | OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
757 | OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
758 | OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
759 | OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), | |
760 | ||
761 | /* McBSP 2 */ | |
762 | OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
763 | OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
764 | OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
765 | OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
766 | ||
767 | /* serial ports */ | |
768 | OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
769 | OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
770 | OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
771 | OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
772 | ||
773 | /* DSS */ | |
774 | OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
775 | OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
776 | OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
777 | OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
778 | OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
779 | OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
780 | OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
781 | OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
782 | OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
783 | OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
784 | OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
785 | OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
786 | OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
787 | OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
788 | OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
789 | OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
790 | OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
791 | OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
792 | OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
793 | OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
794 | OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
795 | OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
796 | OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
797 | OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
798 | OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
799 | OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
800 | OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
801 | OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
802 | ||
7f049ad1 MR |
803 | /* display controls */ |
804 | OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
805 | OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
806 | OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
807 | ||
edc961a2 MR |
808 | /* TPS IRQ */ |
809 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ | |
810 | OMAP_PIN_INPUT_PULLUP), | |
811 | ||
ca5742bd TL |
812 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
813 | }; | |
ca5742bd | 814 | |
884b8369 MM |
815 | static struct omap_musb_board_data musb_board_data = { |
816 | .interface_type = MUSB_INTERFACE_ULPI, | |
817 | .mode = MUSB_OTG, | |
818 | .power = 100, | |
819 | }; | |
820 | ||
2886d128 MR |
821 | static void __init cm_t35_init(void) |
822 | { | |
ca5742bd | 823 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
2886d128 MR |
824 | omap_serial_init(); |
825 | cm_t35_init_i2c(); | |
826 | cm_t35_init_nand(); | |
827 | cm_t35_init_ads7846(); | |
828 | cm_t35_init_ethernet(); | |
829 | cm_t35_init_led(); | |
7f049ad1 | 830 | cm_t35_init_display(); |
2886d128 | 831 | |
884b8369 | 832 | usb_musb_init(&musb_board_data); |
2886d128 MR |
833 | } |
834 | ||
835 | MACHINE_START(CM_T35, "Compulab CM-T35") | |
836 | .phys_io = 0x48000000, | |
837 | .io_pg_offst = ((0xd8000000) >> 18) & 0xfffc, | |
838 | .boot_params = 0x80000100, | |
839 | .map_io = cm_t35_map_io, | |
71ee7dad | 840 | .reserve = omap_reserve, |
2886d128 MR |
841 | .init_irq = cm_t35_init_irq, |
842 | .init_machine = cm_t35_init, | |
843 | .timer = &omap_timer, | |
844 | MACHINE_END |