Commit | Line | Data |
---|---|---|
2886d128 | 1 | /* |
c3146974 | 2 | * CompuLab CM-T35/CM-T3730 modules support |
2886d128 | 3 | * |
d12c2e28 IG |
4 | * Copyright (C) 2009-2011 CompuLab, Ltd. |
5 | * Authors: Mike Rapoport <mike@compulab.co.il> | |
6 | * Igor Grinberg <grinberg@compulab.co.il> | |
2886d128 MR |
7 | * |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * version 2 as published by the Free Software Foundation. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but | |
13 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
15 | * General Public License for more details. | |
16 | * | |
2886d128 MR |
17 | */ |
18 | ||
19 | #include <linux/kernel.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/platform_device.h> | |
22 | #include <linux/input.h> | |
23 | #include <linux/input/matrix_keypad.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/gpio.h> | |
26 | ||
27 | #include <linux/i2c/at24.h> | |
ebeb53e1 | 28 | #include <linux/i2c/twl.h> |
2886d128 | 29 | #include <linux/regulator/machine.h> |
3a63833e | 30 | #include <linux/mmc/host.h> |
2886d128 | 31 | |
7f049ad1 MR |
32 | #include <linux/spi/spi.h> |
33 | #include <linux/spi/tdo24m.h> | |
34 | ||
2886d128 MR |
35 | #include <asm/mach-types.h> |
36 | #include <asm/mach/arch.h> | |
37 | #include <asm/mach/map.h> | |
38 | ||
39 | #include <plat/board.h> | |
4e65331c | 40 | #include "common.h" |
2886d128 MR |
41 | #include <plat/nand.h> |
42 | #include <plat/gpmc.h> | |
43 | #include <plat/usb.h> | |
a0b38cc4 | 44 | #include <video/omapdss.h> |
f8ae2f08 | 45 | #include <video/omap-panel-generic-dpi.h> |
1d7a8654 | 46 | #include <video/omap-panel-dvi.h> |
609c9ba2 | 47 | #include <plat/mcspi.h> |
2886d128 MR |
48 | |
49 | #include <mach/hardware.h> | |
50 | ||
ca5742bd | 51 | #include "mux.h" |
2886d128 | 52 | #include "sdram-micron-mt46h32m32lf-6.h" |
d02a900b | 53 | #include "hsmmc.h" |
96974a24 | 54 | #include "common-board-devices.h" |
2886d128 MR |
55 | |
56 | #define CM_T35_GPIO_PENDOWN 57 | |
57 | ||
58 | #define CM_T35_SMSC911X_CS 5 | |
59 | #define CM_T35_SMSC911X_GPIO 163 | |
60 | #define SB_T35_SMSC911X_CS 4 | |
61 | #define SB_T35_SMSC911X_GPIO 65 | |
62 | ||
2886d128 MR |
63 | #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) |
64 | #include <linux/smsc911x.h> | |
21b42731 | 65 | #include <plat/gpmc-smsc911x.h> |
2886d128 | 66 | |
21b42731 | 67 | static struct omap_smsc911x_platform_data cm_t35_smsc911x_cfg = { |
2886d128 | 68 | .id = 0, |
21b42731 MR |
69 | .cs = CM_T35_SMSC911X_CS, |
70 | .gpio_irq = CM_T35_SMSC911X_GPIO, | |
71 | .gpio_reset = -EINVAL, | |
72 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
2886d128 MR |
73 | }; |
74 | ||
21b42731 | 75 | static struct omap_smsc911x_platform_data sb_t35_smsc911x_cfg = { |
2886d128 | 76 | .id = 1, |
21b42731 MR |
77 | .cs = SB_T35_SMSC911X_CS, |
78 | .gpio_irq = SB_T35_SMSC911X_GPIO, | |
79 | .gpio_reset = -EINVAL, | |
80 | .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS, | |
2886d128 MR |
81 | }; |
82 | ||
2886d128 MR |
83 | static void __init cm_t35_init_ethernet(void) |
84 | { | |
21b42731 MR |
85 | gpmc_smsc911x_init(&cm_t35_smsc911x_cfg); |
86 | gpmc_smsc911x_init(&sb_t35_smsc911x_cfg); | |
2886d128 MR |
87 | } |
88 | #else | |
89 | static inline void __init cm_t35_init_ethernet(void) { return; } | |
90 | #endif | |
91 | ||
92 | #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) | |
93 | #include <linux/leds.h> | |
94 | ||
95 | static struct gpio_led cm_t35_leds[] = { | |
96 | [0] = { | |
97 | .gpio = 186, | |
98 | .name = "cm-t35:green", | |
99 | .default_trigger = "heartbeat", | |
100 | .active_low = 0, | |
101 | }, | |
102 | }; | |
103 | ||
104 | static struct gpio_led_platform_data cm_t35_led_pdata = { | |
105 | .num_leds = ARRAY_SIZE(cm_t35_leds), | |
106 | .leds = cm_t35_leds, | |
107 | }; | |
108 | ||
109 | static struct platform_device cm_t35_led_device = { | |
110 | .name = "leds-gpio", | |
111 | .id = -1, | |
112 | .dev = { | |
113 | .platform_data = &cm_t35_led_pdata, | |
114 | }, | |
115 | }; | |
116 | ||
117 | static void __init cm_t35_init_led(void) | |
118 | { | |
119 | platform_device_register(&cm_t35_led_device); | |
120 | } | |
121 | #else | |
122 | static inline void cm_t35_init_led(void) {} | |
123 | #endif | |
124 | ||
125 | #if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE) | |
126 | #include <linux/mtd/mtd.h> | |
127 | #include <linux/mtd/nand.h> | |
128 | #include <linux/mtd/partitions.h> | |
129 | ||
130 | static struct mtd_partition cm_t35_nand_partitions[] = { | |
131 | { | |
132 | .name = "xloader", | |
133 | .offset = 0, /* Offset = 0x00000 */ | |
134 | .size = 4 * NAND_BLOCK_SIZE, | |
135 | .mask_flags = MTD_WRITEABLE | |
136 | }, | |
137 | { | |
138 | .name = "uboot", | |
139 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */ | |
140 | .size = 15 * NAND_BLOCK_SIZE, | |
141 | }, | |
142 | { | |
143 | .name = "uboot environment", | |
144 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x260000 */ | |
145 | .size = 2 * NAND_BLOCK_SIZE, | |
146 | }, | |
147 | { | |
148 | .name = "linux", | |
d12c2e28 | 149 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */ |
2886d128 MR |
150 | .size = 32 * NAND_BLOCK_SIZE, |
151 | }, | |
152 | { | |
153 | .name = "rootfs", | |
d12c2e28 | 154 | .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */ |
2886d128 MR |
155 | .size = MTDPART_SIZ_FULL, |
156 | }, | |
157 | }; | |
158 | ||
159 | static struct omap_nand_platform_data cm_t35_nand_data = { | |
160 | .parts = cm_t35_nand_partitions, | |
161 | .nr_parts = ARRAY_SIZE(cm_t35_nand_partitions), | |
2886d128 | 162 | .cs = 0, |
2886d128 MR |
163 | }; |
164 | ||
2886d128 MR |
165 | static void __init cm_t35_init_nand(void) |
166 | { | |
f450d867 | 167 | if (gpmc_nand_init(&cm_t35_nand_data) < 0) |
2886d128 MR |
168 | pr_err("CM-T35: Unable to register NAND device\n"); |
169 | } | |
170 | #else | |
171 | static inline void cm_t35_init_nand(void) {} | |
172 | #endif | |
173 | ||
7f049ad1 MR |
174 | #define CM_T35_LCD_EN_GPIO 157 |
175 | #define CM_T35_LCD_BL_GPIO 58 | |
176 | #define CM_T35_DVI_EN_GPIO 54 | |
177 | ||
7f049ad1 MR |
178 | static int lcd_enabled; |
179 | static int dvi_enabled; | |
180 | ||
181 | static int cm_t35_panel_enable_lcd(struct omap_dss_device *dssdev) | |
182 | { | |
183 | if (dvi_enabled) { | |
184 | printk(KERN_ERR "cannot enable LCD, DVI is enabled\n"); | |
185 | return -EINVAL; | |
186 | } | |
187 | ||
bc593f5d IG |
188 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); |
189 | gpio_set_value(CM_T35_LCD_BL_GPIO, 1); | |
7f049ad1 MR |
190 | |
191 | lcd_enabled = 1; | |
192 | ||
193 | return 0; | |
194 | } | |
195 | ||
196 | static void cm_t35_panel_disable_lcd(struct omap_dss_device *dssdev) | |
197 | { | |
198 | lcd_enabled = 0; | |
199 | ||
bc593f5d IG |
200 | gpio_set_value(CM_T35_LCD_BL_GPIO, 0); |
201 | gpio_set_value(CM_T35_LCD_EN_GPIO, 0); | |
7f049ad1 MR |
202 | } |
203 | ||
204 | static int cm_t35_panel_enable_dvi(struct omap_dss_device *dssdev) | |
205 | { | |
206 | if (lcd_enabled) { | |
207 | printk(KERN_ERR "cannot enable DVI, LCD is enabled\n"); | |
208 | return -EINVAL; | |
209 | } | |
210 | ||
bc593f5d | 211 | gpio_set_value(CM_T35_DVI_EN_GPIO, 0); |
7f049ad1 MR |
212 | dvi_enabled = 1; |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | static void cm_t35_panel_disable_dvi(struct omap_dss_device *dssdev) | |
218 | { | |
bc593f5d | 219 | gpio_set_value(CM_T35_DVI_EN_GPIO, 1); |
7f049ad1 MR |
220 | dvi_enabled = 0; |
221 | } | |
222 | ||
223 | static int cm_t35_panel_enable_tv(struct omap_dss_device *dssdev) | |
224 | { | |
225 | return 0; | |
226 | } | |
227 | ||
228 | static void cm_t35_panel_disable_tv(struct omap_dss_device *dssdev) | |
229 | { | |
230 | } | |
231 | ||
89747c91 BW |
232 | static struct panel_generic_dpi_data lcd_panel = { |
233 | .name = "toppoly_tdo35s", | |
234 | .platform_enable = cm_t35_panel_enable_lcd, | |
235 | .platform_disable = cm_t35_panel_disable_lcd, | |
236 | }; | |
237 | ||
7f049ad1 MR |
238 | static struct omap_dss_device cm_t35_lcd_device = { |
239 | .name = "lcd", | |
7f049ad1 | 240 | .type = OMAP_DISPLAY_TYPE_DPI, |
89747c91 BW |
241 | .driver_name = "generic_dpi_panel", |
242 | .data = &lcd_panel, | |
7f049ad1 | 243 | .phy.dpi.data_lines = 18, |
89747c91 BW |
244 | }; |
245 | ||
1d7a8654 | 246 | static struct panel_dvi_platform_data dvi_panel = { |
89747c91 BW |
247 | .platform_enable = cm_t35_panel_enable_dvi, |
248 | .platform_disable = cm_t35_panel_disable_dvi, | |
7f049ad1 MR |
249 | }; |
250 | ||
251 | static struct omap_dss_device cm_t35_dvi_device = { | |
252 | .name = "dvi", | |
7f049ad1 | 253 | .type = OMAP_DISPLAY_TYPE_DPI, |
1d7a8654 | 254 | .driver_name = "dvi", |
89747c91 | 255 | .data = &dvi_panel, |
7f049ad1 | 256 | .phy.dpi.data_lines = 24, |
7f049ad1 MR |
257 | }; |
258 | ||
259 | static struct omap_dss_device cm_t35_tv_device = { | |
260 | .name = "tv", | |
261 | .driver_name = "venc", | |
262 | .type = OMAP_DISPLAY_TYPE_VENC, | |
263 | .phy.venc.type = OMAP_DSS_VENC_TYPE_SVIDEO, | |
264 | .platform_enable = cm_t35_panel_enable_tv, | |
265 | .platform_disable = cm_t35_panel_disable_tv, | |
266 | }; | |
267 | ||
268 | static struct omap_dss_device *cm_t35_dss_devices[] = { | |
269 | &cm_t35_lcd_device, | |
270 | &cm_t35_dvi_device, | |
271 | &cm_t35_tv_device, | |
272 | }; | |
273 | ||
274 | static struct omap_dss_board_info cm_t35_dss_data = { | |
275 | .num_devices = ARRAY_SIZE(cm_t35_dss_devices), | |
276 | .devices = cm_t35_dss_devices, | |
277 | .default_device = &cm_t35_dvi_device, | |
278 | }; | |
279 | ||
7f049ad1 MR |
280 | static struct omap2_mcspi_device_config tdo24m_mcspi_config = { |
281 | .turbo_mode = 0, | |
282 | .single_channel = 1, /* 0: slave, 1: master */ | |
283 | }; | |
284 | ||
285 | static struct tdo24m_platform_data tdo24m_config = { | |
286 | .model = TDO35S, | |
287 | }; | |
288 | ||
289 | static struct spi_board_info cm_t35_lcd_spi_board_info[] __initdata = { | |
290 | { | |
291 | .modalias = "tdo24m", | |
292 | .bus_num = 4, | |
293 | .chip_select = 0, | |
294 | .max_speed_hz = 1000000, | |
295 | .controller_data = &tdo24m_mcspi_config, | |
296 | .platform_data = &tdo24m_config, | |
297 | }, | |
298 | }; | |
299 | ||
bc593f5d IG |
300 | static struct gpio cm_t35_dss_gpios[] __initdata = { |
301 | { CM_T35_LCD_EN_GPIO, GPIOF_OUT_INIT_LOW, "lcd enable" }, | |
302 | { CM_T35_LCD_BL_GPIO, GPIOF_OUT_INIT_LOW, "lcd bl enable" }, | |
303 | { CM_T35_DVI_EN_GPIO, GPIOF_OUT_INIT_HIGH, "dvi enable" }, | |
304 | }; | |
305 | ||
7f049ad1 MR |
306 | static void __init cm_t35_init_display(void) |
307 | { | |
308 | int err; | |
309 | ||
7f049ad1 MR |
310 | spi_register_board_info(cm_t35_lcd_spi_board_info, |
311 | ARRAY_SIZE(cm_t35_lcd_spi_board_info)); | |
312 | ||
bc593f5d IG |
313 | err = gpio_request_array(cm_t35_dss_gpios, |
314 | ARRAY_SIZE(cm_t35_dss_gpios)); | |
7f049ad1 | 315 | if (err) { |
bc593f5d IG |
316 | pr_err("CM-T35: failed to request DSS control GPIOs\n"); |
317 | return; | |
7f049ad1 MR |
318 | } |
319 | ||
bc593f5d IG |
320 | gpio_export(CM_T35_LCD_EN_GPIO, 0); |
321 | gpio_export(CM_T35_LCD_BL_GPIO, 0); | |
322 | gpio_export(CM_T35_DVI_EN_GPIO, 0); | |
7f049ad1 MR |
323 | |
324 | msleep(50); | |
bc593f5d | 325 | gpio_set_value(CM_T35_LCD_EN_GPIO, 1); |
7f049ad1 | 326 | |
d5e13227 | 327 | err = omap_display_init(&cm_t35_dss_data); |
7f049ad1 MR |
328 | if (err) { |
329 | pr_err("CM-T35: failed to register DSS device\n"); | |
bc593f5d | 330 | gpio_free_array(cm_t35_dss_gpios, ARRAY_SIZE(cm_t35_dss_gpios)); |
7f049ad1 | 331 | } |
7f049ad1 MR |
332 | } |
333 | ||
786b01a8 OD |
334 | static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = { |
335 | REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"), | |
2886d128 MR |
336 | }; |
337 | ||
786b01a8 OD |
338 | static struct regulator_consumer_supply cm_t35_vsim_supply[] = { |
339 | REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"), | |
2886d128 MR |
340 | }; |
341 | ||
786b01a8 OD |
342 | static struct regulator_consumer_supply cm_t35_vdvi_supply[] = { |
343 | REGULATOR_SUPPLY("vdvi", "omapdss"), | |
344 | }; | |
7f049ad1 | 345 | |
2886d128 MR |
346 | /* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */ |
347 | static struct regulator_init_data cm_t35_vmmc1 = { | |
348 | .constraints = { | |
349 | .min_uV = 1850000, | |
350 | .max_uV = 3150000, | |
351 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
352 | | REGULATOR_MODE_STANDBY, | |
353 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
354 | | REGULATOR_CHANGE_MODE | |
355 | | REGULATOR_CHANGE_STATUS, | |
356 | }, | |
786b01a8 OD |
357 | .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply), |
358 | .consumer_supplies = cm_t35_vmmc1_supply, | |
2886d128 MR |
359 | }; |
360 | ||
361 | /* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */ | |
362 | static struct regulator_init_data cm_t35_vsim = { | |
363 | .constraints = { | |
364 | .min_uV = 1800000, | |
365 | .max_uV = 3000000, | |
366 | .valid_modes_mask = REGULATOR_MODE_NORMAL | |
367 | | REGULATOR_MODE_STANDBY, | |
368 | .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | |
369 | | REGULATOR_CHANGE_MODE | |
370 | | REGULATOR_CHANGE_STATUS, | |
371 | }, | |
786b01a8 OD |
372 | .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply), |
373 | .consumer_supplies = cm_t35_vsim_supply, | |
2886d128 MR |
374 | }; |
375 | ||
bead4375 | 376 | static uint32_t cm_t35_keymap[] = { |
2886d128 MR |
377 | KEY(0, 0, KEY_A), KEY(0, 1, KEY_B), KEY(0, 2, KEY_LEFT), |
378 | KEY(1, 0, KEY_UP), KEY(1, 1, KEY_ENTER), KEY(1, 2, KEY_DOWN), | |
379 | KEY(2, 0, KEY_RIGHT), KEY(2, 1, KEY_C), KEY(2, 2, KEY_D), | |
380 | }; | |
381 | ||
382 | static struct matrix_keymap_data cm_t35_keymap_data = { | |
383 | .keymap = cm_t35_keymap, | |
384 | .keymap_size = ARRAY_SIZE(cm_t35_keymap), | |
385 | }; | |
386 | ||
387 | static struct twl4030_keypad_data cm_t35_kp_data = { | |
388 | .keymap_data = &cm_t35_keymap_data, | |
389 | .rows = 3, | |
390 | .cols = 3, | |
391 | .rep = 1, | |
392 | }; | |
393 | ||
68ff0423 | 394 | static struct omap2_hsmmc_info mmc[] = { |
2886d128 MR |
395 | { |
396 | .mmc = 1, | |
3a63833e | 397 | .caps = MMC_CAP_4_BIT_DATA, |
2886d128 MR |
398 | .gpio_cd = -EINVAL, |
399 | .gpio_wp = -EINVAL, | |
400 | ||
401 | }, | |
402 | { | |
403 | .mmc = 2, | |
3a63833e | 404 | .caps = MMC_CAP_4_BIT_DATA, |
2886d128 MR |
405 | .transceiver = 1, |
406 | .gpio_cd = -EINVAL, | |
407 | .gpio_wp = -EINVAL, | |
408 | .ocr_mask = 0x00100000, /* 3.3V */ | |
409 | }, | |
410 | {} /* Terminator */ | |
411 | }; | |
412 | ||
181b250c KM |
413 | static struct usbhs_omap_board_data usbhs_bdata __initdata = { |
414 | .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY, | |
415 | .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY, | |
416 | .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED, | |
2886d128 MR |
417 | |
418 | .phy_reset = true, | |
1a6b5923 BW |
419 | .reset_gpio_port[0] = OMAP_MAX_GPIO_LINES + 6, |
420 | .reset_gpio_port[1] = OMAP_MAX_GPIO_LINES + 7, | |
2886d128 MR |
421 | .reset_gpio_port[2] = -EINVAL |
422 | }; | |
423 | ||
424 | static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio, | |
425 | unsigned ngpio) | |
426 | { | |
427 | int wlan_rst = gpio + 2; | |
428 | ||
bc593f5d | 429 | if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) { |
2886d128 | 430 | gpio_export(wlan_rst, 0); |
2886d128 | 431 | udelay(10); |
be741de1 | 432 | gpio_set_value_cansleep(wlan_rst, 0); |
2886d128 | 433 | udelay(10); |
be741de1 | 434 | gpio_set_value_cansleep(wlan_rst, 1); |
2886d128 MR |
435 | } else { |
436 | pr_err("CM-T35: could not obtain gpio for WiFi reset\n"); | |
437 | } | |
438 | ||
439 | /* gpio + 0 is "mmc0_cd" (input/IRQ) */ | |
440 | mmc[0].gpio_cd = gpio + 0; | |
68ff0423 | 441 | omap2_hsmmc_init(mmc); |
2886d128 | 442 | |
2886d128 MR |
443 | return 0; |
444 | } | |
445 | ||
446 | static struct twl4030_gpio_platform_data cm_t35_gpio_data = { | |
447 | .gpio_base = OMAP_MAX_GPIO_LINES, | |
448 | .irq_base = TWL4030_GPIO_IRQ_BASE, | |
449 | .irq_end = TWL4030_GPIO_IRQ_END, | |
450 | .setup = cm_t35_twl_gpio_setup, | |
451 | }; | |
452 | ||
453 | static struct twl4030_platform_data cm_t35_twldata = { | |
2886d128 MR |
454 | /* platform_data for children goes here */ |
455 | .keypad = &cm_t35_kp_data, | |
2886d128 MR |
456 | .gpio = &cm_t35_gpio_data, |
457 | .vmmc1 = &cm_t35_vmmc1, | |
458 | .vsim = &cm_t35_vsim, | |
459 | }; | |
460 | ||
2886d128 MR |
461 | static void __init cm_t35_init_i2c(void) |
462 | { | |
b252b0ef PU |
463 | omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB, |
464 | TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2); | |
465 | ||
466 | cm_t35_twldata.vpll2->constraints.name = "VDVI"; | |
467 | cm_t35_twldata.vpll2->num_consumer_supplies = | |
468 | ARRAY_SIZE(cm_t35_vdvi_supply); | |
469 | cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply; | |
470 | ||
fbd8071c | 471 | omap3_pmic_init("tps65930", &cm_t35_twldata); |
2886d128 MR |
472 | } |
473 | ||
c7ecea24 | 474 | #ifdef CONFIG_OMAP_MUX |
ca5742bd | 475 | static struct omap_board_mux board_mux[] __initdata = { |
edc961a2 MR |
476 | /* nCS and IRQ for CM-T35 ethernet */ |
477 | OMAP3_MUX(GPMC_NCS5, OMAP_MUX_MODE0), | |
478 | OMAP3_MUX(UART3_CTS_RCTX, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
479 | ||
480 | /* nCS and IRQ for SB-T35 ethernet */ | |
481 | OMAP3_MUX(GPMC_NCS4, OMAP_MUX_MODE0), | |
482 | OMAP3_MUX(GPMC_WAIT3, OMAP_MUX_MODE4 | OMAP_PIN_INPUT_PULLUP), | |
483 | ||
484 | /* PENDOWN GPIO */ | |
485 | OMAP3_MUX(GPMC_NCS6, OMAP_MUX_MODE4 | OMAP_PIN_INPUT), | |
486 | ||
487 | /* mUSB */ | |
488 | OMAP3_MUX(HSUSB0_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
489 | OMAP3_MUX(HSUSB0_STP, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
490 | OMAP3_MUX(HSUSB0_DIR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
491 | OMAP3_MUX(HSUSB0_NXT, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
492 | OMAP3_MUX(HSUSB0_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
493 | OMAP3_MUX(HSUSB0_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
494 | OMAP3_MUX(HSUSB0_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
495 | OMAP3_MUX(HSUSB0_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
496 | OMAP3_MUX(HSUSB0_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
497 | OMAP3_MUX(HSUSB0_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
498 | OMAP3_MUX(HSUSB0_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
499 | OMAP3_MUX(HSUSB0_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
500 | ||
501 | /* MMC 2 */ | |
502 | OMAP3_MUX(SDMMC2_DAT4, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
503 | OMAP3_MUX(SDMMC2_DAT5, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
504 | OMAP3_MUX(SDMMC2_DAT6, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
505 | OMAP3_MUX(SDMMC2_DAT7, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
506 | ||
507 | /* McSPI 1 */ | |
508 | OMAP3_MUX(MCSPI1_CLK, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
509 | OMAP3_MUX(MCSPI1_SIMO, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
510 | OMAP3_MUX(MCSPI1_SOMI, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
511 | OMAP3_MUX(MCSPI1_CS0, OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLDOWN), | |
512 | ||
513 | /* McSPI 4 */ | |
514 | OMAP3_MUX(MCBSP1_CLKR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
515 | OMAP3_MUX(MCBSP1_DX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
516 | OMAP3_MUX(MCBSP1_DR, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
517 | OMAP3_MUX(MCBSP1_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT_PULLUP), | |
518 | ||
519 | /* McBSP 2 */ | |
520 | OMAP3_MUX(MCBSP2_FSX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
521 | OMAP3_MUX(MCBSP2_CLKX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
522 | OMAP3_MUX(MCBSP2_DR, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
523 | OMAP3_MUX(MCBSP2_DX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
524 | ||
525 | /* serial ports */ | |
526 | OMAP3_MUX(MCBSP3_CLKX, OMAP_MUX_MODE1 | OMAP_PIN_OUTPUT), | |
527 | OMAP3_MUX(MCBSP3_FSX, OMAP_MUX_MODE1 | OMAP_PIN_INPUT), | |
528 | OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
529 | OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT), | |
530 | ||
c3146974 | 531 | /* common DSS */ |
edc961a2 MR |
532 | OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), |
533 | OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
534 | OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
535 | OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
edc961a2 MR |
536 | OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), |
537 | OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
538 | OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
539 | OMAP3_MUX(DSS_DATA9, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
540 | OMAP3_MUX(DSS_DATA10, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
541 | OMAP3_MUX(DSS_DATA11, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
542 | OMAP3_MUX(DSS_DATA12, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
543 | OMAP3_MUX(DSS_DATA13, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
544 | OMAP3_MUX(DSS_DATA14, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
545 | OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
546 | OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
547 | OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT), | |
edc961a2 | 548 | |
7f049ad1 MR |
549 | /* display controls */ |
550 | OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
551 | OMAP3_MUX(GPMC_NCS7, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
552 | OMAP3_MUX(GPMC_NCS3, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT), | |
553 | ||
edc961a2 MR |
554 | /* TPS IRQ */ |
555 | OMAP3_MUX(SYS_NIRQ, OMAP_MUX_MODE0 | OMAP_WAKEUP_EN | \ | |
556 | OMAP_PIN_INPUT_PULLUP), | |
557 | ||
ca5742bd TL |
558 | { .reg_offset = OMAP_MUX_TERMINATOR }, |
559 | }; | |
c3146974 IG |
560 | |
561 | static void __init cm_t3x_common_dss_mux_init(int mux_mode) | |
562 | { | |
563 | omap_mux_init_signal("dss_data18", mux_mode); | |
564 | omap_mux_init_signal("dss_data19", mux_mode); | |
565 | omap_mux_init_signal("dss_data20", mux_mode); | |
566 | omap_mux_init_signal("dss_data21", mux_mode); | |
567 | omap_mux_init_signal("dss_data22", mux_mode); | |
568 | omap_mux_init_signal("dss_data23", mux_mode); | |
569 | } | |
570 | ||
571 | static void __init cm_t35_init_mux(void) | |
572 | { | |
573 | omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
574 | omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
575 | omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
576 | omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
577 | omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
578 | omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
579 | cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT); | |
580 | } | |
581 | ||
582 | static void __init cm_t3730_init_mux(void) | |
583 | { | |
584 | omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
585 | omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
586 | omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
587 | omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
588 | omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
589 | omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
590 | cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT); | |
591 | } | |
592 | #else | |
593 | static inline void cm_t35_init_mux(void) {} | |
594 | static inline void cm_t3730_init_mux(void) {} | |
c7ecea24 | 595 | #endif |
ca5742bd | 596 | |
e41cccfe TL |
597 | static struct omap_board_config_kernel cm_t35_config[] __initdata = { |
598 | }; | |
599 | ||
c3146974 | 600 | static void __init cm_t3x_common_init(void) |
2886d128 | 601 | { |
e41cccfe TL |
602 | omap_board_config = cm_t35_config; |
603 | omap_board_config_size = ARRAY_SIZE(cm_t35_config); | |
ca5742bd | 604 | omap3_mux_init(board_mux, OMAP_PACKAGE_CUS); |
2886d128 | 605 | omap_serial_init(); |
a4ca9dbe TL |
606 | omap_sdrc_init(mt46h32m32lf6_sdrc_params, |
607 | mt46h32m32lf6_sdrc_params); | |
2886d128 | 608 | cm_t35_init_i2c(); |
96974a24 | 609 | omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL); |
2886d128 MR |
610 | cm_t35_init_ethernet(); |
611 | cm_t35_init_led(); | |
7f049ad1 | 612 | cm_t35_init_display(); |
2886d128 | 613 | |
9e18630b | 614 | usb_musb_init(NULL); |
9e64bb1e | 615 | usbhs_init(&usbhs_bdata); |
2886d128 MR |
616 | } |
617 | ||
c3146974 IG |
618 | static void __init cm_t35_init(void) |
619 | { | |
620 | cm_t3x_common_init(); | |
621 | cm_t35_init_mux(); | |
622 | cm_t35_init_nand(); | |
623 | } | |
624 | ||
625 | static void __init cm_t3730_init(void) | |
626 | { | |
627 | cm_t3x_common_init(); | |
628 | cm_t3730_init_mux(); | |
629 | } | |
630 | ||
2886d128 | 631 | MACHINE_START(CM_T35, "Compulab CM-T35") |
5e52b435 | 632 | .atag_offset = 0x100, |
71ee7dad | 633 | .reserve = omap_reserve, |
3dc3bad6 | 634 | .map_io = omap3_map_io, |
8f5b5a41 | 635 | .init_early = omap35xx_init_early, |
741e3a89 | 636 | .init_irq = omap3_init_irq, |
2886d128 | 637 | .init_machine = cm_t35_init, |
e74984e4 | 638 | .timer = &omap3_timer, |
baa95883 | 639 | .restart = omap_prcm_restart, |
2886d128 | 640 | MACHINE_END |
c3146974 IG |
641 | |
642 | MACHINE_START(CM_T3730, "Compulab CM-T3730") | |
5e52b435 | 643 | .atag_offset = 0x100, |
c3146974 IG |
644 | .reserve = omap_reserve, |
645 | .map_io = omap3_map_io, | |
8f5b5a41 | 646 | .init_early = omap3630_init_early, |
c3146974 IG |
647 | .init_irq = omap3_init_irq, |
648 | .init_machine = cm_t3730_init, | |
649 | .timer = &omap3_timer, | |
baa95883 | 650 | .restart = omap_prcm_restart, |
c3146974 | 651 | MACHINE_END |