Commit | Line | Data |
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ec8f24b7 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
21278aea RH |
2 | menu "TI OMAP/AM/DM/DRA Family" |
3 | depends on ARCH_MULTI_V6 || ARCH_MULTI_V7 | |
4 | ||
68ac8f7d | 5 | config ARCH_OMAP2 |
f558b275 | 6 | bool "TI OMAP2" |
4b0ed696 | 7 | depends on ARCH_MULTI_V6 |
59d92875 | 8 | select ARCH_OMAP2PLUS |
68ac8f7d | 9 | select CPU_V6 |
ecc46cfd | 10 | select SOC_HAS_OMAP2_SDRC |
68ac8f7d TL |
11 | |
12 | config ARCH_OMAP3 | |
f558b275 | 13 | bool "TI OMAP3" |
4b0ed696 | 14 | depends on ARCH_MULTI_V7 |
59d92875 | 15 | select ARCH_OMAP2PLUS |
15e0d9e3 | 16 | select ARM_CPU_SUSPEND if PM |
0ee7261c | 17 | select OMAP_INTERCONNECT |
b1b3f49c | 18 | select PM_OPP if PM |
464ed18e | 19 | select PM if CPU_IDLE |
b1b3f49c | 20 | select SOC_HAS_OMAP2_SDRC |
2e4094bd | 21 | select ARM_ERRATA_430973 |
68ac8f7d TL |
22 | |
23 | config ARCH_OMAP4 | |
f558b275 | 24 | bool "TI OMAP4" |
4b0ed696 | 25 | depends on ARCH_MULTI_V7 |
59d92875 | 26 | select ARCH_OMAP2PLUS |
b1b3f49c RK |
27 | select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP |
28 | select ARM_CPU_SUSPEND if PM | |
29 | select ARM_ERRATA_720789 | |
30 | select ARM_GIC | |
4c3ffffd | 31 | select HAVE_ARM_SCU if SMP |
a894fcc2 | 32 | select HAVE_ARM_TWD if SMP |
b1b3f49c | 33 | select OMAP_INTERCONNECT |
3fa60975 | 34 | select OMAP_INTERCONNECT_BARRIER |
a641f3a6 RK |
35 | select PL310_ERRATA_588369 if CACHE_L2X0 |
36 | select PL310_ERRATA_727915 if CACHE_L2X0 | |
f5a6422d | 37 | select PM_OPP if PM |
464ed18e | 38 | select PM if CPU_IDLE |
7a981995 S |
39 | select ARM_ERRATA_754322 |
40 | select ARM_ERRATA_775420 | |
8d29bdba | 41 | select OMAP_INTERCONNECT |
68ac8f7d | 42 | |
35eb4298 S |
43 | config SOC_OMAP5 |
44 | bool "TI OMAP5" | |
4b0ed696 | 45 | depends on ARCH_MULTI_V7 |
59d92875 | 46 | select ARCH_OMAP2PLUS |
b1b3f49c | 47 | select ARM_CPU_SUSPEND if PM |
35eb4298 | 48 | select ARM_GIC |
896eba3b | 49 | select HAVE_ARM_SCU if SMP |
8a4da6e3 | 50 | select HAVE_ARM_ARCH_TIMER |
f82a3133 | 51 | select ARM_ERRATA_798181 if SMP |
d8f8004e | 52 | select OMAP_INTERCONNECT |
3fa60975 | 53 | select OMAP_INTERCONNECT_BARRIER |
d8f8004e | 54 | select PM_OPP if PM |
6a3b764b | 55 | select ZONE_DMA if ARM_LPAE |
35eb4298 | 56 | |
59d92875 | 57 | config SOC_AM33XX |
1085189f | 58 | bool "TI AM33XX" |
59d92875 AB |
59 | depends on ARCH_MULTI_V7 |
60 | select ARCH_OMAP2PLUS | |
61 | select ARM_CPU_SUSPEND if PM | |
59d92875 AB |
62 | |
63 | config SOC_AM43XX | |
64 | bool "TI AM43x" | |
65 | depends on ARCH_MULTI_V7 | |
59d92875 | 66 | select ARCH_OMAP2PLUS |
59d92875 | 67 | select ARM_GIC |
59d92875 | 68 | select MACH_OMAP_GENERIC |
d941f86f | 69 | select MIGHT_HAVE_CACHE_L2X0 |
f87d089d | 70 | select HAVE_ARM_SCU |
0b3e6fca | 71 | select GENERIC_CLOCKEVENTS_BROADCAST |
54011103 | 72 | select HAVE_ARM_TWD |
65db875d DG |
73 | select ARM_ERRATA_754322 |
74 | select ARM_ERRATA_775420 | |
72bb40b8 | 75 | select OMAP_INTERCONNECT |
41d9d44d | 76 | select ARM_CPU_SUSPEND if PM |
59d92875 | 77 | |
68b9f608 TK |
78 | config SOC_DRA7XX |
79 | bool "TI DRA7XX" | |
80 | depends on ARCH_MULTI_V7 | |
81 | select ARCH_OMAP2PLUS | |
82 | select ARM_CPU_SUSPEND if PM | |
83 | select ARM_GIC | |
d2e104c6 | 84 | select HAVE_ARM_SCU if SMP |
68b9f608 | 85 | select HAVE_ARM_ARCH_TIMER |
5c61e619 | 86 | select IRQ_CROSSBAR |
209431ef | 87 | select ARM_ERRATA_798181 if SMP |
d2e104c6 | 88 | select OMAP_INTERCONNECT |
3fa60975 | 89 | select OMAP_INTERCONNECT_BARRIER |
d2e104c6 | 90 | select PM_OPP if PM |
6a3b764b | 91 | select ZONE_DMA if ARM_LPAE |
c2818a19 | 92 | select PINCTRL_TI_IODELAY if OF && PINCTRL |
68b9f608 | 93 | |
59d92875 AB |
94 | config ARCH_OMAP2PLUS |
95 | bool | |
96 | select ARCH_HAS_BANDGAP | |
59d92875 AB |
97 | select ARCH_HAS_HOLES_MEMORYMODEL |
98 | select ARCH_OMAP | |
59d92875 | 99 | select CLKSRC_MMIO |
59d92875 | 100 | select GENERIC_IRQ_CHIP |
5c34a4e8 | 101 | select GPIOLIB |
f2acae69 | 102 | select MACH_OMAP_GENERIC |
18640193 | 103 | select MEMORY |
da4d8145 | 104 | select MFD_SYSCON |
59d92875 | 105 | select OMAP_DM_TIMER |
18640193 | 106 | select OMAP_GPMC |
59d92875 | 107 | select PINCTRL |
59d92875 | 108 | select SOC_BUS |
0eecc636 | 109 | select TI_SYSC |
8598066c | 110 | select OMAP_IRQCHIP |
429ac200 | 111 | select CLKSRC_TI_32K |
59d92875 AB |
112 | help |
113 | Systems based on OMAP2, OMAP3, OMAP4 or OMAP5 | |
114 | ||
3fa60975 RK |
115 | config OMAP_INTERCONNECT_BARRIER |
116 | bool | |
117 | select ARM_HEAVY_MB | |
118 | ||
59d92875 AB |
119 | |
120 | if ARCH_OMAP2PLUS | |
121 | ||
122 | menu "TI OMAP2/3/4 Specific Features" | |
123 | ||
124 | config ARCH_OMAP2PLUS_TYPICAL | |
125 | bool "Typical OMAP configuration" | |
126 | default y | |
127 | select AEABI | |
128 | select HIGHMEM | |
129 | select I2C | |
130 | select I2C_OMAP | |
131 | select MENELAUS if ARCH_OMAP2 | |
8dd21c93 | 132 | select NEON if CPU_V7 |
464ed18e | 133 | select PM |
59d92875 | 134 | select REGULATOR |
fc827928 | 135 | select REGULATOR_FIXED_VOLTAGE |
59d92875 AB |
136 | select TWL4030_CORE if ARCH_OMAP3 || ARCH_OMAP4 |
137 | select TWL4030_POWER if ARCH_OMAP3 || ARCH_OMAP4 | |
138 | select VFP | |
139 | help | |
140 | Compile a kernel suitable for booting most boards | |
141 | ||
142 | config SOC_HAS_OMAP2_SDRC | |
143 | bool "OMAP2 SDRAM Controller support" | |
144 | ||
145 | config SOC_HAS_REALTIME_COUNTER | |
146 | bool "Real time free running counter" | |
f18153f9 | 147 | depends on SOC_OMAP5 || SOC_DRA7XX |
59d92875 AB |
148 | default y |
149 | ||
1dbae815 | 150 | comment "OMAP Core Type" |
f558b275 | 151 | depends on ARCH_OMAP2 |
1dbae815 | 152 | |
59b479e0 | 153 | config SOC_OMAP2420 |
1dbae815 | 154 | bool "OMAP2420 support" |
f558b275 | 155 | depends on ARCH_OMAP2 |
ffb63e34 | 156 | default y |
77900a2f | 157 | select OMAP_DM_TIMER |
ecc46cfd | 158 | select SOC_HAS_OMAP2_SDRC |
1dbae815 | 159 | |
59b479e0 | 160 | config SOC_OMAP2430 |
72d0f1c3 | 161 | bool "OMAP2430 support" |
f558b275 | 162 | depends on ARCH_OMAP2 |
ffb63e34 | 163 | default y |
ecc46cfd | 164 | select SOC_HAS_OMAP2_SDRC |
72d0f1c3 | 165 | |
59b479e0 | 166 | config SOC_OMAP3430 |
cc26b3b0 | 167 | bool "OMAP3430 support" |
f558b275 | 168 | depends on ARCH_OMAP3 |
ffb63e34 | 169 | default y |
ecc46cfd | 170 | select SOC_HAS_OMAP2_SDRC |
cc26b3b0 | 171 | |
33959553 | 172 | config SOC_TI81XX |
a920360f | 173 | bool "TI81XX support" |
f558b275 | 174 | depends on ARCH_OMAP3 |
4bd7be22 HP |
175 | default y |
176 | ||
ddaa912a TL |
177 | config OMAP_PACKAGE_CBC |
178 | bool | |
179 | ||
180 | config OMAP_PACKAGE_CBB | |
181 | bool | |
182 | ||
183 | config OMAP_PACKAGE_CUS | |
184 | bool | |
185 | ||
662c8b55 TL |
186 | config OMAP_PACKAGE_CBP |
187 | bool | |
188 | ||
f2acae69 | 189 | comment "OMAP Legacy Platform Data Board Type" |
f558b275 | 190 | depends on ARCH_OMAP2PLUS |
1dbae815 TL |
191 | |
192 | config MACH_OMAP_GENERIC | |
f2acae69 | 193 | bool |
1dbae815 | 194 | |
1b52d5df KV |
195 | config MACH_OMAP2_TUSB6010 |
196 | bool | |
59b479e0 | 197 | depends on ARCH_OMAP2 && SOC_OMAP2420 |
1b52d5df KV |
198 | default y if MACH_NOKIA_N8X0 |
199 | ||
549f95ed TL |
200 | config MACH_OMAP3517EVM |
201 | bool "OMAP3517/ AM3517 EVM board" | |
202 | depends on ARCH_OMAP3 | |
203 | default y | |
204 | ||
da177247 GI |
205 | config MACH_OMAP3_PANDORA |
206 | bool "OMAP3 Pandora" | |
a8eb7ca0 | 207 | depends on ARCH_OMAP3 |
ffb63e34 | 208 | default y |
ca5742bd | 209 | select OMAP_PACKAGE_CBB |
6fdc29e2 | 210 | |
d2fbf345 TL |
211 | config MACH_NOKIA_N810 |
212 | bool | |
213 | ||
214 | config MACH_NOKIA_N810_WIMAX | |
215 | bool | |
216 | ||
63138812 KV |
217 | config MACH_NOKIA_N8X0 |
218 | bool "Nokia N800/N810" | |
59b479e0 | 219 | depends on SOC_OMAP2420 |
ffb63e34 | 220 | default y |
d2fbf345 TL |
221 | select MACH_NOKIA_N810 |
222 | select MACH_NOKIA_N810_WIMAX | |
63138812 | 223 | |
18862cbe PW |
224 | config OMAP3_SDRC_AC_TIMING |
225 | bool "Enable SDRC AC timing register changes" | |
a8eb7ca0 | 226 | depends on ARCH_OMAP3 |
18862cbe PW |
227 | help |
228 | If you know that none of your system initiators will attempt to | |
229 | access SDRAM during CORE DVFS, select Y here. This should boost | |
230 | SDRAM performance at lower CORE OPPs. There are relatively few | |
231 | users who will wish to say yes at this point - almost everyone will | |
232 | wish to say no. Selecting yes without understanding what is | |
233 | going on could result in system crashes; | |
234 | ||
4a54db61 TL |
235 | endmenu |
236 | ||
237 | endif | |
21278aea | 238 | |
c0053bd5 NM |
239 | config OMAP5_ERRATA_801819 |
240 | bool "Errata 801819: An eviction from L1 data cache might stall indefinitely" | |
241 | depends on SOC_OMAP5 || SOC_DRA7XX | |
242 | help | |
243 | A livelock can occur in the L2 cache arbitration that might prevent | |
244 | a snoop from completing. Under certain conditions this can cause the | |
245 | system to deadlock. | |
246 | ||
21278aea | 247 | endmenu |