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1a59d1b8 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
5e1c5ff4 TL |
2 | /* |
3 | * linux/arch/arm/plat-omap/ocpi.c | |
4 | * | |
5 | * Minimal OCP bus support for omap16xx | |
6 | * | |
7 | * Copyright (C) 2003 - 2005 Nokia Corporation | |
6f3c1af2 | 8 | * Copyright (C) 2012 Texas Instruments, Inc. |
5e1c5ff4 TL |
9 | * Written by Tony Lindgren <tony@atomide.com> |
10 | * | |
11 | * Modified for clock framework by Paul Mundt <paul.mundt@nokia.com>. | |
5e1c5ff4 TL |
12 | */ |
13 | ||
5e1c5ff4 | 14 | #include <linux/module.h> |
5e1c5ff4 TL |
15 | #include <linux/types.h> |
16 | #include <linux/errno.h> | |
17 | #include <linux/kernel.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/err.h> | |
f8ce2547 | 21 | #include <linux/clk.h> |
fced80c7 | 22 | #include <linux/io.h> |
5e1c5ff4 | 23 | |
a09e64fb | 24 | #include <mach/hardware.h> |
5e1c5ff4 | 25 | |
6f3c1af2 PW |
26 | #include "common.h" |
27 | ||
5e1c5ff4 TL |
28 | #define OCPI_BASE 0xfffec320 |
29 | #define OCPI_FAULT (OCPI_BASE + 0x00) | |
30 | #define OCPI_CMD_FAULT (OCPI_BASE + 0x04) | |
31 | #define OCPI_SINT0 (OCPI_BASE + 0x08) | |
32 | #define OCPI_TABORT (OCPI_BASE + 0x0c) | |
33 | #define OCPI_SINT1 (OCPI_BASE + 0x10) | |
34 | #define OCPI_PROT (OCPI_BASE + 0x14) | |
35 | #define OCPI_SEC (OCPI_BASE + 0x18) | |
36 | ||
37 | /* USB OHCI OCPI access error registers */ | |
38 | #define HOSTUEADDR 0xfffba0e0 | |
39 | #define HOSTUESTATUS 0xfffba0e4 | |
40 | ||
41 | static struct clk *ocpi_ck; | |
42 | ||
43 | /* | |
44 | * Enables device access to OMAP buses via the OCPI bridge | |
5e1c5ff4 TL |
45 | */ |
46 | int ocpi_enable(void) | |
47 | { | |
48 | unsigned int val; | |
49 | ||
50 | if (!cpu_is_omap16xx()) | |
51 | return -ENODEV; | |
52 | ||
5e1c5ff4 TL |
53 | /* Enable access for OHCI in OCPI */ |
54 | val = omap_readl(OCPI_PROT); | |
55 | val &= ~0xff; | |
6f3c1af2 | 56 | /* val &= (1 << 0); Allow access only to EMIFS */ |
5e1c5ff4 TL |
57 | omap_writel(val, OCPI_PROT); |
58 | ||
59 | val = omap_readl(OCPI_SEC); | |
60 | val &= ~0xff; | |
61 | omap_writel(val, OCPI_SEC); | |
62 | ||
63 | return 0; | |
64 | } | |
65 | EXPORT_SYMBOL(ocpi_enable); | |
66 | ||
67 | static int __init omap_ocpi_init(void) | |
68 | { | |
69 | if (!cpu_is_omap16xx()) | |
70 | return -ENODEV; | |
71 | ||
72 | ocpi_ck = clk_get(NULL, "l3_ocpi_ck"); | |
73 | if (IS_ERR(ocpi_ck)) | |
74 | return PTR_ERR(ocpi_ck); | |
75 | ||
30ff720b | 76 | clk_enable(ocpi_ck); |
5e1c5ff4 | 77 | ocpi_enable(); |
6f3c1af2 | 78 | pr_info("OMAP OCPI interconnect driver loaded\n"); |
5e1c5ff4 TL |
79 | |
80 | return 0; | |
81 | } | |
82 | ||
83 | static void __exit omap_ocpi_exit(void) | |
84 | { | |
85 | /* REVISIT: Disable OCPI */ | |
86 | ||
87 | if (!cpu_is_omap16xx()) | |
88 | return; | |
89 | ||
30ff720b | 90 | clk_disable(ocpi_ck); |
5e1c5ff4 TL |
91 | clk_put(ocpi_ck); |
92 | } | |
93 | ||
94 | MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>"); | |
95 | MODULE_DESCRIPTION("OMAP OCPI bus controller module"); | |
96 | MODULE_LICENSE("GPL"); | |
97 | module_init(omap_ocpi_init); | |
98 | module_exit(omap_ocpi_exit); |