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6568f7c4 MK |
1 | /* |
2 | * OMAP1/OMAP7xx - specific DMA driver | |
3 | * | |
4 | * Copyright (C) 2003 - 2008 Nokia Corporation | |
5 | * Author: Juha Yrjölä <juha.yrjola@nokia.com> | |
6 | * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com> | |
7 | * Graphics DMA and LCD DMA graphics tranformations | |
8 | * by Imre Deak <imre.deak@nokia.com> | |
9 | * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc. | |
10 | * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc. | |
11 | * | |
12 | * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/ | |
13 | * Converted DMA library into platform driver | |
14 | * - G, Manjunath Kondaiah <manjugk@ti.com> | |
15 | * | |
16 | * This program is free software; you can redistribute it and/or modify | |
17 | * it under the terms of the GNU General Public License version 2 as | |
18 | * published by the Free Software Foundation. | |
19 | */ | |
20 | ||
21 | #include <linux/err.h> | |
6568f7c4 MK |
22 | #include <linux/slab.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/device.h> | |
2e3ee9f4 | 26 | #include <linux/io.h> |
be1f9481 | 27 | #include <linux/dma-mapping.h> |
45c3eb7d | 28 | #include <linux/omap-dma.h> |
54b693d4 | 29 | #include <mach/tc.h> |
8afc5e08 | 30 | |
685e2d08 | 31 | #include "soc.h" |
6568f7c4 MK |
32 | |
33 | #define OMAP1_DMA_BASE (0xfffed800) | |
f31cc962 | 34 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 |
f31cc962 | 35 | |
f31cc962 | 36 | static u32 enable_1510_mode; |
f31cc962 | 37 | |
64a2dc3d RK |
38 | static const struct omap_dma_reg reg_map[] = { |
39 | [GCR] = { 0x0400, 0x00, OMAP_DMA_REG_16BIT }, | |
40 | [GSCR] = { 0x0404, 0x00, OMAP_DMA_REG_16BIT }, | |
41 | [GRST1] = { 0x0408, 0x00, OMAP_DMA_REG_16BIT }, | |
42 | [HW_ID] = { 0x0442, 0x00, OMAP_DMA_REG_16BIT }, | |
43 | [PCH2_ID] = { 0x0444, 0x00, OMAP_DMA_REG_16BIT }, | |
44 | [PCH0_ID] = { 0x0446, 0x00, OMAP_DMA_REG_16BIT }, | |
45 | [PCH1_ID] = { 0x0448, 0x00, OMAP_DMA_REG_16BIT }, | |
46 | [PCHG_ID] = { 0x044a, 0x00, OMAP_DMA_REG_16BIT }, | |
47 | [PCHD_ID] = { 0x044c, 0x00, OMAP_DMA_REG_16BIT }, | |
48 | [CAPS_0] = { 0x044e, 0x00, OMAP_DMA_REG_2X16BIT }, | |
49 | [CAPS_1] = { 0x0452, 0x00, OMAP_DMA_REG_2X16BIT }, | |
50 | [CAPS_2] = { 0x0456, 0x00, OMAP_DMA_REG_16BIT }, | |
51 | [CAPS_3] = { 0x0458, 0x00, OMAP_DMA_REG_16BIT }, | |
52 | [CAPS_4] = { 0x045a, 0x00, OMAP_DMA_REG_16BIT }, | |
53 | [PCH2_SR] = { 0x0460, 0x00, OMAP_DMA_REG_16BIT }, | |
54 | [PCH0_SR] = { 0x0480, 0x00, OMAP_DMA_REG_16BIT }, | |
55 | [PCH1_SR] = { 0x0482, 0x00, OMAP_DMA_REG_16BIT }, | |
56 | [PCHD_SR] = { 0x04c0, 0x00, OMAP_DMA_REG_16BIT }, | |
f31cc962 MK |
57 | |
58 | /* Common Registers */ | |
64a2dc3d RK |
59 | [CSDP] = { 0x0000, 0x40, OMAP_DMA_REG_16BIT }, |
60 | [CCR] = { 0x0002, 0x40, OMAP_DMA_REG_16BIT }, | |
61 | [CICR] = { 0x0004, 0x40, OMAP_DMA_REG_16BIT }, | |
62 | [CSR] = { 0x0006, 0x40, OMAP_DMA_REG_16BIT }, | |
63 | [CEN] = { 0x0010, 0x40, OMAP_DMA_REG_16BIT }, | |
64 | [CFN] = { 0x0012, 0x40, OMAP_DMA_REG_16BIT }, | |
65 | [CSFI] = { 0x0014, 0x40, OMAP_DMA_REG_16BIT }, | |
66 | [CSEI] = { 0x0016, 0x40, OMAP_DMA_REG_16BIT }, | |
67 | [CPC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, /* 15xx only */ | |
68 | [CSAC] = { 0x0018, 0x40, OMAP_DMA_REG_16BIT }, | |
69 | [CDAC] = { 0x001a, 0x40, OMAP_DMA_REG_16BIT }, | |
70 | [CDEI] = { 0x001c, 0x40, OMAP_DMA_REG_16BIT }, | |
71 | [CDFI] = { 0x001e, 0x40, OMAP_DMA_REG_16BIT }, | |
72 | [CLNK_CTRL] = { 0x0028, 0x40, OMAP_DMA_REG_16BIT }, | |
f31cc962 MK |
73 | |
74 | /* Channel specific register offsets */ | |
64a2dc3d RK |
75 | [CSSA] = { 0x0008, 0x40, OMAP_DMA_REG_2X16BIT }, |
76 | [CDSA] = { 0x000c, 0x40, OMAP_DMA_REG_2X16BIT }, | |
77 | [COLOR] = { 0x0020, 0x40, OMAP_DMA_REG_2X16BIT }, | |
78 | [CCR2] = { 0x0024, 0x40, OMAP_DMA_REG_16BIT }, | |
79 | [LCH_CTRL] = { 0x002a, 0x40, OMAP_DMA_REG_16BIT }, | |
f31cc962 | 80 | }; |
6568f7c4 MK |
81 | |
82 | static struct resource res[] __initdata = { | |
83 | [0] = { | |
84 | .start = OMAP1_DMA_BASE, | |
85 | .end = OMAP1_DMA_BASE + SZ_2K - 1, | |
86 | .flags = IORESOURCE_MEM, | |
87 | }, | |
88 | [1] = { | |
89 | .name = "0", | |
90 | .start = INT_DMA_CH0_6, | |
91 | .flags = IORESOURCE_IRQ, | |
92 | }, | |
93 | [2] = { | |
94 | .name = "1", | |
95 | .start = INT_DMA_CH1_7, | |
96 | .flags = IORESOURCE_IRQ, | |
97 | }, | |
98 | [3] = { | |
99 | .name = "2", | |
100 | .start = INT_DMA_CH2_8, | |
101 | .flags = IORESOURCE_IRQ, | |
102 | }, | |
103 | [4] = { | |
104 | .name = "3", | |
105 | .start = INT_DMA_CH3, | |
106 | .flags = IORESOURCE_IRQ, | |
107 | }, | |
108 | [5] = { | |
109 | .name = "4", | |
110 | .start = INT_DMA_CH4, | |
111 | .flags = IORESOURCE_IRQ, | |
112 | }, | |
113 | [6] = { | |
114 | .name = "5", | |
115 | .start = INT_DMA_CH5, | |
116 | .flags = IORESOURCE_IRQ, | |
117 | }, | |
f31cc962 | 118 | /* Handled in lcd_dma.c */ |
6568f7c4 MK |
119 | [7] = { |
120 | .name = "6", | |
121 | .start = INT_1610_DMA_CH6, | |
122 | .flags = IORESOURCE_IRQ, | |
123 | }, | |
124 | /* irq's for omap16xx and omap7xx */ | |
125 | [8] = { | |
126 | .name = "7", | |
127 | .start = INT_1610_DMA_CH7, | |
128 | .flags = IORESOURCE_IRQ, | |
129 | }, | |
130 | [9] = { | |
131 | .name = "8", | |
132 | .start = INT_1610_DMA_CH8, | |
133 | .flags = IORESOURCE_IRQ, | |
134 | }, | |
135 | [10] = { | |
136 | .name = "9", | |
137 | .start = INT_1610_DMA_CH9, | |
138 | .flags = IORESOURCE_IRQ, | |
139 | }, | |
140 | [11] = { | |
141 | .name = "10", | |
142 | .start = INT_1610_DMA_CH10, | |
143 | .flags = IORESOURCE_IRQ, | |
144 | }, | |
145 | [12] = { | |
146 | .name = "11", | |
147 | .start = INT_1610_DMA_CH11, | |
148 | .flags = IORESOURCE_IRQ, | |
149 | }, | |
150 | [13] = { | |
151 | .name = "12", | |
152 | .start = INT_1610_DMA_CH12, | |
153 | .flags = IORESOURCE_IRQ, | |
154 | }, | |
155 | [14] = { | |
156 | .name = "13", | |
157 | .start = INT_1610_DMA_CH13, | |
158 | .flags = IORESOURCE_IRQ, | |
159 | }, | |
160 | [15] = { | |
161 | .name = "14", | |
162 | .start = INT_1610_DMA_CH14, | |
163 | .flags = IORESOURCE_IRQ, | |
164 | }, | |
165 | [16] = { | |
166 | .name = "15", | |
167 | .start = INT_1610_DMA_CH15, | |
168 | .flags = IORESOURCE_IRQ, | |
169 | }, | |
170 | [17] = { | |
171 | .name = "16", | |
172 | .start = INT_DMA_LCD, | |
173 | .flags = IORESOURCE_IRQ, | |
174 | }, | |
175 | }; | |
176 | ||
f31cc962 MK |
177 | static void __iomem *dma_base; |
178 | static inline void dma_write(u32 val, int reg, int lch) | |
179 | { | |
64a2dc3d RK |
180 | void __iomem *addr = dma_base; |
181 | ||
182 | addr += reg_map[reg].offset; | |
183 | addr += reg_map[reg].stride * lch; | |
184 | ||
185 | __raw_writew(val, addr); | |
186 | if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT) | |
187 | __raw_writew(val >> 16, addr + 2); | |
f31cc962 MK |
188 | } |
189 | ||
190 | static inline u32 dma_read(int reg, int lch) | |
191 | { | |
64a2dc3d RK |
192 | void __iomem *addr = dma_base; |
193 | uint32_t val; | |
194 | ||
195 | addr += reg_map[reg].offset; | |
196 | addr += reg_map[reg].stride * lch; | |
197 | ||
198 | val = __raw_readw(addr); | |
199 | if (reg_map[reg].type == OMAP_DMA_REG_2X16BIT) | |
200 | val |= __raw_readw(addr + 2) << 16; | |
201 | ||
f31cc962 MK |
202 | return val; |
203 | } | |
204 | ||
205 | static void omap1_clear_lch_regs(int lch) | |
206 | { | |
ad0c381a | 207 | int i; |
f31cc962 | 208 | |
ad0c381a | 209 | for (i = CPC; i <= COLOR; i += 1) |
f31cc962 MK |
210 | dma_write(0, i, lch); |
211 | } | |
212 | ||
213 | static void omap1_clear_dma(int lch) | |
214 | { | |
215 | u32 l; | |
216 | ||
217 | l = dma_read(CCR, lch); | |
218 | l &= ~OMAP_DMA_CCR_EN; | |
219 | dma_write(l, CCR, lch); | |
220 | ||
221 | /* Clear pending interrupts */ | |
222 | l = dma_read(CSR, lch); | |
223 | } | |
224 | ||
225 | static void omap1_show_dma_caps(void) | |
226 | { | |
227 | if (enable_1510_mode) { | |
228 | printk(KERN_INFO "DMA support for OMAP15xx initialized\n"); | |
229 | } else { | |
230 | u16 w; | |
231 | printk(KERN_INFO "OMAP DMA hardware version %d\n", | |
232 | dma_read(HW_ID, 0)); | |
233 | printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n", | |
234 | dma_read(CAPS_0, 0), dma_read(CAPS_1, 0), | |
235 | dma_read(CAPS_2, 0), dma_read(CAPS_3, 0), | |
236 | dma_read(CAPS_4, 0)); | |
237 | ||
238 | /* Disable OMAP 3.0/3.1 compatibility mode. */ | |
239 | w = dma_read(GSCR, 0); | |
240 | w |= 1 << 3; | |
241 | dma_write(w, GSCR, 0); | |
242 | } | |
243 | return; | |
244 | } | |
245 | ||
0ef64986 | 246 | static unsigned configure_dma_errata(void) |
f31cc962 | 247 | { |
0ef64986 | 248 | unsigned errata = 0; |
f31cc962 MK |
249 | |
250 | /* | |
251 | * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is | |
252 | * read before the DMA controller finished disabling the channel. | |
253 | */ | |
254 | if (!cpu_is_omap15xx()) | |
255 | SET_DMA_ERRATA(DMA_ERRATA_3_3); | |
256 | ||
257 | return errata; | |
258 | } | |
259 | ||
be1f9481 TL |
260 | static const struct platform_device_info omap_dma_dev_info = { |
261 | .name = "omap-dma-engine", | |
262 | .id = -1, | |
263 | .dma_mask = DMA_BIT_MASK(32), | |
596c471b RK |
264 | .res = res, |
265 | .num_res = 1, | |
be1f9481 TL |
266 | }; |
267 | ||
34a378fc | 268 | static struct omap_system_dma_plat_info dma_plat_info __initdata = { |
596c471b RK |
269 | .reg_map = reg_map, |
270 | .channel_stride = 0x40, | |
34a378fc RK |
271 | .show_dma_caps = omap1_show_dma_caps, |
272 | .clear_lch_regs = omap1_clear_lch_regs, | |
273 | .clear_dma = omap1_clear_dma, | |
274 | .dma_write = dma_write, | |
275 | .dma_read = dma_read, | |
276 | }; | |
277 | ||
6568f7c4 MK |
278 | static int __init omap1_system_dma_init(void) |
279 | { | |
34a378fc | 280 | struct omap_system_dma_plat_info p; |
f31cc962 | 281 | struct omap_dma_dev_attr *d; |
be1f9481 | 282 | struct platform_device *pdev, *dma_pdev; |
6568f7c4 MK |
283 | int ret; |
284 | ||
285 | pdev = platform_device_alloc("omap_dma_system", 0); | |
286 | if (!pdev) { | |
287 | pr_err("%s: Unable to device alloc for dma\n", | |
288 | __func__); | |
289 | return -ENOMEM; | |
290 | } | |
291 | ||
f31cc962 MK |
292 | dma_base = ioremap(res[0].start, resource_size(&res[0])); |
293 | if (!dma_base) { | |
294 | pr_err("%s: Unable to ioremap\n", __func__); | |
77f7059a JL |
295 | ret = -ENODEV; |
296 | goto exit_device_put; | |
f31cc962 MK |
297 | } |
298 | ||
6568f7c4 MK |
299 | ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res)); |
300 | if (ret) { | |
301 | dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", | |
302 | __func__, pdev->name, pdev->id); | |
348c3422 | 303 | goto exit_iounmap; |
6568f7c4 MK |
304 | } |
305 | ||
f31cc962 MK |
306 | d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL); |
307 | if (!d) { | |
308 | dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n", | |
309 | __func__, pdev->name); | |
310 | ret = -ENOMEM; | |
34a378fc | 311 | goto exit_iounmap; |
f31cc962 MK |
312 | } |
313 | ||
314 | d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT; | |
315 | ||
316 | /* Valid attributes for omap1 plus processors */ | |
317 | if (cpu_is_omap15xx()) | |
318 | d->dev_caps = ENABLE_1510_MODE; | |
319 | enable_1510_mode = d->dev_caps & ENABLE_1510_MODE; | |
320 | ||
82809601 TL |
321 | if (cpu_is_omap16xx()) |
322 | d->dev_caps = ENABLE_16XX_MODE; | |
323 | ||
f31cc962 MK |
324 | d->dev_caps |= SRC_PORT; |
325 | d->dev_caps |= DST_PORT; | |
326 | d->dev_caps |= SRC_INDEX; | |
327 | d->dev_caps |= DST_INDEX; | |
328 | d->dev_caps |= IS_BURST_ONLY4; | |
329 | d->dev_caps |= CLEAR_CSR_ON_READ; | |
330 | d->dev_caps |= IS_WORD_16; | |
331 | ||
f31cc962 MK |
332 | if (cpu_is_omap15xx()) |
333 | d->chan_count = 9; | |
334 | else if (cpu_is_omap16xx() || cpu_is_omap7xx()) { | |
335 | if (!(d->dev_caps & ENABLE_1510_MODE)) | |
336 | d->chan_count = 16; | |
337 | else | |
338 | d->chan_count = 9; | |
339 | } | |
340 | ||
34a378fc RK |
341 | p = dma_plat_info; |
342 | p.dma_attr = d; | |
343 | p.errata = configure_dma_errata(); | |
f31cc962 | 344 | |
34a378fc | 345 | ret = platform_device_add_data(pdev, &p, sizeof(p)); |
6568f7c4 MK |
346 | if (ret) { |
347 | dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", | |
348 | __func__, pdev->name, pdev->id); | |
9834f813 | 349 | goto exit_release_d; |
6568f7c4 MK |
350 | } |
351 | ||
352 | ret = platform_device_add(pdev); | |
353 | if (ret) { | |
354 | dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n", | |
355 | __func__, pdev->name, pdev->id); | |
9834f813 | 356 | goto exit_release_d; |
6568f7c4 MK |
357 | } |
358 | ||
be1f9481 TL |
359 | dma_pdev = platform_device_register_full(&omap_dma_dev_info); |
360 | if (IS_ERR(dma_pdev)) { | |
361 | ret = PTR_ERR(dma_pdev); | |
362 | goto exit_release_pdev; | |
363 | } | |
364 | ||
6568f7c4 MK |
365 | return ret; |
366 | ||
be1f9481 TL |
367 | exit_release_pdev: |
368 | platform_device_del(pdev); | |
f31cc962 MK |
369 | exit_release_d: |
370 | kfree(d); | |
348c3422 WY |
371 | exit_iounmap: |
372 | iounmap(dma_base); | |
77f7059a JL |
373 | exit_device_put: |
374 | platform_device_put(pdev); | |
6568f7c4 MK |
375 | |
376 | return ret; | |
377 | } | |
378 | arch_initcall(omap1_system_dma_init); |