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3179a019 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.h | |
3 | * | |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
15 | ||
3179a019 TL |
16 | static void omap1_ckctl_recalc(struct clk * clk); |
17 | static void omap1_watchdog_recalc(struct clk * clk); | |
df2c2e70 ID |
18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
19 | static void omap1_sossi_recalc(struct clk *clk); | |
3179a019 | 20 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk); |
3179a019 | 21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); |
3179a019 TL |
22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); |
23 | static void omap1_uart_recalc(struct clk * clk); | |
3179a019 TL |
24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); |
25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | |
26 | static void omap1_init_ext_clk(struct clk * clk); | |
27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | |
28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | |
3179a019 | 29 | |
d5e6072b RK |
30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | |
32 | ||
3179a019 TL |
33 | struct mpu_rate { |
34 | unsigned long rate; | |
35 | unsigned long xtal; | |
36 | unsigned long pll_rate; | |
37 | __u16 ckctl_val; | |
38 | __u16 dpllctl_val; | |
39 | }; | |
40 | ||
41 | struct uart_clk { | |
42 | struct clk clk; | |
43 | unsigned long sysc_addr; | |
44 | }; | |
45 | ||
46 | /* Provide a method for preventing idling some ARM IDLECT clocks */ | |
47 | struct arm_idlect1_clk { | |
48 | struct clk clk; | |
49 | unsigned long no_idle_count; | |
50 | __u8 idlect_shift; | |
51 | }; | |
52 | ||
53 | /* ARM_CKCTL bit shifts */ | |
54 | #define CKCTL_PERDIV_OFFSET 0 | |
55 | #define CKCTL_LCDDIV_OFFSET 2 | |
56 | #define CKCTL_ARMDIV_OFFSET 4 | |
57 | #define CKCTL_DSPDIV_OFFSET 6 | |
58 | #define CKCTL_TCDIV_OFFSET 8 | |
59 | #define CKCTL_DSPMMUDIV_OFFSET 10 | |
60 | /*#define ARM_TIMXO 12*/ | |
61 | #define EN_DSPCK 13 | |
62 | /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ | |
63 | /* DSP_CKCTL bit shifts */ | |
64 | #define CKCTL_DSPPERDIV_OFFSET 0 | |
65 | ||
66 | /* ARM_IDLECT2 bit shifts */ | |
67 | #define EN_WDTCK 0 | |
68 | #define EN_XORPCK 1 | |
69 | #define EN_PERCK 2 | |
70 | #define EN_LCDCK 3 | |
71 | #define EN_LBCK 4 /* Not on 1610/1710 */ | |
72 | /*#define EN_HSABCK 5*/ | |
73 | #define EN_APICK 6 | |
74 | #define EN_TIMCK 7 | |
75 | #define DMACK_REQ 8 | |
76 | #define EN_GPIOCK 9 /* Not on 1610/1710 */ | |
77 | /*#define EN_LBFREECK 10*/ | |
78 | #define EN_CKOUT_ARM 11 | |
79 | ||
80 | /* ARM_IDLECT3 bit shifts */ | |
81 | #define EN_OCPI_CK 0 | |
82 | #define EN_TC1_CK 2 | |
83 | #define EN_TC2_CK 4 | |
84 | ||
85 | /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ | |
86 | #define EN_DSPTIMCK 5 | |
87 | ||
88 | /* Various register defines for clock controls scattered around OMAP chip */ | |
90afd5cb | 89 | #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
3179a019 TL |
90 | #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
91 | #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ | |
92 | #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ | |
93 | #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ | |
94 | #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 | |
95 | #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 | |
96 | #define SOFT_REQ_REG 0xfffe0834 | |
97 | #define SOFT_REQ_REG2 0xfffe0880 | |
98 | ||
99 | /*------------------------------------------------------------------------- | |
100 | * Omap1 MPU rate table | |
101 | *-------------------------------------------------------------------------*/ | |
102 | static struct mpu_rate rate_table[] = { | |
103 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | |
104 | * NOTE: Comment order here is different from bits in CKCTL value: | |
105 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | |
106 | */ | |
107 | #if defined(CONFIG_OMAP_ARM_216MHZ) | |
108 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | |
109 | #endif | |
110 | #if defined(CONFIG_OMAP_ARM_195MHZ) | |
111 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | |
112 | #endif | |
113 | #if defined(CONFIG_OMAP_ARM_192MHZ) | |
114 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | |
115 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | |
116 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | |
117 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | |
118 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | |
119 | #endif | |
120 | #if defined(CONFIG_OMAP_ARM_182MHZ) | |
121 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | |
122 | #endif | |
123 | #if defined(CONFIG_OMAP_ARM_168MHZ) | |
124 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | |
125 | #endif | |
126 | #if defined(CONFIG_OMAP_ARM_150MHZ) | |
127 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | |
128 | #endif | |
129 | #if defined(CONFIG_OMAP_ARM_120MHZ) | |
130 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | |
131 | #endif | |
132 | #if defined(CONFIG_OMAP_ARM_96MHZ) | |
133 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | |
134 | #endif | |
135 | #if defined(CONFIG_OMAP_ARM_60MHZ) | |
136 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | |
137 | #endif | |
138 | #if defined(CONFIG_OMAP_ARM_30MHZ) | |
139 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | |
140 | #endif | |
141 | { 0, 0, 0, 0, 0 }, | |
142 | }; | |
143 | ||
144 | /*------------------------------------------------------------------------- | |
145 | * Omap1 clocks | |
146 | *-------------------------------------------------------------------------*/ | |
147 | ||
148 | static struct clk ck_ref = { | |
149 | .name = "ck_ref", | |
897dcded | 150 | .ops = &clkops_null, |
3179a019 | 151 | .rate = 12000000, |
3179a019 TL |
152 | }; |
153 | ||
154 | static struct clk ck_dpll1 = { | |
155 | .name = "ck_dpll1", | |
897dcded | 156 | .ops = &clkops_null, |
3179a019 | 157 | .parent = &ck_ref, |
d7e8f1f9 | 158 | .flags = RATE_PROPAGATES, |
3179a019 TL |
159 | }; |
160 | ||
161 | static struct arm_idlect1_clk ck_dpll1out = { | |
162 | .clk = { | |
df2c2e70 | 163 | .name = "ck_dpll1out", |
548d8495 | 164 | .ops = &clkops_generic, |
3179a019 | 165 | .parent = &ck_dpll1, |
d7e8f1f9 | 166 | .flags = CLOCK_IDLE_CONTROL | |
df2c2e70 | 167 | ENABLE_REG_32BIT | RATE_PROPAGATES, |
3179a019 TL |
168 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
169 | .enable_bit = EN_CKOUT_ARM, | |
170 | .recalc = &followparent_recalc, | |
3179a019 TL |
171 | }, |
172 | .idlect_shift = 12, | |
173 | }; | |
174 | ||
df2c2e70 ID |
175 | static struct clk sossi_ck = { |
176 | .name = "ck_sossi", | |
548d8495 | 177 | .ops = &clkops_generic, |
df2c2e70 | 178 | .parent = &ck_dpll1out.clk, |
d7e8f1f9 | 179 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, |
df2c2e70 ID |
180 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_1, |
181 | .enable_bit = 16, | |
182 | .recalc = &omap1_sossi_recalc, | |
183 | .set_rate = &omap1_set_sossi_rate, | |
df2c2e70 ID |
184 | }; |
185 | ||
3179a019 TL |
186 | static struct clk arm_ck = { |
187 | .name = "arm_ck", | |
897dcded | 188 | .ops = &clkops_null, |
3179a019 | 189 | .parent = &ck_dpll1, |
d7e8f1f9 | 190 | .flags = RATE_PROPAGATES, |
3179a019 TL |
191 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
192 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
193 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
194 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
195 | }; |
196 | ||
197 | static struct arm_idlect1_clk armper_ck = { | |
198 | .clk = { | |
199 | .name = "armper_ck", | |
548d8495 | 200 | .ops = &clkops_generic, |
3179a019 | 201 | .parent = &ck_dpll1, |
d7e8f1f9 | 202 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
203 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
204 | .enable_bit = EN_PERCK, | |
205 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
206 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
207 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
208 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
209 | }, |
210 | .idlect_shift = 2, | |
211 | }; | |
212 | ||
213 | static struct clk arm_gpio_ck = { | |
214 | .name = "arm_gpio_ck", | |
548d8495 | 215 | .ops = &clkops_generic, |
3179a019 | 216 | .parent = &ck_dpll1, |
3179a019 TL |
217 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
218 | .enable_bit = EN_GPIOCK, | |
219 | .recalc = &followparent_recalc, | |
3179a019 TL |
220 | }; |
221 | ||
222 | static struct arm_idlect1_clk armxor_ck = { | |
223 | .clk = { | |
224 | .name = "armxor_ck", | |
548d8495 | 225 | .ops = &clkops_generic, |
3179a019 | 226 | .parent = &ck_ref, |
d7e8f1f9 | 227 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
228 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
229 | .enable_bit = EN_XORPCK, | |
230 | .recalc = &followparent_recalc, | |
3179a019 TL |
231 | }, |
232 | .idlect_shift = 1, | |
233 | }; | |
234 | ||
235 | static struct arm_idlect1_clk armtim_ck = { | |
236 | .clk = { | |
237 | .name = "armtim_ck", | |
548d8495 | 238 | .ops = &clkops_generic, |
3179a019 | 239 | .parent = &ck_ref, |
d7e8f1f9 | 240 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
241 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
242 | .enable_bit = EN_TIMCK, | |
243 | .recalc = &followparent_recalc, | |
3179a019 TL |
244 | }, |
245 | .idlect_shift = 9, | |
246 | }; | |
247 | ||
248 | static struct arm_idlect1_clk armwdt_ck = { | |
249 | .clk = { | |
250 | .name = "armwdt_ck", | |
548d8495 | 251 | .ops = &clkops_generic, |
3179a019 | 252 | .parent = &ck_ref, |
d7e8f1f9 | 253 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
254 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
255 | .enable_bit = EN_WDTCK, | |
256 | .recalc = &omap1_watchdog_recalc, | |
3179a019 TL |
257 | }, |
258 | .idlect_shift = 0, | |
259 | }; | |
260 | ||
261 | static struct clk arminth_ck16xx = { | |
262 | .name = "arminth_ck", | |
897dcded | 263 | .ops = &clkops_null, |
3179a019 | 264 | .parent = &arm_ck, |
3179a019 TL |
265 | .recalc = &followparent_recalc, |
266 | /* Note: On 16xx the frequency can be divided by 2 by programming | |
267 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | |
268 | * | |
269 | * 1510 version is in TC clocks. | |
270 | */ | |
3179a019 TL |
271 | }; |
272 | ||
273 | static struct clk dsp_ck = { | |
274 | .name = "dsp_ck", | |
548d8495 | 275 | .ops = &clkops_generic, |
3179a019 | 276 | .parent = &ck_dpll1, |
3179a019 TL |
277 | .enable_reg = (void __iomem *)ARM_CKCTL, |
278 | .enable_bit = EN_DSPCK, | |
279 | .rate_offset = CKCTL_DSPDIV_OFFSET, | |
280 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
281 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
282 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
283 | }; |
284 | ||
285 | static struct clk dspmmu_ck = { | |
286 | .name = "dspmmu_ck", | |
897dcded | 287 | .ops = &clkops_null, |
3179a019 | 288 | .parent = &ck_dpll1, |
3179a019 TL |
289 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
290 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
291 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
292 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
293 | }; |
294 | ||
295 | static struct clk dspper_ck = { | |
296 | .name = "dspper_ck", | |
548d8495 | 297 | .ops = &clkops_dspck, |
3179a019 | 298 | .parent = &ck_dpll1, |
d7e8f1f9 | 299 | .flags = VIRTUAL_IO_ADDRESS, |
397fcaf7 | 300 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
301 | .enable_bit = EN_PERCK, |
302 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
303 | .recalc = &omap1_ckctl_recalc_dsp_domain, | |
d5e6072b | 304 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
3179a019 | 305 | .set_rate = &omap1_clk_set_rate_dsp_domain, |
3179a019 TL |
306 | }; |
307 | ||
308 | static struct clk dspxor_ck = { | |
309 | .name = "dspxor_ck", | |
548d8495 | 310 | .ops = &clkops_dspck, |
3179a019 | 311 | .parent = &ck_ref, |
d7e8f1f9 | 312 | .flags = VIRTUAL_IO_ADDRESS, |
397fcaf7 | 313 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
314 | .enable_bit = EN_XORPCK, |
315 | .recalc = &followparent_recalc, | |
3179a019 TL |
316 | }; |
317 | ||
318 | static struct clk dsptim_ck = { | |
319 | .name = "dsptim_ck", | |
548d8495 | 320 | .ops = &clkops_dspck, |
3179a019 | 321 | .parent = &ck_ref, |
d7e8f1f9 | 322 | .flags = VIRTUAL_IO_ADDRESS, |
397fcaf7 | 323 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
324 | .enable_bit = EN_DSPTIMCK, |
325 | .recalc = &followparent_recalc, | |
3179a019 TL |
326 | }; |
327 | ||
328 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | |
329 | static struct arm_idlect1_clk tc_ck = { | |
330 | .clk = { | |
331 | .name = "tc_ck", | |
897dcded | 332 | .ops = &clkops_null, |
3179a019 | 333 | .parent = &ck_dpll1, |
d7e8f1f9 | 334 | .flags = RATE_PROPAGATES | CLOCK_IDLE_CONTROL, |
3179a019 TL |
335 | .rate_offset = CKCTL_TCDIV_OFFSET, |
336 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
337 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
338 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
339 | }, |
340 | .idlect_shift = 6, | |
341 | }; | |
342 | ||
343 | static struct clk arminth_ck1510 = { | |
344 | .name = "arminth_ck", | |
897dcded | 345 | .ops = &clkops_null, |
3179a019 | 346 | .parent = &tc_ck.clk, |
3179a019 TL |
347 | .recalc = &followparent_recalc, |
348 | /* Note: On 1510 the frequency follows TC_CK | |
349 | * | |
350 | * 16xx version is in MPU clocks. | |
351 | */ | |
3179a019 TL |
352 | }; |
353 | ||
354 | static struct clk tipb_ck = { | |
355 | /* No-idle controlled by "tc_ck" */ | |
6017e295 | 356 | .name = "tipb_ck", |
897dcded | 357 | .ops = &clkops_null, |
3179a019 | 358 | .parent = &tc_ck.clk, |
3179a019 | 359 | .recalc = &followparent_recalc, |
3179a019 TL |
360 | }; |
361 | ||
362 | static struct clk l3_ocpi_ck = { | |
363 | /* No-idle controlled by "tc_ck" */ | |
364 | .name = "l3_ocpi_ck", | |
548d8495 | 365 | .ops = &clkops_generic, |
3179a019 | 366 | .parent = &tc_ck.clk, |
3179a019 TL |
367 | .enable_reg = (void __iomem *)ARM_IDLECT3, |
368 | .enable_bit = EN_OCPI_CK, | |
369 | .recalc = &followparent_recalc, | |
3179a019 TL |
370 | }; |
371 | ||
372 | static struct clk tc1_ck = { | |
373 | .name = "tc1_ck", | |
548d8495 | 374 | .ops = &clkops_generic, |
3179a019 | 375 | .parent = &tc_ck.clk, |
3179a019 TL |
376 | .enable_reg = (void __iomem *)ARM_IDLECT3, |
377 | .enable_bit = EN_TC1_CK, | |
378 | .recalc = &followparent_recalc, | |
3179a019 TL |
379 | }; |
380 | ||
381 | static struct clk tc2_ck = { | |
382 | .name = "tc2_ck", | |
548d8495 | 383 | .ops = &clkops_generic, |
3179a019 | 384 | .parent = &tc_ck.clk, |
3179a019 TL |
385 | .enable_reg = (void __iomem *)ARM_IDLECT3, |
386 | .enable_bit = EN_TC2_CK, | |
387 | .recalc = &followparent_recalc, | |
3179a019 TL |
388 | }; |
389 | ||
390 | static struct clk dma_ck = { | |
391 | /* No-idle controlled by "tc_ck" */ | |
392 | .name = "dma_ck", | |
897dcded | 393 | .ops = &clkops_null, |
3179a019 | 394 | .parent = &tc_ck.clk, |
3179a019 | 395 | .recalc = &followparent_recalc, |
3179a019 TL |
396 | }; |
397 | ||
398 | static struct clk dma_lcdfree_ck = { | |
399 | .name = "dma_lcdfree_ck", | |
897dcded | 400 | .ops = &clkops_null, |
3179a019 | 401 | .parent = &tc_ck.clk, |
3179a019 | 402 | .recalc = &followparent_recalc, |
3179a019 TL |
403 | }; |
404 | ||
405 | static struct arm_idlect1_clk api_ck = { | |
406 | .clk = { | |
407 | .name = "api_ck", | |
548d8495 | 408 | .ops = &clkops_generic, |
3179a019 | 409 | .parent = &tc_ck.clk, |
d7e8f1f9 | 410 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
411 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
412 | .enable_bit = EN_APICK, | |
413 | .recalc = &followparent_recalc, | |
3179a019 TL |
414 | }, |
415 | .idlect_shift = 8, | |
416 | }; | |
417 | ||
418 | static struct arm_idlect1_clk lb_ck = { | |
419 | .clk = { | |
420 | .name = "lb_ck", | |
548d8495 | 421 | .ops = &clkops_generic, |
3179a019 | 422 | .parent = &tc_ck.clk, |
d7e8f1f9 | 423 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
424 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
425 | .enable_bit = EN_LBCK, | |
426 | .recalc = &followparent_recalc, | |
3179a019 TL |
427 | }, |
428 | .idlect_shift = 4, | |
429 | }; | |
430 | ||
431 | static struct clk rhea1_ck = { | |
432 | .name = "rhea1_ck", | |
897dcded | 433 | .ops = &clkops_null, |
3179a019 | 434 | .parent = &tc_ck.clk, |
3179a019 | 435 | .recalc = &followparent_recalc, |
3179a019 TL |
436 | }; |
437 | ||
438 | static struct clk rhea2_ck = { | |
439 | .name = "rhea2_ck", | |
897dcded | 440 | .ops = &clkops_null, |
3179a019 | 441 | .parent = &tc_ck.clk, |
3179a019 | 442 | .recalc = &followparent_recalc, |
3179a019 TL |
443 | }; |
444 | ||
445 | static struct clk lcd_ck_16xx = { | |
446 | .name = "lcd_ck", | |
548d8495 | 447 | .ops = &clkops_generic, |
3179a019 | 448 | .parent = &ck_dpll1, |
3179a019 TL |
449 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
450 | .enable_bit = EN_LCDCK, | |
451 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
452 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
453 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
454 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
455 | }; |
456 | ||
457 | static struct arm_idlect1_clk lcd_ck_1510 = { | |
458 | .clk = { | |
459 | .name = "lcd_ck", | |
548d8495 | 460 | .ops = &clkops_generic, |
3179a019 | 461 | .parent = &ck_dpll1, |
d7e8f1f9 | 462 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
463 | .enable_reg = (void __iomem *)ARM_IDLECT2, |
464 | .enable_bit = EN_LCDCK, | |
465 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
466 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
467 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
468 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
469 | }, |
470 | .idlect_shift = 3, | |
471 | }; | |
472 | ||
473 | static struct clk uart1_1510 = { | |
474 | .name = "uart1_ck", | |
897dcded | 475 | .ops = &clkops_null, |
3179a019 TL |
476 | /* Direct from ULPD, no real parent */ |
477 | .parent = &armper_ck.clk, | |
478 | .rate = 12000000, | |
d7e8f1f9 | 479 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
3179a019 TL |
480 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
481 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ | |
482 | .set_rate = &omap1_set_uart_rate, | |
483 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
484 | }; |
485 | ||
486 | static struct uart_clk uart1_16xx = { | |
487 | .clk = { | |
488 | .name = "uart1_ck", | |
548d8495 | 489 | .ops = &clkops_uart, |
3179a019 TL |
490 | /* Direct from ULPD, no real parent */ |
491 | .parent = &armper_ck.clk, | |
492 | .rate = 48000000, | |
d7e8f1f9 RK |
493 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
494 | CLOCK_NO_IDLE_PARENT, | |
3179a019 TL |
495 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
496 | .enable_bit = 29, | |
3179a019 TL |
497 | }, |
498 | .sysc_addr = 0xfffb0054, | |
499 | }; | |
500 | ||
501 | static struct clk uart2_ck = { | |
502 | .name = "uart2_ck", | |
897dcded | 503 | .ops = &clkops_null, |
3179a019 TL |
504 | /* Direct from ULPD, no real parent */ |
505 | .parent = &armper_ck.clk, | |
506 | .rate = 12000000, | |
d7e8f1f9 | 507 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
3179a019 TL |
508 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
509 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ | |
510 | .set_rate = &omap1_set_uart_rate, | |
511 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
512 | }; |
513 | ||
514 | static struct clk uart3_1510 = { | |
515 | .name = "uart3_ck", | |
897dcded | 516 | .ops = &clkops_null, |
3179a019 TL |
517 | /* Direct from ULPD, no real parent */ |
518 | .parent = &armper_ck.clk, | |
519 | .rate = 12000000, | |
d7e8f1f9 | 520 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
3179a019 TL |
521 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
522 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ | |
523 | .set_rate = &omap1_set_uart_rate, | |
524 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
525 | }; |
526 | ||
527 | static struct uart_clk uart3_16xx = { | |
528 | .clk = { | |
529 | .name = "uart3_ck", | |
548d8495 | 530 | .ops = &clkops_uart, |
3179a019 TL |
531 | /* Direct from ULPD, no real parent */ |
532 | .parent = &armper_ck.clk, | |
533 | .rate = 48000000, | |
d7e8f1f9 RK |
534 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
535 | CLOCK_NO_IDLE_PARENT, | |
3179a019 TL |
536 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
537 | .enable_bit = 31, | |
3179a019 TL |
538 | }, |
539 | .sysc_addr = 0xfffb9854, | |
540 | }; | |
541 | ||
542 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |
543 | .name = "usb_clko", | |
548d8495 | 544 | .ops = &clkops_generic, |
3179a019 TL |
545 | /* Direct from ULPD, no parent */ |
546 | .rate = 6000000, | |
d7e8f1f9 | 547 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
3179a019 TL |
548 | .enable_reg = (void __iomem *)ULPD_CLOCK_CTRL, |
549 | .enable_bit = USB_MCLK_EN_BIT, | |
3179a019 TL |
550 | }; |
551 | ||
552 | static struct clk usb_hhc_ck1510 = { | |
553 | .name = "usb_hhc_ck", | |
548d8495 | 554 | .ops = &clkops_generic, |
3179a019 TL |
555 | /* Direct from ULPD, no parent */ |
556 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | |
d7e8f1f9 | 557 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
3179a019 TL |
558 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
559 | .enable_bit = USB_HOST_HHC_UHOST_EN, | |
3179a019 TL |
560 | }; |
561 | ||
562 | static struct clk usb_hhc_ck16xx = { | |
563 | .name = "usb_hhc_ck", | |
548d8495 | 564 | .ops = &clkops_generic, |
3179a019 TL |
565 | /* Direct from ULPD, no parent */ |
566 | .rate = 48000000, | |
567 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | |
d7e8f1f9 | 568 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
3179a019 TL |
569 | .enable_reg = (void __iomem *)OTG_BASE + 0x08 /* OTG_SYSCON_2 */, |
570 | .enable_bit = 8 /* UHOST_EN */, | |
3179a019 TL |
571 | }; |
572 | ||
573 | static struct clk usb_dc_ck = { | |
574 | .name = "usb_dc_ck", | |
548d8495 | 575 | .ops = &clkops_generic, |
3179a019 TL |
576 | /* Direct from ULPD, no parent */ |
577 | .rate = 48000000, | |
d7e8f1f9 | 578 | .flags = RATE_FIXED, |
3179a019 TL |
579 | .enable_reg = (void __iomem *)SOFT_REQ_REG, |
580 | .enable_bit = 4, | |
3179a019 TL |
581 | }; |
582 | ||
583 | static struct clk mclk_1510 = { | |
584 | .name = "mclk", | |
548d8495 | 585 | .ops = &clkops_generic, |
3179a019 TL |
586 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
587 | .rate = 12000000, | |
d7e8f1f9 | 588 | .flags = RATE_FIXED, |
b824efae TL |
589 | .enable_reg = (void __iomem *)SOFT_REQ_REG, |
590 | .enable_bit = 6, | |
3179a019 TL |
591 | }; |
592 | ||
593 | static struct clk mclk_16xx = { | |
594 | .name = "mclk", | |
548d8495 | 595 | .ops = &clkops_generic, |
3179a019 | 596 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
3179a019 TL |
597 | .enable_reg = (void __iomem *)COM_CLK_DIV_CTRL_SEL, |
598 | .enable_bit = COM_ULPD_PLL_CLK_REQ, | |
599 | .set_rate = &omap1_set_ext_clk_rate, | |
600 | .round_rate = &omap1_round_ext_clk_rate, | |
601 | .init = &omap1_init_ext_clk, | |
3179a019 TL |
602 | }; |
603 | ||
604 | static struct clk bclk_1510 = { | |
605 | .name = "bclk", | |
548d8495 | 606 | .ops = &clkops_generic, |
3179a019 TL |
607 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
608 | .rate = 12000000, | |
d7e8f1f9 | 609 | .flags = RATE_FIXED, |
3179a019 TL |
610 | }; |
611 | ||
612 | static struct clk bclk_16xx = { | |
613 | .name = "bclk", | |
548d8495 | 614 | .ops = &clkops_generic, |
3179a019 | 615 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
3179a019 TL |
616 | .enable_reg = (void __iomem *)SWD_CLK_DIV_CTRL_SEL, |
617 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, | |
618 | .set_rate = &omap1_set_ext_clk_rate, | |
619 | .round_rate = &omap1_round_ext_clk_rate, | |
620 | .init = &omap1_init_ext_clk, | |
3179a019 TL |
621 | }; |
622 | ||
623 | static struct clk mmc1_ck = { | |
b824efae | 624 | .name = "mmc_ck", |
548d8495 | 625 | .ops = &clkops_generic, |
3179a019 TL |
626 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
627 | .parent = &armper_ck.clk, | |
628 | .rate = 48000000, | |
d7e8f1f9 | 629 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
3179a019 TL |
630 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
631 | .enable_bit = 23, | |
3179a019 TL |
632 | }; |
633 | ||
634 | static struct clk mmc2_ck = { | |
b824efae | 635 | .name = "mmc_ck", |
d8874665 | 636 | .id = 1, |
548d8495 | 637 | .ops = &clkops_generic, |
3179a019 TL |
638 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
639 | .parent = &armper_ck.clk, | |
640 | .rate = 48000000, | |
d7e8f1f9 | 641 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
3179a019 TL |
642 | .enable_reg = (void __iomem *)MOD_CONF_CTRL_0, |
643 | .enable_bit = 20, | |
3179a019 TL |
644 | }; |
645 | ||
646 | static struct clk virtual_ck_mpu = { | |
647 | .name = "mpu", | |
897dcded | 648 | .ops = &clkops_null, |
3179a019 TL |
649 | .parent = &arm_ck, /* Is smarter alias for */ |
650 | .recalc = &followparent_recalc, | |
651 | .set_rate = &omap1_select_table_rate, | |
652 | .round_rate = &omap1_round_to_table_rate, | |
3179a019 TL |
653 | }; |
654 | ||
b824efae TL |
655 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK |
656 | remains active during MPU idle whenever this is enabled */ | |
657 | static struct clk i2c_fck = { | |
658 | .name = "i2c_fck", | |
659 | .id = 1, | |
897dcded | 660 | .ops = &clkops_null, |
d7e8f1f9 | 661 | .flags = CLOCK_NO_IDLE_PARENT, |
b824efae TL |
662 | .parent = &armxor_ck.clk, |
663 | .recalc = &followparent_recalc, | |
b824efae TL |
664 | }; |
665 | ||
90afd5cb TL |
666 | static struct clk i2c_ick = { |
667 | .name = "i2c_ick", | |
668 | .id = 1, | |
897dcded | 669 | .ops = &clkops_null, |
d7e8f1f9 | 670 | .flags = CLOCK_NO_IDLE_PARENT, |
90afd5cb TL |
671 | .parent = &armper_ck.clk, |
672 | .recalc = &followparent_recalc, | |
90afd5cb TL |
673 | }; |
674 | ||
3179a019 | 675 | #endif |