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3179a019 TL |
1 | /* |
2 | * linux/arch/arm/mach-omap1/clock.h | |
3 | * | |
4 | * Copyright (C) 2004 - 2005 Nokia corporation | |
5 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
6 | * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
13 | #ifndef __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
14 | #define __ARCH_ARM_MACH_OMAP1_CLOCK_H | |
15 | ||
8b9dbc16 RK |
16 | static unsigned long omap1_ckctl_recalc(struct clk *clk); |
17 | static unsigned long omap1_watchdog_recalc(struct clk *clk); | |
df2c2e70 | 18 | static int omap1_set_sossi_rate(struct clk *clk, unsigned long rate); |
8b9dbc16 RK |
19 | static unsigned long omap1_sossi_recalc(struct clk *clk); |
20 | static unsigned long omap1_ckctl_recalc_dsp_domain(struct clk *clk); | |
3179a019 | 21 | static int omap1_clk_set_rate_dsp_domain(struct clk * clk, unsigned long rate); |
3179a019 | 22 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate); |
8b9dbc16 | 23 | static unsigned long omap1_uart_recalc(struct clk *clk); |
3179a019 TL |
24 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate); |
25 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate); | |
26 | static void omap1_init_ext_clk(struct clk * clk); | |
27 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate); | |
28 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate); | |
3179a019 | 29 | |
d5e6072b RK |
30 | static int omap1_clk_set_rate_ckctl_arm(struct clk *clk, unsigned long rate); |
31 | static long omap1_clk_round_rate_ckctl_arm(struct clk *clk, unsigned long rate); | |
32 | ||
3179a019 TL |
33 | struct mpu_rate { |
34 | unsigned long rate; | |
35 | unsigned long xtal; | |
36 | unsigned long pll_rate; | |
37 | __u16 ckctl_val; | |
38 | __u16 dpllctl_val; | |
39 | }; | |
40 | ||
41 | struct uart_clk { | |
42 | struct clk clk; | |
43 | unsigned long sysc_addr; | |
44 | }; | |
45 | ||
46 | /* Provide a method for preventing idling some ARM IDLECT clocks */ | |
47 | struct arm_idlect1_clk { | |
48 | struct clk clk; | |
49 | unsigned long no_idle_count; | |
50 | __u8 idlect_shift; | |
51 | }; | |
52 | ||
53 | /* ARM_CKCTL bit shifts */ | |
54 | #define CKCTL_PERDIV_OFFSET 0 | |
55 | #define CKCTL_LCDDIV_OFFSET 2 | |
56 | #define CKCTL_ARMDIV_OFFSET 4 | |
57 | #define CKCTL_DSPDIV_OFFSET 6 | |
58 | #define CKCTL_TCDIV_OFFSET 8 | |
59 | #define CKCTL_DSPMMUDIV_OFFSET 10 | |
60 | /*#define ARM_TIMXO 12*/ | |
61 | #define EN_DSPCK 13 | |
62 | /*#define ARM_INTHCK_SEL 14*/ /* Divide-by-2 for mpu inth_ck */ | |
63 | /* DSP_CKCTL bit shifts */ | |
64 | #define CKCTL_DSPPERDIV_OFFSET 0 | |
65 | ||
66 | /* ARM_IDLECT2 bit shifts */ | |
67 | #define EN_WDTCK 0 | |
68 | #define EN_XORPCK 1 | |
69 | #define EN_PERCK 2 | |
70 | #define EN_LCDCK 3 | |
71 | #define EN_LBCK 4 /* Not on 1610/1710 */ | |
72 | /*#define EN_HSABCK 5*/ | |
73 | #define EN_APICK 6 | |
74 | #define EN_TIMCK 7 | |
75 | #define DMACK_REQ 8 | |
76 | #define EN_GPIOCK 9 /* Not on 1610/1710 */ | |
77 | /*#define EN_LBFREECK 10*/ | |
78 | #define EN_CKOUT_ARM 11 | |
79 | ||
80 | /* ARM_IDLECT3 bit shifts */ | |
81 | #define EN_OCPI_CK 0 | |
82 | #define EN_TC1_CK 2 | |
83 | #define EN_TC2_CK 4 | |
84 | ||
85 | /* DSP_IDLECT2 bit shifts (0,1,2 are same as for ARM_IDLECT2) */ | |
86 | #define EN_DSPTIMCK 5 | |
87 | ||
88 | /* Various register defines for clock controls scattered around OMAP chip */ | |
90afd5cb | 89 | #define SDW_MCLK_INV_BIT 2 /* In ULPD_CLKC_CTRL */ |
3179a019 TL |
90 | #define USB_MCLK_EN_BIT 4 /* In ULPD_CLKC_CTRL */ |
91 | #define USB_HOST_HHC_UHOST_EN 9 /* In MOD_CONF_CTRL_0 */ | |
92 | #define SWD_ULPD_PLL_CLK_REQ 1 /* In SWD_CLK_DIV_CTRL_SEL */ | |
93 | #define COM_ULPD_PLL_CLK_REQ 1 /* In COM_CLK_DIV_CTRL_SEL */ | |
94 | #define SWD_CLK_DIV_CTRL_SEL 0xfffe0874 | |
95 | #define COM_CLK_DIV_CTRL_SEL 0xfffe0878 | |
96 | #define SOFT_REQ_REG 0xfffe0834 | |
97 | #define SOFT_REQ_REG2 0xfffe0880 | |
98 | ||
99 | /*------------------------------------------------------------------------- | |
100 | * Omap1 MPU rate table | |
101 | *-------------------------------------------------------------------------*/ | |
102 | static struct mpu_rate rate_table[] = { | |
103 | /* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL | |
104 | * NOTE: Comment order here is different from bits in CKCTL value: | |
105 | * armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv | |
106 | */ | |
107 | #if defined(CONFIG_OMAP_ARM_216MHZ) | |
108 | { 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */ | |
109 | #endif | |
110 | #if defined(CONFIG_OMAP_ARM_195MHZ) | |
111 | { 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */ | |
112 | #endif | |
113 | #if defined(CONFIG_OMAP_ARM_192MHZ) | |
114 | { 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */ | |
115 | { 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */ | |
116 | { 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */ | |
117 | { 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */ | |
118 | { 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */ | |
119 | #endif | |
120 | #if defined(CONFIG_OMAP_ARM_182MHZ) | |
121 | { 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */ | |
122 | #endif | |
123 | #if defined(CONFIG_OMAP_ARM_168MHZ) | |
124 | { 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */ | |
125 | #endif | |
126 | #if defined(CONFIG_OMAP_ARM_150MHZ) | |
127 | { 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */ | |
128 | #endif | |
129 | #if defined(CONFIG_OMAP_ARM_120MHZ) | |
130 | { 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */ | |
131 | #endif | |
132 | #if defined(CONFIG_OMAP_ARM_96MHZ) | |
133 | { 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */ | |
134 | #endif | |
135 | #if defined(CONFIG_OMAP_ARM_60MHZ) | |
136 | { 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */ | |
137 | #endif | |
138 | #if defined(CONFIG_OMAP_ARM_30MHZ) | |
139 | { 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */ | |
140 | #endif | |
141 | { 0, 0, 0, 0, 0 }, | |
142 | }; | |
143 | ||
144 | /*------------------------------------------------------------------------- | |
145 | * Omap1 clocks | |
146 | *-------------------------------------------------------------------------*/ | |
147 | ||
148 | static struct clk ck_ref = { | |
149 | .name = "ck_ref", | |
897dcded | 150 | .ops = &clkops_null, |
3179a019 | 151 | .rate = 12000000, |
3179a019 TL |
152 | }; |
153 | ||
154 | static struct clk ck_dpll1 = { | |
155 | .name = "ck_dpll1", | |
897dcded | 156 | .ops = &clkops_null, |
3179a019 | 157 | .parent = &ck_ref, |
3179a019 TL |
158 | }; |
159 | ||
160 | static struct arm_idlect1_clk ck_dpll1out = { | |
161 | .clk = { | |
df2c2e70 | 162 | .name = "ck_dpll1out", |
548d8495 | 163 | .ops = &clkops_generic, |
3179a019 | 164 | .parent = &ck_dpll1, |
3f0a820c | 165 | .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT, |
fed415e4 | 166 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
167 | .enable_bit = EN_CKOUT_ARM, |
168 | .recalc = &followparent_recalc, | |
3179a019 TL |
169 | }, |
170 | .idlect_shift = 12, | |
171 | }; | |
172 | ||
df2c2e70 ID |
173 | static struct clk sossi_ck = { |
174 | .name = "ck_sossi", | |
548d8495 | 175 | .ops = &clkops_generic, |
df2c2e70 | 176 | .parent = &ck_dpll1out.clk, |
d7e8f1f9 | 177 | .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT, |
fed415e4 | 178 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1), |
df2c2e70 ID |
179 | .enable_bit = 16, |
180 | .recalc = &omap1_sossi_recalc, | |
181 | .set_rate = &omap1_set_sossi_rate, | |
df2c2e70 ID |
182 | }; |
183 | ||
3179a019 TL |
184 | static struct clk arm_ck = { |
185 | .name = "arm_ck", | |
897dcded | 186 | .ops = &clkops_null, |
3179a019 | 187 | .parent = &ck_dpll1, |
3179a019 TL |
188 | .rate_offset = CKCTL_ARMDIV_OFFSET, |
189 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
190 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
191 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
192 | }; |
193 | ||
194 | static struct arm_idlect1_clk armper_ck = { | |
195 | .clk = { | |
196 | .name = "armper_ck", | |
548d8495 | 197 | .ops = &clkops_generic, |
3179a019 | 198 | .parent = &ck_dpll1, |
d7e8f1f9 | 199 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 200 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
201 | .enable_bit = EN_PERCK, |
202 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
203 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
204 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
205 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
206 | }, |
207 | .idlect_shift = 2, | |
208 | }; | |
209 | ||
210 | static struct clk arm_gpio_ck = { | |
211 | .name = "arm_gpio_ck", | |
548d8495 | 212 | .ops = &clkops_generic, |
3179a019 | 213 | .parent = &ck_dpll1, |
fed415e4 | 214 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
215 | .enable_bit = EN_GPIOCK, |
216 | .recalc = &followparent_recalc, | |
3179a019 TL |
217 | }; |
218 | ||
219 | static struct arm_idlect1_clk armxor_ck = { | |
220 | .clk = { | |
221 | .name = "armxor_ck", | |
548d8495 | 222 | .ops = &clkops_generic, |
3179a019 | 223 | .parent = &ck_ref, |
d7e8f1f9 | 224 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 225 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
226 | .enable_bit = EN_XORPCK, |
227 | .recalc = &followparent_recalc, | |
3179a019 TL |
228 | }, |
229 | .idlect_shift = 1, | |
230 | }; | |
231 | ||
232 | static struct arm_idlect1_clk armtim_ck = { | |
233 | .clk = { | |
234 | .name = "armtim_ck", | |
548d8495 | 235 | .ops = &clkops_generic, |
3179a019 | 236 | .parent = &ck_ref, |
d7e8f1f9 | 237 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 238 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
239 | .enable_bit = EN_TIMCK, |
240 | .recalc = &followparent_recalc, | |
3179a019 TL |
241 | }, |
242 | .idlect_shift = 9, | |
243 | }; | |
244 | ||
245 | static struct arm_idlect1_clk armwdt_ck = { | |
246 | .clk = { | |
247 | .name = "armwdt_ck", | |
548d8495 | 248 | .ops = &clkops_generic, |
3179a019 | 249 | .parent = &ck_ref, |
d7e8f1f9 | 250 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 251 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
252 | .enable_bit = EN_WDTCK, |
253 | .recalc = &omap1_watchdog_recalc, | |
3179a019 TL |
254 | }, |
255 | .idlect_shift = 0, | |
256 | }; | |
257 | ||
258 | static struct clk arminth_ck16xx = { | |
259 | .name = "arminth_ck", | |
897dcded | 260 | .ops = &clkops_null, |
3179a019 | 261 | .parent = &arm_ck, |
3179a019 TL |
262 | .recalc = &followparent_recalc, |
263 | /* Note: On 16xx the frequency can be divided by 2 by programming | |
264 | * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1 | |
265 | * | |
266 | * 1510 version is in TC clocks. | |
267 | */ | |
3179a019 TL |
268 | }; |
269 | ||
270 | static struct clk dsp_ck = { | |
271 | .name = "dsp_ck", | |
548d8495 | 272 | .ops = &clkops_generic, |
3179a019 | 273 | .parent = &ck_dpll1, |
fed415e4 | 274 | .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL), |
3179a019 TL |
275 | .enable_bit = EN_DSPCK, |
276 | .rate_offset = CKCTL_DSPDIV_OFFSET, | |
277 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
278 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
279 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
280 | }; |
281 | ||
282 | static struct clk dspmmu_ck = { | |
283 | .name = "dspmmu_ck", | |
897dcded | 284 | .ops = &clkops_null, |
3179a019 | 285 | .parent = &ck_dpll1, |
3179a019 TL |
286 | .rate_offset = CKCTL_DSPMMUDIV_OFFSET, |
287 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
288 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
289 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
290 | }; |
291 | ||
292 | static struct clk dspper_ck = { | |
293 | .name = "dspper_ck", | |
548d8495 | 294 | .ops = &clkops_dspck, |
3179a019 | 295 | .parent = &ck_dpll1, |
397fcaf7 | 296 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
297 | .enable_bit = EN_PERCK, |
298 | .rate_offset = CKCTL_PERDIV_OFFSET, | |
299 | .recalc = &omap1_ckctl_recalc_dsp_domain, | |
d5e6072b | 300 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
3179a019 | 301 | .set_rate = &omap1_clk_set_rate_dsp_domain, |
3179a019 TL |
302 | }; |
303 | ||
304 | static struct clk dspxor_ck = { | |
305 | .name = "dspxor_ck", | |
548d8495 | 306 | .ops = &clkops_dspck, |
3179a019 | 307 | .parent = &ck_ref, |
397fcaf7 | 308 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
309 | .enable_bit = EN_XORPCK, |
310 | .recalc = &followparent_recalc, | |
3179a019 TL |
311 | }; |
312 | ||
313 | static struct clk dsptim_ck = { | |
314 | .name = "dsptim_ck", | |
548d8495 | 315 | .ops = &clkops_dspck, |
3179a019 | 316 | .parent = &ck_ref, |
397fcaf7 | 317 | .enable_reg = DSP_IDLECT2, |
3179a019 TL |
318 | .enable_bit = EN_DSPTIMCK, |
319 | .recalc = &followparent_recalc, | |
3179a019 TL |
320 | }; |
321 | ||
322 | /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */ | |
323 | static struct arm_idlect1_clk tc_ck = { | |
324 | .clk = { | |
325 | .name = "tc_ck", | |
897dcded | 326 | .ops = &clkops_null, |
3179a019 | 327 | .parent = &ck_dpll1, |
3f0a820c | 328 | .flags = CLOCK_IDLE_CONTROL, |
3179a019 TL |
329 | .rate_offset = CKCTL_TCDIV_OFFSET, |
330 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
331 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
332 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
333 | }, |
334 | .idlect_shift = 6, | |
335 | }; | |
336 | ||
337 | static struct clk arminth_ck1510 = { | |
338 | .name = "arminth_ck", | |
897dcded | 339 | .ops = &clkops_null, |
3179a019 | 340 | .parent = &tc_ck.clk, |
3179a019 TL |
341 | .recalc = &followparent_recalc, |
342 | /* Note: On 1510 the frequency follows TC_CK | |
343 | * | |
344 | * 16xx version is in MPU clocks. | |
345 | */ | |
3179a019 TL |
346 | }; |
347 | ||
348 | static struct clk tipb_ck = { | |
349 | /* No-idle controlled by "tc_ck" */ | |
6017e295 | 350 | .name = "tipb_ck", |
897dcded | 351 | .ops = &clkops_null, |
3179a019 | 352 | .parent = &tc_ck.clk, |
3179a019 | 353 | .recalc = &followparent_recalc, |
3179a019 TL |
354 | }; |
355 | ||
356 | static struct clk l3_ocpi_ck = { | |
357 | /* No-idle controlled by "tc_ck" */ | |
358 | .name = "l3_ocpi_ck", | |
548d8495 | 359 | .ops = &clkops_generic, |
3179a019 | 360 | .parent = &tc_ck.clk, |
fed415e4 | 361 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
3179a019 TL |
362 | .enable_bit = EN_OCPI_CK, |
363 | .recalc = &followparent_recalc, | |
3179a019 TL |
364 | }; |
365 | ||
366 | static struct clk tc1_ck = { | |
367 | .name = "tc1_ck", | |
548d8495 | 368 | .ops = &clkops_generic, |
3179a019 | 369 | .parent = &tc_ck.clk, |
fed415e4 | 370 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
3179a019 TL |
371 | .enable_bit = EN_TC1_CK, |
372 | .recalc = &followparent_recalc, | |
3179a019 TL |
373 | }; |
374 | ||
375 | static struct clk tc2_ck = { | |
376 | .name = "tc2_ck", | |
548d8495 | 377 | .ops = &clkops_generic, |
3179a019 | 378 | .parent = &tc_ck.clk, |
fed415e4 | 379 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3), |
3179a019 TL |
380 | .enable_bit = EN_TC2_CK, |
381 | .recalc = &followparent_recalc, | |
3179a019 TL |
382 | }; |
383 | ||
384 | static struct clk dma_ck = { | |
385 | /* No-idle controlled by "tc_ck" */ | |
386 | .name = "dma_ck", | |
897dcded | 387 | .ops = &clkops_null, |
3179a019 | 388 | .parent = &tc_ck.clk, |
3179a019 | 389 | .recalc = &followparent_recalc, |
3179a019 TL |
390 | }; |
391 | ||
392 | static struct clk dma_lcdfree_ck = { | |
393 | .name = "dma_lcdfree_ck", | |
897dcded | 394 | .ops = &clkops_null, |
3179a019 | 395 | .parent = &tc_ck.clk, |
3179a019 | 396 | .recalc = &followparent_recalc, |
3179a019 TL |
397 | }; |
398 | ||
399 | static struct arm_idlect1_clk api_ck = { | |
400 | .clk = { | |
401 | .name = "api_ck", | |
548d8495 | 402 | .ops = &clkops_generic, |
3179a019 | 403 | .parent = &tc_ck.clk, |
d7e8f1f9 | 404 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 405 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
406 | .enable_bit = EN_APICK, |
407 | .recalc = &followparent_recalc, | |
3179a019 TL |
408 | }, |
409 | .idlect_shift = 8, | |
410 | }; | |
411 | ||
412 | static struct arm_idlect1_clk lb_ck = { | |
413 | .clk = { | |
414 | .name = "lb_ck", | |
548d8495 | 415 | .ops = &clkops_generic, |
3179a019 | 416 | .parent = &tc_ck.clk, |
d7e8f1f9 | 417 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 418 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
419 | .enable_bit = EN_LBCK, |
420 | .recalc = &followparent_recalc, | |
3179a019 TL |
421 | }, |
422 | .idlect_shift = 4, | |
423 | }; | |
424 | ||
425 | static struct clk rhea1_ck = { | |
426 | .name = "rhea1_ck", | |
897dcded | 427 | .ops = &clkops_null, |
3179a019 | 428 | .parent = &tc_ck.clk, |
3179a019 | 429 | .recalc = &followparent_recalc, |
3179a019 TL |
430 | }; |
431 | ||
432 | static struct clk rhea2_ck = { | |
433 | .name = "rhea2_ck", | |
897dcded | 434 | .ops = &clkops_null, |
3179a019 | 435 | .parent = &tc_ck.clk, |
3179a019 | 436 | .recalc = &followparent_recalc, |
3179a019 TL |
437 | }; |
438 | ||
439 | static struct clk lcd_ck_16xx = { | |
440 | .name = "lcd_ck", | |
548d8495 | 441 | .ops = &clkops_generic, |
3179a019 | 442 | .parent = &ck_dpll1, |
fed415e4 | 443 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
444 | .enable_bit = EN_LCDCK, |
445 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
446 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
447 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
448 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
449 | }; |
450 | ||
451 | static struct arm_idlect1_clk lcd_ck_1510 = { | |
452 | .clk = { | |
453 | .name = "lcd_ck", | |
548d8495 | 454 | .ops = &clkops_generic, |
3179a019 | 455 | .parent = &ck_dpll1, |
d7e8f1f9 | 456 | .flags = CLOCK_IDLE_CONTROL, |
fed415e4 | 457 | .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2), |
3179a019 TL |
458 | .enable_bit = EN_LCDCK, |
459 | .rate_offset = CKCTL_LCDDIV_OFFSET, | |
460 | .recalc = &omap1_ckctl_recalc, | |
d5e6072b RK |
461 | .round_rate = omap1_clk_round_rate_ckctl_arm, |
462 | .set_rate = omap1_clk_set_rate_ckctl_arm, | |
3179a019 TL |
463 | }, |
464 | .idlect_shift = 3, | |
465 | }; | |
466 | ||
467 | static struct clk uart1_1510 = { | |
468 | .name = "uart1_ck", | |
897dcded | 469 | .ops = &clkops_null, |
3179a019 TL |
470 | /* Direct from ULPD, no real parent */ |
471 | .parent = &armper_ck.clk, | |
472 | .rate = 12000000, | |
d7e8f1f9 | 473 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 474 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 TL |
475 | .enable_bit = 29, /* Chooses between 12MHz and 48MHz */ |
476 | .set_rate = &omap1_set_uart_rate, | |
477 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
478 | }; |
479 | ||
480 | static struct uart_clk uart1_16xx = { | |
481 | .clk = { | |
482 | .name = "uart1_ck", | |
548d8495 | 483 | .ops = &clkops_uart, |
3179a019 TL |
484 | /* Direct from ULPD, no real parent */ |
485 | .parent = &armper_ck.clk, | |
486 | .rate = 48000000, | |
d7e8f1f9 RK |
487 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
488 | CLOCK_NO_IDLE_PARENT, | |
fed415e4 | 489 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 490 | .enable_bit = 29, |
3179a019 TL |
491 | }, |
492 | .sysc_addr = 0xfffb0054, | |
493 | }; | |
494 | ||
495 | static struct clk uart2_ck = { | |
496 | .name = "uart2_ck", | |
897dcded | 497 | .ops = &clkops_null, |
3179a019 TL |
498 | /* Direct from ULPD, no real parent */ |
499 | .parent = &armper_ck.clk, | |
500 | .rate = 12000000, | |
d7e8f1f9 | 501 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 502 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 TL |
503 | .enable_bit = 30, /* Chooses between 12MHz and 48MHz */ |
504 | .set_rate = &omap1_set_uart_rate, | |
505 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
506 | }; |
507 | ||
508 | static struct clk uart3_1510 = { | |
509 | .name = "uart3_ck", | |
897dcded | 510 | .ops = &clkops_null, |
3179a019 TL |
511 | /* Direct from ULPD, no real parent */ |
512 | .parent = &armper_ck.clk, | |
513 | .rate = 12000000, | |
d7e8f1f9 | 514 | .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 515 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 TL |
516 | .enable_bit = 31, /* Chooses between 12MHz and 48MHz */ |
517 | .set_rate = &omap1_set_uart_rate, | |
518 | .recalc = &omap1_uart_recalc, | |
3179a019 TL |
519 | }; |
520 | ||
521 | static struct uart_clk uart3_16xx = { | |
522 | .clk = { | |
523 | .name = "uart3_ck", | |
548d8495 | 524 | .ops = &clkops_uart, |
3179a019 TL |
525 | /* Direct from ULPD, no real parent */ |
526 | .parent = &armper_ck.clk, | |
527 | .rate = 48000000, | |
d7e8f1f9 RK |
528 | .flags = RATE_FIXED | ENABLE_REG_32BIT | |
529 | CLOCK_NO_IDLE_PARENT, | |
fed415e4 | 530 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 531 | .enable_bit = 31, |
3179a019 TL |
532 | }, |
533 | .sysc_addr = 0xfffb9854, | |
534 | }; | |
535 | ||
536 | static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */ | |
537 | .name = "usb_clko", | |
548d8495 | 538 | .ops = &clkops_generic, |
3179a019 TL |
539 | /* Direct from ULPD, no parent */ |
540 | .rate = 6000000, | |
d7e8f1f9 | 541 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
fed415e4 | 542 | .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL), |
3179a019 | 543 | .enable_bit = USB_MCLK_EN_BIT, |
3179a019 TL |
544 | }; |
545 | ||
546 | static struct clk usb_hhc_ck1510 = { | |
547 | .name = "usb_hhc_ck", | |
548d8495 | 548 | .ops = &clkops_generic, |
3179a019 TL |
549 | /* Direct from ULPD, no parent */ |
550 | .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */ | |
d7e8f1f9 | 551 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
fed415e4 | 552 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 553 | .enable_bit = USB_HOST_HHC_UHOST_EN, |
3179a019 TL |
554 | }; |
555 | ||
556 | static struct clk usb_hhc_ck16xx = { | |
557 | .name = "usb_hhc_ck", | |
548d8495 | 558 | .ops = &clkops_generic, |
3179a019 TL |
559 | /* Direct from ULPD, no parent */ |
560 | .rate = 48000000, | |
561 | /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */ | |
d7e8f1f9 | 562 | .flags = RATE_FIXED | ENABLE_REG_32BIT, |
fed415e4 | 563 | .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */ |
3179a019 | 564 | .enable_bit = 8 /* UHOST_EN */, |
3179a019 TL |
565 | }; |
566 | ||
567 | static struct clk usb_dc_ck = { | |
568 | .name = "usb_dc_ck", | |
548d8495 | 569 | .ops = &clkops_generic, |
3179a019 TL |
570 | /* Direct from ULPD, no parent */ |
571 | .rate = 48000000, | |
d7e8f1f9 | 572 | .flags = RATE_FIXED, |
fed415e4 | 573 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
3179a019 | 574 | .enable_bit = 4, |
3179a019 TL |
575 | }; |
576 | ||
577 | static struct clk mclk_1510 = { | |
578 | .name = "mclk", | |
548d8495 | 579 | .ops = &clkops_generic, |
3179a019 TL |
580 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
581 | .rate = 12000000, | |
d7e8f1f9 | 582 | .flags = RATE_FIXED, |
fed415e4 TL |
583 | .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG), |
584 | .enable_bit = 6, | |
3179a019 TL |
585 | }; |
586 | ||
587 | static struct clk mclk_16xx = { | |
588 | .name = "mclk", | |
548d8495 | 589 | .ops = &clkops_generic, |
3179a019 | 590 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
fed415e4 | 591 | .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL), |
3179a019 TL |
592 | .enable_bit = COM_ULPD_PLL_CLK_REQ, |
593 | .set_rate = &omap1_set_ext_clk_rate, | |
594 | .round_rate = &omap1_round_ext_clk_rate, | |
595 | .init = &omap1_init_ext_clk, | |
3179a019 TL |
596 | }; |
597 | ||
598 | static struct clk bclk_1510 = { | |
599 | .name = "bclk", | |
548d8495 | 600 | .ops = &clkops_generic, |
3179a019 TL |
601 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
602 | .rate = 12000000, | |
d7e8f1f9 | 603 | .flags = RATE_FIXED, |
3179a019 TL |
604 | }; |
605 | ||
606 | static struct clk bclk_16xx = { | |
607 | .name = "bclk", | |
548d8495 | 608 | .ops = &clkops_generic, |
3179a019 | 609 | /* Direct from ULPD, no parent. May be enabled by ext hardware. */ |
fed415e4 | 610 | .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL), |
3179a019 TL |
611 | .enable_bit = SWD_ULPD_PLL_CLK_REQ, |
612 | .set_rate = &omap1_set_ext_clk_rate, | |
613 | .round_rate = &omap1_round_ext_clk_rate, | |
614 | .init = &omap1_init_ext_clk, | |
3179a019 TL |
615 | }; |
616 | ||
617 | static struct clk mmc1_ck = { | |
b824efae | 618 | .name = "mmc_ck", |
548d8495 | 619 | .ops = &clkops_generic, |
3179a019 TL |
620 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
621 | .parent = &armper_ck.clk, | |
622 | .rate = 48000000, | |
d7e8f1f9 | 623 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 624 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 625 | .enable_bit = 23, |
3179a019 TL |
626 | }; |
627 | ||
628 | static struct clk mmc2_ck = { | |
b824efae | 629 | .name = "mmc_ck", |
d8874665 | 630 | .id = 1, |
548d8495 | 631 | .ops = &clkops_generic, |
3179a019 TL |
632 | /* Functional clock is direct from ULPD, interface clock is ARMPER */ |
633 | .parent = &armper_ck.clk, | |
634 | .rate = 48000000, | |
d7e8f1f9 | 635 | .flags = RATE_FIXED | ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT, |
fed415e4 | 636 | .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0), |
3179a019 | 637 | .enable_bit = 20, |
3179a019 TL |
638 | }; |
639 | ||
640 | static struct clk virtual_ck_mpu = { | |
641 | .name = "mpu", | |
897dcded | 642 | .ops = &clkops_null, |
3179a019 TL |
643 | .parent = &arm_ck, /* Is smarter alias for */ |
644 | .recalc = &followparent_recalc, | |
645 | .set_rate = &omap1_select_table_rate, | |
646 | .round_rate = &omap1_round_to_table_rate, | |
3179a019 TL |
647 | }; |
648 | ||
b824efae TL |
649 | /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK |
650 | remains active during MPU idle whenever this is enabled */ | |
651 | static struct clk i2c_fck = { | |
652 | .name = "i2c_fck", | |
653 | .id = 1, | |
897dcded | 654 | .ops = &clkops_null, |
d7e8f1f9 | 655 | .flags = CLOCK_NO_IDLE_PARENT, |
b824efae TL |
656 | .parent = &armxor_ck.clk, |
657 | .recalc = &followparent_recalc, | |
b824efae TL |
658 | }; |
659 | ||
90afd5cb TL |
660 | static struct clk i2c_ick = { |
661 | .name = "i2c_ick", | |
662 | .id = 1, | |
897dcded | 663 | .ops = &clkops_null, |
d7e8f1f9 | 664 | .flags = CLOCK_NO_IDLE_PARENT, |
90afd5cb TL |
665 | .parent = &armper_ck.clk, |
666 | .recalc = &followparent_recalc, | |
90afd5cb TL |
667 | }; |
668 | ||
3179a019 | 669 | #endif |