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495f71db | 1 | //kernel/linux-omap-fsample/arch/arm/mach-omap1/clock.c#2 - edit change 3808 (text) |
3179a019 TL |
2 | /* |
3 | * linux/arch/arm/mach-omap1/clock.c | |
4 | * | |
5 | * Copyright (C) 2004 - 2005 Nokia corporation | |
6 | * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> | |
7 | * | |
8 | * Modified to use omap shared clock framework by | |
9 | * Tony Lindgren <tony@atomide.com> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | #include <linux/module.h> | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/list.h> | |
18 | #include <linux/errno.h> | |
19 | #include <linux/err.h> | |
f8ce2547 | 20 | #include <linux/clk.h> |
3179a019 TL |
21 | |
22 | #include <asm/io.h> | |
90afd5cb | 23 | #include <asm/mach-types.h> |
3179a019 | 24 | |
495f71db | 25 | #include <asm/arch/cpu.h> |
3179a019 TL |
26 | #include <asm/arch/usb.h> |
27 | #include <asm/arch/clock.h> | |
28 | #include <asm/arch/sram.h> | |
29 | ||
30 | #include "clock.h" | |
31 | ||
32 | __u32 arm_idlect1_mask; | |
33 | ||
34 | /*------------------------------------------------------------------------- | |
35 | * Omap1 specific clock functions | |
36 | *-------------------------------------------------------------------------*/ | |
37 | ||
38 | static void omap1_watchdog_recalc(struct clk * clk) | |
39 | { | |
40 | clk->rate = clk->parent->rate / 14; | |
41 | } | |
42 | ||
43 | static void omap1_uart_recalc(struct clk * clk) | |
44 | { | |
45 | unsigned int val = omap_readl(clk->enable_reg); | |
46 | if (val & clk->enable_bit) | |
47 | clk->rate = 48000000; | |
48 | else | |
49 | clk->rate = 12000000; | |
50 | } | |
51 | ||
52 | static int omap1_clk_enable_dsp_domain(struct clk *clk) | |
53 | { | |
54 | int retval; | |
55 | ||
10b55794 | 56 | retval = omap1_clk_enable(&api_ck.clk); |
3179a019 | 57 | if (!retval) { |
10b55794 TL |
58 | retval = omap1_clk_enable_generic(clk); |
59 | omap1_clk_disable(&api_ck.clk); | |
3179a019 TL |
60 | } |
61 | ||
62 | return retval; | |
63 | } | |
64 | ||
65 | static void omap1_clk_disable_dsp_domain(struct clk *clk) | |
66 | { | |
10b55794 TL |
67 | if (omap1_clk_enable(&api_ck.clk) == 0) { |
68 | omap1_clk_disable_generic(clk); | |
69 | omap1_clk_disable(&api_ck.clk); | |
3179a019 TL |
70 | } |
71 | } | |
72 | ||
73 | static int omap1_clk_enable_uart_functional(struct clk *clk) | |
74 | { | |
75 | int ret; | |
76 | struct uart_clk *uclk; | |
77 | ||
10b55794 | 78 | ret = omap1_clk_enable_generic(clk); |
3179a019 TL |
79 | if (ret == 0) { |
80 | /* Set smart idle acknowledgement mode */ | |
81 | uclk = (struct uart_clk *)clk; | |
82 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x10) | 8, | |
83 | uclk->sysc_addr); | |
84 | } | |
85 | ||
86 | return ret; | |
87 | } | |
88 | ||
89 | static void omap1_clk_disable_uart_functional(struct clk *clk) | |
90 | { | |
91 | struct uart_clk *uclk; | |
92 | ||
93 | /* Set force idle acknowledgement mode */ | |
94 | uclk = (struct uart_clk *)clk; | |
95 | omap_writeb((omap_readb(uclk->sysc_addr) & ~0x18), uclk->sysc_addr); | |
96 | ||
10b55794 | 97 | omap1_clk_disable_generic(clk); |
3179a019 TL |
98 | } |
99 | ||
100 | static void omap1_clk_allow_idle(struct clk *clk) | |
101 | { | |
102 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | |
103 | ||
104 | if (!(clk->flags & CLOCK_IDLE_CONTROL)) | |
105 | return; | |
106 | ||
107 | if (iclk->no_idle_count > 0 && !(--iclk->no_idle_count)) | |
108 | arm_idlect1_mask |= 1 << iclk->idlect_shift; | |
109 | } | |
110 | ||
111 | static void omap1_clk_deny_idle(struct clk *clk) | |
112 | { | |
113 | struct arm_idlect1_clk * iclk = (struct arm_idlect1_clk *)clk; | |
114 | ||
115 | if (!(clk->flags & CLOCK_IDLE_CONTROL)) | |
116 | return; | |
117 | ||
118 | if (iclk->no_idle_count++ == 0) | |
119 | arm_idlect1_mask &= ~(1 << iclk->idlect_shift); | |
120 | } | |
121 | ||
122 | static __u16 verify_ckctl_value(__u16 newval) | |
123 | { | |
124 | /* This function checks for following limitations set | |
125 | * by the hardware (all conditions must be true): | |
126 | * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 | |
127 | * ARM_CK >= TC_CK | |
128 | * DSP_CK >= TC_CK | |
129 | * DSPMMU_CK >= TC_CK | |
130 | * | |
131 | * In addition following rules are enforced: | |
132 | * LCD_CK <= TC_CK | |
133 | * ARMPER_CK <= TC_CK | |
134 | * | |
135 | * However, maximum frequencies are not checked for! | |
136 | */ | |
137 | __u8 per_exp; | |
138 | __u8 lcd_exp; | |
139 | __u8 arm_exp; | |
140 | __u8 dsp_exp; | |
141 | __u8 tc_exp; | |
142 | __u8 dspmmu_exp; | |
143 | ||
144 | per_exp = (newval >> CKCTL_PERDIV_OFFSET) & 3; | |
145 | lcd_exp = (newval >> CKCTL_LCDDIV_OFFSET) & 3; | |
146 | arm_exp = (newval >> CKCTL_ARMDIV_OFFSET) & 3; | |
147 | dsp_exp = (newval >> CKCTL_DSPDIV_OFFSET) & 3; | |
148 | tc_exp = (newval >> CKCTL_TCDIV_OFFSET) & 3; | |
149 | dspmmu_exp = (newval >> CKCTL_DSPMMUDIV_OFFSET) & 3; | |
150 | ||
151 | if (dspmmu_exp < dsp_exp) | |
152 | dspmmu_exp = dsp_exp; | |
153 | if (dspmmu_exp > dsp_exp+1) | |
154 | dspmmu_exp = dsp_exp+1; | |
155 | if (tc_exp < arm_exp) | |
156 | tc_exp = arm_exp; | |
157 | if (tc_exp < dspmmu_exp) | |
158 | tc_exp = dspmmu_exp; | |
159 | if (tc_exp > lcd_exp) | |
160 | lcd_exp = tc_exp; | |
161 | if (tc_exp > per_exp) | |
162 | per_exp = tc_exp; | |
163 | ||
164 | newval &= 0xf000; | |
165 | newval |= per_exp << CKCTL_PERDIV_OFFSET; | |
166 | newval |= lcd_exp << CKCTL_LCDDIV_OFFSET; | |
167 | newval |= arm_exp << CKCTL_ARMDIV_OFFSET; | |
168 | newval |= dsp_exp << CKCTL_DSPDIV_OFFSET; | |
169 | newval |= tc_exp << CKCTL_TCDIV_OFFSET; | |
170 | newval |= dspmmu_exp << CKCTL_DSPMMUDIV_OFFSET; | |
171 | ||
172 | return newval; | |
173 | } | |
174 | ||
175 | static int calc_dsor_exp(struct clk *clk, unsigned long rate) | |
176 | { | |
177 | /* Note: If target frequency is too low, this function will return 4, | |
178 | * which is invalid value. Caller must check for this value and act | |
179 | * accordingly. | |
180 | * | |
181 | * Note: This function does not check for following limitations set | |
182 | * by the hardware (all conditions must be true): | |
183 | * DSPMMU_CK == DSP_CK or DSPMMU_CK == DSP_CK/2 | |
184 | * ARM_CK >= TC_CK | |
185 | * DSP_CK >= TC_CK | |
186 | * DSPMMU_CK >= TC_CK | |
187 | */ | |
188 | unsigned long realrate; | |
189 | struct clk * parent; | |
190 | unsigned dsor_exp; | |
191 | ||
192 | if (unlikely(!(clk->flags & RATE_CKCTL))) | |
193 | return -EINVAL; | |
194 | ||
195 | parent = clk->parent; | |
196 | if (unlikely(parent == 0)) | |
197 | return -EIO; | |
198 | ||
199 | realrate = parent->rate; | |
200 | for (dsor_exp=0; dsor_exp<4; dsor_exp++) { | |
201 | if (realrate <= rate) | |
202 | break; | |
203 | ||
204 | realrate /= 2; | |
205 | } | |
206 | ||
207 | return dsor_exp; | |
208 | } | |
209 | ||
210 | static void omap1_ckctl_recalc(struct clk * clk) | |
211 | { | |
212 | int dsor; | |
213 | ||
214 | /* Calculate divisor encoded as 2-bit exponent */ | |
215 | dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); | |
216 | ||
217 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | |
218 | return; /* No change, quick exit */ | |
219 | clk->rate = clk->parent->rate / dsor; | |
220 | ||
221 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
222 | propagate_rate(clk); | |
223 | } | |
224 | ||
225 | static void omap1_ckctl_recalc_dsp_domain(struct clk * clk) | |
226 | { | |
227 | int dsor; | |
228 | ||
229 | /* Calculate divisor encoded as 2-bit exponent | |
230 | * | |
231 | * The clock control bits are in DSP domain, | |
232 | * so api_ck is needed for access. | |
233 | * Note that DSP_CKCTL virt addr = phys addr, so | |
234 | * we must use __raw_readw() instead of omap_readw(). | |
235 | */ | |
10b55794 | 236 | omap1_clk_enable(&api_ck.clk); |
3179a019 | 237 | dsor = 1 << (3 & (__raw_readw(DSP_CKCTL) >> clk->rate_offset)); |
10b55794 | 238 | omap1_clk_disable(&api_ck.clk); |
3179a019 TL |
239 | |
240 | if (unlikely(clk->rate == clk->parent->rate / dsor)) | |
241 | return; /* No change, quick exit */ | |
242 | clk->rate = clk->parent->rate / dsor; | |
243 | ||
244 | if (unlikely(clk->flags & RATE_PROPAGATES)) | |
245 | propagate_rate(clk); | |
246 | } | |
247 | ||
248 | /* MPU virtual clock functions */ | |
249 | static int omap1_select_table_rate(struct clk * clk, unsigned long rate) | |
250 | { | |
251 | /* Find the highest supported frequency <= rate and switch to it */ | |
252 | struct mpu_rate * ptr; | |
253 | ||
254 | if (clk != &virtual_ck_mpu) | |
255 | return -EINVAL; | |
256 | ||
257 | for (ptr = rate_table; ptr->rate; ptr++) { | |
258 | if (ptr->xtal != ck_ref.rate) | |
259 | continue; | |
260 | ||
261 | /* DPLL1 cannot be reprogrammed without risking system crash */ | |
262 | if (likely(ck_dpll1.rate!=0) && ptr->pll_rate != ck_dpll1.rate) | |
263 | continue; | |
264 | ||
265 | /* Can check only after xtal frequency check */ | |
266 | if (ptr->rate <= rate) | |
267 | break; | |
268 | } | |
269 | ||
270 | if (!ptr->rate) | |
271 | return -EINVAL; | |
272 | ||
273 | /* | |
274 | * In most cases we should not need to reprogram DPLL. | |
275 | * Reprogramming the DPLL is tricky, it must be done from SRAM. | |
495f71db | 276 | * (on 730, bit 13 must always be 1) |
3179a019 | 277 | */ |
495f71db BS |
278 | if (cpu_is_omap730()) |
279 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000); | |
280 | else | |
281 | omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val); | |
3179a019 TL |
282 | |
283 | ck_dpll1.rate = ptr->pll_rate; | |
284 | propagate_rate(&ck_dpll1); | |
285 | return 0; | |
286 | } | |
287 | ||
288 | static int omap1_clk_set_rate_dsp_domain(struct clk *clk, unsigned long rate) | |
289 | { | |
290 | int ret = -EINVAL; | |
291 | int dsor_exp; | |
292 | __u16 regval; | |
293 | ||
294 | if (clk->flags & RATE_CKCTL) { | |
295 | dsor_exp = calc_dsor_exp(clk, rate); | |
296 | if (dsor_exp > 3) | |
297 | dsor_exp = -EINVAL; | |
298 | if (dsor_exp < 0) | |
299 | return dsor_exp; | |
300 | ||
301 | regval = __raw_readw(DSP_CKCTL); | |
302 | regval &= ~(3 << clk->rate_offset); | |
303 | regval |= dsor_exp << clk->rate_offset; | |
304 | __raw_writew(regval, DSP_CKCTL); | |
305 | clk->rate = clk->parent->rate / (1 << dsor_exp); | |
306 | ret = 0; | |
307 | } | |
308 | ||
309 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | |
310 | propagate_rate(clk); | |
311 | ||
312 | return ret; | |
313 | } | |
314 | ||
315 | static long omap1_round_to_table_rate(struct clk * clk, unsigned long rate) | |
316 | { | |
317 | /* Find the highest supported frequency <= rate */ | |
318 | struct mpu_rate * ptr; | |
319 | long highest_rate; | |
320 | ||
321 | if (clk != &virtual_ck_mpu) | |
322 | return -EINVAL; | |
323 | ||
324 | highest_rate = -EINVAL; | |
325 | ||
326 | for (ptr = rate_table; ptr->rate; ptr++) { | |
327 | if (ptr->xtal != ck_ref.rate) | |
328 | continue; | |
329 | ||
330 | highest_rate = ptr->rate; | |
331 | ||
332 | /* Can check only after xtal frequency check */ | |
333 | if (ptr->rate <= rate) | |
334 | break; | |
335 | } | |
336 | ||
337 | return highest_rate; | |
338 | } | |
339 | ||
340 | static unsigned calc_ext_dsor(unsigned long rate) | |
341 | { | |
342 | unsigned dsor; | |
343 | ||
344 | /* MCLK and BCLK divisor selection is not linear: | |
345 | * freq = 96MHz / dsor | |
346 | * | |
347 | * RATIO_SEL range: dsor <-> RATIO_SEL | |
348 | * 0..6: (RATIO_SEL+2) <-> (dsor-2) | |
349 | * 6..48: (8+(RATIO_SEL-6)*2) <-> ((dsor-8)/2+6) | |
350 | * Minimum dsor is 2 and maximum is 96. Odd divisors starting from 9 | |
351 | * can not be used. | |
352 | */ | |
353 | for (dsor = 2; dsor < 96; ++dsor) { | |
354 | if ((dsor & 1) && dsor > 8) | |
b824efae | 355 | continue; |
3179a019 TL |
356 | if (rate >= 96000000 / dsor) |
357 | break; | |
358 | } | |
359 | return dsor; | |
360 | } | |
361 | ||
362 | /* Only needed on 1510 */ | |
363 | static int omap1_set_uart_rate(struct clk * clk, unsigned long rate) | |
364 | { | |
365 | unsigned int val; | |
366 | ||
367 | val = omap_readl(clk->enable_reg); | |
368 | if (rate == 12000000) | |
369 | val &= ~(1 << clk->enable_bit); | |
370 | else if (rate == 48000000) | |
371 | val |= (1 << clk->enable_bit); | |
372 | else | |
373 | return -EINVAL; | |
374 | omap_writel(val, clk->enable_reg); | |
375 | clk->rate = rate; | |
376 | ||
377 | return 0; | |
378 | } | |
379 | ||
380 | /* External clock (MCLK & BCLK) functions */ | |
381 | static int omap1_set_ext_clk_rate(struct clk * clk, unsigned long rate) | |
382 | { | |
383 | unsigned dsor; | |
384 | __u16 ratio_bits; | |
385 | ||
386 | dsor = calc_ext_dsor(rate); | |
387 | clk->rate = 96000000 / dsor; | |
388 | if (dsor > 8) | |
389 | ratio_bits = ((dsor - 8) / 2 + 6) << 2; | |
390 | else | |
391 | ratio_bits = (dsor - 2) << 2; | |
392 | ||
393 | ratio_bits |= omap_readw(clk->enable_reg) & ~0xfd; | |
394 | omap_writew(ratio_bits, clk->enable_reg); | |
395 | ||
396 | return 0; | |
397 | } | |
398 | ||
399 | static long omap1_round_ext_clk_rate(struct clk * clk, unsigned long rate) | |
400 | { | |
401 | return 96000000 / calc_ext_dsor(rate); | |
402 | } | |
403 | ||
404 | static void omap1_init_ext_clk(struct clk * clk) | |
405 | { | |
406 | unsigned dsor; | |
407 | __u16 ratio_bits; | |
408 | ||
409 | /* Determine current rate and ensure clock is based on 96MHz APLL */ | |
410 | ratio_bits = omap_readw(clk->enable_reg) & ~1; | |
411 | omap_writew(ratio_bits, clk->enable_reg); | |
412 | ||
413 | ratio_bits = (ratio_bits & 0xfc) >> 2; | |
414 | if (ratio_bits > 6) | |
415 | dsor = (ratio_bits - 6) * 2 + 8; | |
416 | else | |
417 | dsor = ratio_bits + 2; | |
418 | ||
419 | clk-> rate = 96000000 / dsor; | |
420 | } | |
421 | ||
10b55794 | 422 | static int omap1_clk_enable(struct clk *clk) |
3179a019 TL |
423 | { |
424 | int ret = 0; | |
425 | if (clk->usecount++ == 0) { | |
426 | if (likely(clk->parent)) { | |
10b55794 | 427 | ret = omap1_clk_enable(clk->parent); |
3179a019 TL |
428 | |
429 | if (unlikely(ret != 0)) { | |
430 | clk->usecount--; | |
431 | return ret; | |
432 | } | |
433 | ||
434 | if (clk->flags & CLOCK_NO_IDLE_PARENT) | |
6f9c92f1 | 435 | omap1_clk_deny_idle(clk->parent); |
3179a019 TL |
436 | } |
437 | ||
438 | ret = clk->enable(clk); | |
439 | ||
440 | if (unlikely(ret != 0) && clk->parent) { | |
10b55794 | 441 | omap1_clk_disable(clk->parent); |
3179a019 TL |
442 | clk->usecount--; |
443 | } | |
444 | } | |
445 | ||
446 | return ret; | |
447 | } | |
448 | ||
10b55794 | 449 | static void omap1_clk_disable(struct clk *clk) |
3179a019 TL |
450 | { |
451 | if (clk->usecount > 0 && !(--clk->usecount)) { | |
452 | clk->disable(clk); | |
453 | if (likely(clk->parent)) { | |
10b55794 | 454 | omap1_clk_disable(clk->parent); |
3179a019 | 455 | if (clk->flags & CLOCK_NO_IDLE_PARENT) |
6f9c92f1 | 456 | omap1_clk_allow_idle(clk->parent); |
3179a019 TL |
457 | } |
458 | } | |
459 | } | |
460 | ||
10b55794 | 461 | static int omap1_clk_enable_generic(struct clk *clk) |
3179a019 TL |
462 | { |
463 | __u16 regval16; | |
464 | __u32 regval32; | |
465 | ||
466 | if (clk->flags & ALWAYS_ENABLED) | |
467 | return 0; | |
468 | ||
469 | if (unlikely(clk->enable_reg == 0)) { | |
470 | printk(KERN_ERR "clock.c: Enable for %s without enable code\n", | |
471 | clk->name); | |
6f9c92f1 | 472 | return -EINVAL; |
3179a019 TL |
473 | } |
474 | ||
475 | if (clk->flags & ENABLE_REG_32BIT) { | |
476 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
477 | regval32 = __raw_readl(clk->enable_reg); | |
478 | regval32 |= (1 << clk->enable_bit); | |
479 | __raw_writel(regval32, clk->enable_reg); | |
480 | } else { | |
481 | regval32 = omap_readl(clk->enable_reg); | |
482 | regval32 |= (1 << clk->enable_bit); | |
483 | omap_writel(regval32, clk->enable_reg); | |
484 | } | |
485 | } else { | |
486 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
487 | regval16 = __raw_readw(clk->enable_reg); | |
488 | regval16 |= (1 << clk->enable_bit); | |
489 | __raw_writew(regval16, clk->enable_reg); | |
490 | } else { | |
491 | regval16 = omap_readw(clk->enable_reg); | |
492 | regval16 |= (1 << clk->enable_bit); | |
493 | omap_writew(regval16, clk->enable_reg); | |
494 | } | |
495 | } | |
496 | ||
6f9c92f1 | 497 | return 0; |
3179a019 TL |
498 | } |
499 | ||
10b55794 | 500 | static void omap1_clk_disable_generic(struct clk *clk) |
3179a019 TL |
501 | { |
502 | __u16 regval16; | |
503 | __u32 regval32; | |
504 | ||
505 | if (clk->enable_reg == 0) | |
506 | return; | |
507 | ||
508 | if (clk->flags & ENABLE_REG_32BIT) { | |
509 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
510 | regval32 = __raw_readl(clk->enable_reg); | |
511 | regval32 &= ~(1 << clk->enable_bit); | |
512 | __raw_writel(regval32, clk->enable_reg); | |
513 | } else { | |
514 | regval32 = omap_readl(clk->enable_reg); | |
515 | regval32 &= ~(1 << clk->enable_bit); | |
516 | omap_writel(regval32, clk->enable_reg); | |
517 | } | |
518 | } else { | |
519 | if (clk->flags & VIRTUAL_IO_ADDRESS) { | |
520 | regval16 = __raw_readw(clk->enable_reg); | |
521 | regval16 &= ~(1 << clk->enable_bit); | |
522 | __raw_writew(regval16, clk->enable_reg); | |
523 | } else { | |
524 | regval16 = omap_readw(clk->enable_reg); | |
525 | regval16 &= ~(1 << clk->enable_bit); | |
526 | omap_writew(regval16, clk->enable_reg); | |
527 | } | |
528 | } | |
529 | } | |
530 | ||
531 | static long omap1_clk_round_rate(struct clk *clk, unsigned long rate) | |
532 | { | |
533 | int dsor_exp; | |
534 | ||
535 | if (clk->flags & RATE_FIXED) | |
536 | return clk->rate; | |
537 | ||
538 | if (clk->flags & RATE_CKCTL) { | |
539 | dsor_exp = calc_dsor_exp(clk, rate); | |
540 | if (dsor_exp < 0) | |
541 | return dsor_exp; | |
542 | if (dsor_exp > 3) | |
543 | dsor_exp = 3; | |
544 | return clk->parent->rate / (1 << dsor_exp); | |
545 | } | |
546 | ||
547 | if(clk->round_rate != 0) | |
548 | return clk->round_rate(clk, rate); | |
549 | ||
550 | return clk->rate; | |
551 | } | |
552 | ||
553 | static int omap1_clk_set_rate(struct clk *clk, unsigned long rate) | |
554 | { | |
555 | int ret = -EINVAL; | |
556 | int dsor_exp; | |
557 | __u16 regval; | |
558 | ||
559 | if (clk->set_rate) | |
560 | ret = clk->set_rate(clk, rate); | |
561 | else if (clk->flags & RATE_CKCTL) { | |
562 | dsor_exp = calc_dsor_exp(clk, rate); | |
563 | if (dsor_exp > 3) | |
564 | dsor_exp = -EINVAL; | |
565 | if (dsor_exp < 0) | |
566 | return dsor_exp; | |
567 | ||
568 | regval = omap_readw(ARM_CKCTL); | |
569 | regval &= ~(3 << clk->rate_offset); | |
570 | regval |= dsor_exp << clk->rate_offset; | |
571 | regval = verify_ckctl_value(regval); | |
572 | omap_writew(regval, ARM_CKCTL); | |
573 | clk->rate = clk->parent->rate / (1 << dsor_exp); | |
574 | ret = 0; | |
575 | } | |
576 | ||
577 | if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES))) | |
578 | propagate_rate(clk); | |
579 | ||
580 | return ret; | |
581 | } | |
582 | ||
583 | /*------------------------------------------------------------------------- | |
584 | * Omap1 clock reset and init functions | |
585 | *-------------------------------------------------------------------------*/ | |
586 | ||
587 | #ifdef CONFIG_OMAP_RESET_CLOCKS | |
3179a019 | 588 | |
90afd5cb | 589 | static void __init omap1_clk_disable_unused(struct clk *clk) |
3179a019 | 590 | { |
3179a019 TL |
591 | __u32 regval32; |
592 | ||
90afd5cb TL |
593 | /* Clocks in the DSP domain need api_ck. Just assume bootloader |
594 | * has not enabled any DSP clocks */ | |
595 | if ((u32)clk->enable_reg == DSP_IDLECT2) { | |
596 | printk(KERN_INFO "Skipping reset check for DSP domain " | |
597 | "clock \"%s\"\n", clk->name); | |
598 | return; | |
599 | } | |
3179a019 | 600 | |
90afd5cb TL |
601 | /* Is the clock already disabled? */ |
602 | if (clk->flags & ENABLE_REG_32BIT) { | |
603 | if (clk->flags & VIRTUAL_IO_ADDRESS) | |
604 | regval32 = __raw_readl(clk->enable_reg); | |
3179a019 | 605 | else |
90afd5cb TL |
606 | regval32 = omap_readl(clk->enable_reg); |
607 | } else { | |
608 | if (clk->flags & VIRTUAL_IO_ADDRESS) | |
609 | regval32 = __raw_readw(clk->enable_reg); | |
610 | else | |
611 | regval32 = omap_readw(clk->enable_reg); | |
612 | } | |
3179a019 | 613 | |
90afd5cb TL |
614 | if ((regval32 & (1 << clk->enable_bit)) == 0) |
615 | return; | |
3179a019 | 616 | |
90afd5cb TL |
617 | /* FIXME: This clock seems to be necessary but no-one |
618 | * has asked for its activation. */ | |
619 | if (clk == &tc2_ck // FIX: pm.c (SRAM), CCP, Camera | |
620 | || clk == &ck_dpll1out.clk // FIX: SoSSI, SSR | |
621 | || clk == &arm_gpio_ck // FIX: GPIO code for 1510 | |
622 | ) { | |
623 | printk(KERN_INFO "FIXME: Clock \"%s\" seems unused\n", | |
624 | clk->name); | |
625 | return; | |
3179a019 TL |
626 | } |
627 | ||
90afd5cb TL |
628 | printk(KERN_INFO "Disabling unused clock \"%s\"... ", clk->name); |
629 | clk->disable(clk); | |
630 | printk(" done\n"); | |
3179a019 | 631 | } |
3179a019 TL |
632 | |
633 | #else | |
90afd5cb | 634 | #define omap1_clk_disable_unused NULL |
3179a019 TL |
635 | #endif |
636 | ||
637 | static struct clk_functions omap1_clk_functions = { | |
10b55794 TL |
638 | .clk_enable = omap1_clk_enable, |
639 | .clk_disable = omap1_clk_disable, | |
3179a019 TL |
640 | .clk_round_rate = omap1_clk_round_rate, |
641 | .clk_set_rate = omap1_clk_set_rate, | |
90afd5cb | 642 | .clk_disable_unused = omap1_clk_disable_unused, |
3179a019 TL |
643 | }; |
644 | ||
645 | int __init omap1_clk_init(void) | |
646 | { | |
647 | struct clk ** clkp; | |
648 | const struct omap_clock_config *info; | |
649 | int crystal_type = 0; /* Default 12 MHz */ | |
90afd5cb TL |
650 | u32 reg; |
651 | ||
ef772f2e DB |
652 | #ifdef CONFIG_DEBUG_LL |
653 | /* Resets some clocks that may be left on from bootloader, | |
654 | * but leaves serial clocks on. | |
655 | */ | |
656 | omap_writel(0x3 << 29, MOD_CONF_CTRL_0); | |
657 | #endif | |
658 | ||
90afd5cb TL |
659 | /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */ |
660 | reg = omap_readw(SOFT_REQ_REG) & (1 << 4); | |
661 | omap_writew(reg, SOFT_REQ_REG); | |
ef557d76 AZ |
662 | if (!cpu_is_omap15xx()) |
663 | omap_writew(0, SOFT_REQ_REG2); | |
3179a019 | 664 | |
3179a019 TL |
665 | clk_init(&omap1_clk_functions); |
666 | ||
667 | /* By default all idlect1 clocks are allowed to idle */ | |
668 | arm_idlect1_mask = ~0; | |
669 | ||
670 | for (clkp = onchip_clks; clkp < onchip_clks+ARRAY_SIZE(onchip_clks); clkp++) { | |
671 | if (((*clkp)->flags &CLOCK_IN_OMAP1510) && cpu_is_omap1510()) { | |
672 | clk_register(*clkp); | |
673 | continue; | |
674 | } | |
675 | ||
676 | if (((*clkp)->flags &CLOCK_IN_OMAP16XX) && cpu_is_omap16xx()) { | |
677 | clk_register(*clkp); | |
678 | continue; | |
679 | } | |
680 | ||
681 | if (((*clkp)->flags &CLOCK_IN_OMAP730) && cpu_is_omap730()) { | |
682 | clk_register(*clkp); | |
683 | continue; | |
684 | } | |
b824efae TL |
685 | |
686 | if (((*clkp)->flags &CLOCK_IN_OMAP310) && cpu_is_omap310()) { | |
687 | clk_register(*clkp); | |
688 | continue; | |
689 | } | |
3179a019 TL |
690 | } |
691 | ||
692 | info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config); | |
693 | if (info != NULL) { | |
99c658a6 | 694 | if (!cpu_is_omap15xx()) |
3179a019 TL |
695 | crystal_type = info->system_clock_type; |
696 | } | |
697 | ||
698 | #if defined(CONFIG_ARCH_OMAP730) | |
699 | ck_ref.rate = 13000000; | |
700 | #elif defined(CONFIG_ARCH_OMAP16XX) | |
701 | if (crystal_type == 2) | |
702 | ck_ref.rate = 19200000; | |
703 | #endif | |
704 | ||
705 | printk("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", | |
706 | omap_readw(ARM_SYSST), omap_readw(DPLL_CTL), | |
707 | omap_readw(ARM_CKCTL)); | |
708 | ||
709 | /* We want to be in syncronous scalable mode */ | |
710 | omap_writew(0x1000, ARM_SYSST); | |
711 | ||
712 | #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER | |
713 | /* Use values set by bootloader. Determine PLL rate and recalculate | |
714 | * dependent clocks as if kernel had changed PLL or divisors. | |
715 | */ | |
716 | { | |
717 | unsigned pll_ctl_val = omap_readw(DPLL_CTL); | |
718 | ||
719 | ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */ | |
720 | if (pll_ctl_val & 0x10) { | |
721 | /* PLL enabled, apply multiplier and divisor */ | |
722 | if (pll_ctl_val & 0xf80) | |
723 | ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7; | |
724 | ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1; | |
725 | } else { | |
726 | /* PLL disabled, apply bypass divisor */ | |
727 | switch (pll_ctl_val & 0xc) { | |
728 | case 0: | |
729 | break; | |
730 | case 0x4: | |
731 | ck_dpll1.rate /= 2; | |
732 | break; | |
733 | default: | |
734 | ck_dpll1.rate /= 4; | |
735 | break; | |
736 | } | |
737 | } | |
738 | } | |
739 | propagate_rate(&ck_dpll1); | |
740 | #else | |
741 | /* Find the highest supported frequency and enable it */ | |
742 | if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) { | |
743 | printk(KERN_ERR "System frequencies not set. Check your config.\n"); | |
744 | /* Guess sane values (60MHz) */ | |
745 | omap_writew(0x2290, DPLL_CTL); | |
495f71db | 746 | omap_writew(cpu_is_omap730() ? 0x3005 : 0x1005, ARM_CKCTL); |
3179a019 TL |
747 | ck_dpll1.rate = 60000000; |
748 | propagate_rate(&ck_dpll1); | |
749 | } | |
750 | #endif | |
751 | /* Cache rates for clocks connected to ck_ref (not dpll1) */ | |
752 | propagate_rate(&ck_ref); | |
753 | printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): " | |
754 | "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n", | |
755 | ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10, | |
756 | ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10, | |
757 | arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10); | |
758 | ||
495f71db | 759 | #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE) |
3179a019 TL |
760 | /* Select slicer output as OMAP input clock */ |
761 | omap_writew(omap_readw(OMAP730_PCC_UPLD_CTRL) & ~0x1, OMAP730_PCC_UPLD_CTRL); | |
762 | #endif | |
763 | ||
90afd5cb TL |
764 | /* Amstrad Delta wants BCLK high when inactive */ |
765 | if (machine_is_ams_delta()) | |
766 | omap_writel(omap_readl(ULPD_CLOCK_CTRL) | | |
767 | (1 << SDW_MCLK_INV_BIT), | |
768 | ULPD_CLOCK_CTRL); | |
769 | ||
3179a019 | 770 | /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */ |
495f71db BS |
771 | /* (on 730, bit 13 must not be cleared) */ |
772 | if (cpu_is_omap730()) | |
773 | omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); | |
774 | else | |
775 | omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); | |
3179a019 TL |
776 | |
777 | /* Put DSP/MPUI into reset until needed */ | |
778 | omap_writew(0, ARM_RSTCT1); | |
779 | omap_writew(1, ARM_RSTCT2); | |
780 | omap_writew(0x400, ARM_IDLECT1); | |
781 | ||
782 | /* | |
783 | * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8) | |
784 | * of the ARM_IDLECT2 register must be set to zero. The power-on | |
785 | * default value of this bit is one. | |
786 | */ | |
787 | omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */ | |
788 | ||
789 | /* | |
790 | * Only enable those clocks we will need, let the drivers | |
791 | * enable other clocks as necessary | |
792 | */ | |
10b55794 TL |
793 | clk_enable(&armper_ck.clk); |
794 | clk_enable(&armxor_ck.clk); | |
795 | clk_enable(&armtim_ck.clk); /* This should be done by timer code */ | |
3179a019 | 796 | |
b824efae | 797 | if (cpu_is_omap15xx()) |
3179a019 TL |
798 | clk_enable(&arm_gpio_ck); |
799 | ||
800 | return 0; | |
801 | } | |
802 |