[linux-2.6-block.git] / arch / arm / mach-omap1 / ams-delta-fiq.c

/*
 *  Amstrad E3 FIQ handling
 *
 *  Copyright (C) 2009 Janusz Krzysztofik
 *  Copyright (c) 2006 Matt Callow
 *  Copyright (c) 2004 Amstrad Plc
 *  Copyright (C) 2001 RidgeRun, Inc.
 *
 * Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
 * in the MontaVista 2.4 kernel (and the Amstrad changes therein)
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 */
#include <linux/gpio.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/io.h>

#include <mach/board-ams-delta.h>

#include <asm/fiq.h>

#include <mach/ams-delta-fiq.h>

static struct fiq_handler fh = {
	.name	= "ams-delta-fiq"
};

/*
 * This buffer is shared between FIQ and IRQ contexts.
 * The FIQ and IRQ isrs can both read and write it.
 * It is structured as a header section several 32bit slots,
 * followed by the circular buffer where the FIQ isr stores
 * keystrokes received from the qwerty keyboard.
 * See ams-delta-fiq.h for details of offsets.
 */
unsigned int fiq_buffer[1024];
EXPORT_SYMBOL(fiq_buffer);

static unsigned int irq_counter[16];

static irqreturn_t deferred_fiq(int irq, void *dev_id)
{
	int gpio, irq_num, fiq_count;
	struct irq_chip *irq_chip;

	irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));

	/*
	 * For each handled GPIO interrupt, keep calling its interrupt handler
	 * until the IRQ counter catches the FIQ incremented interrupt counter.
	 */
	for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
			gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
		irq_num = gpio_to_irq(gpio);
		fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];

		while (irq_counter[gpio] < fiq_count) {
			if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
				struct irq_data *d = irq_get_irq_data(irq_num);

				/*
				 * It looks like handle_edge_irq() that
				 * OMAP GPIO edge interrupts default to,
				 * expects interrupt already unmasked.
				 */
				if (irq_chip && irq_chip->irq_unmask)
					irq_chip->irq_unmask(d);
			}
			generic_handle_irq(irq_num);

			irq_counter[gpio]++;
		}
	}
	return IRQ_HANDLED;
}

void __init ams_delta_init_fiq(void)
{
	void *fiqhandler_start;
	unsigned int fiqhandler_length;
	struct pt_regs FIQ_regs;
	unsigned long val, offset;
	int i, retval;

	fiqhandler_start = &qwerty_fiqin_start;
	fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
	pr_info("Installing fiq handler from %p, length 0x%x\n",
			fiqhandler_start, fiqhandler_length);

	retval = claim_fiq(&fh);
	if (retval) {
		pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
				retval);
		return;
	}

	retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
			IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
	if (retval < 0) {
		pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
		release_fiq(&fh);
		return;
	}
	/*
	 * Since no set_type() method is provided by OMAP irq chip,
	 * switch to edge triggered interrupt type manually.
	 */
	offset = IRQ_ILR0_REG_OFFSET +
			((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
	val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
	omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);

	set_fiq_handler(fiqhandler_start, fiqhandler_length);

	/*
	 * Initialise the buffer which is shared
	 * between FIQ mode and IRQ mode
	 */
	fiq_buffer[FIQ_GPIO_INT_MASK]	= 0;
	fiq_buffer[FIQ_MASK]		= 0;
	fiq_buffer[FIQ_STATE]		= 0;
	fiq_buffer[FIQ_KEY]		= 0;
	fiq_buffer[FIQ_KEYS_CNT]	= 0;
	fiq_buffer[FIQ_KEYS_HICNT]	= 0;
	fiq_buffer[FIQ_TAIL_OFFSET]	= 0;
	fiq_buffer[FIQ_HEAD_OFFSET]	= 0;
	fiq_buffer[FIQ_BUF_LEN]		= 256;
	fiq_buffer[FIQ_MISSED_KEYS]	= 0;
	fiq_buffer[FIQ_BUFFER_START]	=
			(unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];

	for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
		fiq_buffer[i] = 0;

	/*
	 * FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
	 * will run in an unpredictable context. The fiq_buffer is the FIQ isr's
	 * only means of communication with the IRQ level and other kernel
	 * context code.
	 */
	FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
	set_fiq_regs(&FIQ_regs);

	pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);

	/*
	 * Redirect GPIO interrupts to FIQ
	 */
	offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
	val = omap_readl(OMAP_IH1_BASE + offset) | 1;
	omap_writel(val, OMAP_IH1_BASE + offset);
}
Commit	Line	Data
11f9562a JK	1	/*
	2	* Amstrad E3 FIQ handling
	3	*
	4	* Copyright (C) 2009 Janusz Krzysztofik
	5	* Copyright (c) 2006 Matt Callow
	6	* Copyright (c) 2004 Amstrad Plc
	7	* Copyright (C) 2001 RidgeRun, Inc.
	8	*
	9	* Parts of this code are taken from linux/arch/arm/mach-omap/irq.c
	10	* in the MontaVista 2.4 kernel (and the Amstrad changes therein)
	11	*
	12	* This program is free software; you can redistribute it and/or modify it
	13	* under the terms of the GNU General Public License version 2 as published by
	14	* the Free Software Foundation.
	15	*/
	16	#include <linux/gpio.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/irq.h>
	19	#include <linux/module.h>
	20	#include <linux/io.h>
	21
e27e35ec	22	#include <mach/board-ams-delta.h>
11f9562a JK	23
11f9562a JK	24	#include <asm/fiq.h>
2e3ee9f4	25
11f9562a JK	26	#include <mach/ams-delta-fiq.h>
	27
	28	static struct fiq_handler fh = {
	29	.name = "ams-delta-fiq"
	30	};
	31
	32	/*
	33	* This buffer is shared between FIQ and IRQ contexts.
	34	* The FIQ and IRQ isrs can both read and write it.
	35	* It is structured as a header section several 32bit slots,
	36	* followed by the circular buffer where the FIQ isr stores
	37	* keystrokes received from the qwerty keyboard.
	38	* See ams-delta-fiq.h for details of offsets.
	39	*/
	40	unsigned int fiq_buffer[1024];
	41	EXPORT_SYMBOL(fiq_buffer);
	42
	43	static unsigned int irq_counter[16];
	44
	45	static irqreturn_t deferred_fiq(int irq, void *dev_id)
	46	{
11f9562a	47	int gpio, irq_num, fiq_count;
8435cf75	48	struct irq_chip *irq_chip;
11f9562a	49
b524ca74	50	irq_chip = irq_get_chip(gpio_to_irq(AMS_DELTA_GPIO_PIN_KEYBRD_CLK));
11f9562a JK	51
	52	/*
	53	* For each handled GPIO interrupt, keep calling its interrupt handler
	54	* until the IRQ counter catches the FIQ incremented interrupt counter.
	55	*/
	56	for (gpio = AMS_DELTA_GPIO_PIN_KEYBRD_CLK;
	57	gpio <= AMS_DELTA_GPIO_PIN_HOOK_SWITCH; gpio++) {
	58	irq_num = gpio_to_irq(gpio);
	59	fiq_count = fiq_buffer[FIQ_CNT_INT_00 + gpio];
	60
	61	while (irq_counter[gpio] < fiq_count) {
	62	if (gpio != AMS_DELTA_GPIO_PIN_KEYBRD_CLK) {
a51eef7e LB	63	struct irq_data *d = irq_get_irq_data(irq_num);
a51eef7e LB	64
11f9562a JK	65	/*
	66	* It looks like handle_edge_irq() that
	67	* OMAP GPIO edge interrupts default to,
	68	* expects interrupt already unmasked.
	69	*/
a51eef7e LB	70	if (irq_chip && irq_chip->irq_unmask)
a51eef7e LB	71	irq_chip->irq_unmask(d);
11f9562a JK	72	}
	73	generic_handle_irq(irq_num);
	74
	75	irq_counter[gpio]++;
	76	}
	77	}
	78	return IRQ_HANDLED;
	79	}
	80
	81	void __init ams_delta_init_fiq(void)
	82	{
	83	void *fiqhandler_start;
	84	unsigned int fiqhandler_length;
	85	struct pt_regs FIQ_regs;
	86	unsigned long val, offset;
	87	int i, retval;
	88
	89	fiqhandler_start = &qwerty_fiqin_start;
	90	fiqhandler_length = &qwerty_fiqin_end - &qwerty_fiqin_start;
	91	pr_info("Installing fiq handler from %p, length 0x%x\n",
	92	fiqhandler_start, fiqhandler_length);
	93
	94	retval = claim_fiq(&fh);
	95	if (retval) {
	96	pr_err("ams_delta_init_fiq(): couldn't claim FIQ, ret=%d\n",
	97	retval);
	98	return;
	99	}
	100
	101	retval = request_irq(INT_DEFERRED_FIQ, deferred_fiq,
a7022d60	102	IRQ_TYPE_EDGE_RISING, "deferred_fiq", NULL);
11f9562a JK	103	if (retval < 0) {
	104	pr_err("Failed to get deferred_fiq IRQ, ret=%d\n", retval);
	105	release_fiq(&fh);
	106	return;
	107	}
	108	/*
	109	* Since no set_type() method is provided by OMAP irq chip,
	110	* switch to edge triggered interrupt type manually.
	111	*/
ef5bdccf JK	112	offset = IRQ_ILR0_REG_OFFSET +
ef5bdccf JK	113	((INT_DEFERRED_FIQ - NR_IRQS_LEGACY) & 0x1f) * 0x4;
11f9562a JK	114	val = omap_readl(DEFERRED_FIQ_IH_BASE + offset) & ~(1 << 1);
	115	omap_writel(val, DEFERRED_FIQ_IH_BASE + offset);
	116
	117	set_fiq_handler(fiqhandler_start, fiqhandler_length);
	118
	119	/*
	120	* Initialise the buffer which is shared
	121	* between FIQ mode and IRQ mode
	122	*/
	123	fiq_buffer[FIQ_GPIO_INT_MASK] = 0;
	124	fiq_buffer[FIQ_MASK] = 0;
	125	fiq_buffer[FIQ_STATE] = 0;
	126	fiq_buffer[FIQ_KEY] = 0;
	127	fiq_buffer[FIQ_KEYS_CNT] = 0;
	128	fiq_buffer[FIQ_KEYS_HICNT] = 0;
	129	fiq_buffer[FIQ_TAIL_OFFSET] = 0;
	130	fiq_buffer[FIQ_HEAD_OFFSET] = 0;
	131	fiq_buffer[FIQ_BUF_LEN] = 256;
	132	fiq_buffer[FIQ_MISSED_KEYS] = 0;
	133	fiq_buffer[FIQ_BUFFER_START] =
	134	(unsigned int) &fiq_buffer[FIQ_CIRC_BUFF];
	135
	136	for (i = FIQ_CNT_INT_00; i <= FIQ_CNT_INT_15; i++)
	137	fiq_buffer[i] = 0;
	138
	139	/*
	140	* FIQ mode r9 always points to the fiq_buffer, becauses the FIQ isr
	141	* will run in an unpredictable context. The fiq_buffer is the FIQ isr's
	142	* only means of communication with the IRQ level and other kernel
	143	* context code.
	144	*/
	145	FIQ_regs.ARM_r9 = (unsigned int)fiq_buffer;
	146	set_fiq_regs(&FIQ_regs);
	147
	148	pr_info("request_fiq(): fiq_buffer = %p\n", fiq_buffer);
	149
	150	/*
	151	* Redirect GPIO interrupts to FIQ
	152	*/
ef5bdccf	153	offset = IRQ_ILR0_REG_OFFSET + (INT_GPIO_BANK1 - NR_IRQS_LEGACY) * 0x4;
11f9562a JK	154	val = omap_readl(OMAP_IH1_BASE + offset) \| 1;
	155	omap_writel(val, OMAP_IH1_BASE + offset);
	156	}