[linux-2.6-block.git] / arch / arm / mach-omap1 / ams-delta-fiq-handler.S

/* SPDX-License-Identifier: GPL-2.0-only */
/*
 *  linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
 *
 *  Based on  linux/arch/arm/lib/floppydma.S
 *  Renamed and modified to work with 2.6 kernel by Matt Callow
 *  Copyright (C) 1995, 1996 Russell King
 *  Copyright (C) 2004 Pete Trapps
 *  Copyright (C) 2006 Matt Callow
 *  Copyright (C) 2010 Janusz Krzysztofik
 */

#include <linux/linkage.h>
#include <linux/platform_data/ams-delta-fiq.h>
#include <linux/platform_data/gpio-omap.h>

#include <asm/assembler.h>

#include "ams-delta-fiq.h"
#include "board-ams-delta.h"
#include "iomap.h"
#include "soc.h"

/*
 * OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
 * Unfortunately, it was not placed in a separate header file.
 */
#define OMAP1510_GPIO_BASE		0xFFFCE000

/* GPIO register bitmasks */
#define KEYBRD_DATA_MASK		(0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA)
#define KEYBRD_CLK_MASK			(0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK)
#define MODEM_IRQ_MASK			(0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ)
#define HOOK_SWITCH_MASK		(0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH)
#define OTHERS_MASK			(MODEM_IRQ_MASK | HOOK_SWITCH_MASK)

/* IRQ handler register bitmasks */
#define DEFERRED_FIQ_MASK		OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
#define GPIO_BANK1_MASK  		OMAP_IRQ_BIT(INT_GPIO_BANK1)

/* Driver buffer byte offsets */
#define BUF_MASK			(FIQ_MASK * 4)
#define BUF_STATE			(FIQ_STATE * 4)
#define BUF_KEYS_CNT			(FIQ_KEYS_CNT * 4)
#define BUF_TAIL_OFFSET			(FIQ_TAIL_OFFSET * 4)
#define BUF_HEAD_OFFSET			(FIQ_HEAD_OFFSET * 4)
#define BUF_BUF_LEN			(FIQ_BUF_LEN * 4)
#define BUF_KEY				(FIQ_KEY * 4)
#define BUF_MISSED_KEYS			(FIQ_MISSED_KEYS * 4)
#define BUF_BUFFER_START		(FIQ_BUFFER_START * 4)
#define BUF_GPIO_INT_MASK		(FIQ_GPIO_INT_MASK * 4)
#define BUF_KEYS_HICNT			(FIQ_KEYS_HICNT * 4)
#define BUF_IRQ_PEND			(FIQ_IRQ_PEND * 4)
#define BUF_SIR_CODE_L1			(FIQ_SIR_CODE_L1 * 4)
#define BUF_SIR_CODE_L2			(IRQ_SIR_CODE_L2 * 4)
#define BUF_CNT_INT_00			(FIQ_CNT_INT_00 * 4)
#define BUF_CNT_INT_KEY			(FIQ_CNT_INT_KEY * 4)
#define BUF_CNT_INT_MDM			(FIQ_CNT_INT_MDM * 4)
#define BUF_CNT_INT_03			(FIQ_CNT_INT_03 * 4)
#define BUF_CNT_INT_HSW			(FIQ_CNT_INT_HSW * 4)
#define BUF_CNT_INT_05			(FIQ_CNT_INT_05 * 4)
#define BUF_CNT_INT_06			(FIQ_CNT_INT_06 * 4)
#define BUF_CNT_INT_07			(FIQ_CNT_INT_07 * 4)
#define BUF_CNT_INT_08			(FIQ_CNT_INT_08 * 4)
#define BUF_CNT_INT_09			(FIQ_CNT_INT_09 * 4)
#define BUF_CNT_INT_10			(FIQ_CNT_INT_10 * 4)
#define BUF_CNT_INT_11			(FIQ_CNT_INT_11 * 4)
#define BUF_CNT_INT_12			(FIQ_CNT_INT_12 * 4)
#define BUF_CNT_INT_13			(FIQ_CNT_INT_13 * 4)
#define BUF_CNT_INT_14			(FIQ_CNT_INT_14 * 4)
#define BUF_CNT_INT_15			(FIQ_CNT_INT_15 * 4)
#define BUF_CIRC_BUFF			(FIQ_CIRC_BUFF * 4)


/*
 * Register usage
 * r8  - temporary
 * r9  - the driver buffer
 * r10 - temporary
 * r11 - interrupts mask
 * r12 - base pointers
 * r13 - interrupts status
 */

	.text

	.global qwerty_fiqin_end

ENTRY(qwerty_fiqin_start)
	@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
	@ FIQ intrrupt handler
	ldr r12, omap_ih1_base			@ set pointer to level1 handler

	ldr r11, [r12, #IRQ_MIR_REG_OFFSET]	@ fetch interrupts mask

	ldr r13, [r12, #IRQ_ITR_REG_OFFSET]	@ fetch interrupts status
	bics r13, r13, r11			@ clear masked - any left?
	beq exit				@ none - spurious FIQ? exit

	ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET]	@ get requested interrupt number

	mov r8, #2				@ reset FIQ agreement
	str r8, [r12, #IRQ_CONTROL_REG_OFFSET]

	cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY)	@ is it GPIO interrupt?
	beq gpio				@ yes - process it

	mov r8, #1
	orr r8, r11, r8, lsl r10		@ mask spurious interrupt
	str r8, [r12, #IRQ_MIR_REG_OFFSET]
exit:
	subs	pc, lr, #4			@ return from FIQ
	@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@


	@@@@@@@@@@@@@@@@@@@@@@@@@@@
gpio:	@ GPIO bank interrupt handler
	ldr r12, omap1510_gpio_base		@ set base pointer to GPIO bank

	ldr r11, [r12, #OMAP1510_GPIO_INT_MASK]	@ fetch GPIO interrupts mask
restart:
	ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS]	@ fetch status bits
	bics r13, r13, r11			@ clear masked - any left?
	beq exit				@ no - spurious interrupt? exit

	orr r11, r11, r13			@ mask all requested interrupts
	str r11, [r12, #OMAP1510_GPIO_INT_MASK]

	ands r10, r13, #KEYBRD_CLK_MASK		@ extract keyboard status - set?
	beq hksw				@ no - try next source


	@@@@@@@@@@@@@@@@@@@@@@
	@ Keyboard clock FIQ mode interrupt handler
	@ r10 now contains KEYBRD_CLK_MASK, use it
	str r10, [r12, #OMAP1510_GPIO_INT_STATUS]	@ ack the interrupt
	bic r11, r11, r10				@ unmask it
	str r11, [r12, #OMAP1510_GPIO_INT_MASK]

	@ Process keyboard data
	ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT]	@ fetch GPIO input

	ldr r10, [r9, #BUF_STATE]		@ fetch kbd interface state
	cmp r10, #0				@ are we expecting start bit?
	bne data				@ no - go to data processing

	ands r8, r8, #KEYBRD_DATA_MASK		@ check start bit - detected?
	beq hksw				@ no - try next source

	@ r8 contains KEYBRD_DATA_MASK, use it
	str r8, [r9, #BUF_STATE]		@ enter data processing state
	@ r10 already contains 0, reuse it
	str r10, [r9, #BUF_KEY]			@ clear keycode
	mov r10, #2				@ reset input bit mask
	str r10, [r9, #BUF_MASK]

	@ Mask other GPIO line interrupts till key done
	str r11, [r9, #BUF_GPIO_INT_MASK]	@ save mask for later restore
	mvn r11, #KEYBRD_CLK_MASK		@ prepare all except kbd mask
	str r11, [r12, #OMAP1510_GPIO_INT_MASK]	@ store into the mask register

	b restart				@ restart

data:	ldr r10, [r9, #BUF_MASK]		@ fetch current input bit mask

	@ r8 still contains GPIO input bits
	ands r8, r8, #KEYBRD_DATA_MASK		@ is keyboard data line low?
	ldreq r8, [r9, #BUF_KEY]		@ yes - fetch collected so far,
	orreq r8, r8, r10			@ set 1 at current mask position
	streq r8, [r9, #BUF_KEY]		@ and save back

	mov r10, r10, lsl #1			@ shift mask left
	bics r10, r10, #0x800			@ have we got all the bits?
	strne r10, [r9, #BUF_MASK]		@ not yet - store the mask
	bne restart				@ and restart

	@ r10 already contains 0, reuse it
	str r10, [r9, #BUF_STATE]		@ reset state to start

	@ Key done - restore interrupt mask
	ldr r10, [r9, #BUF_GPIO_INT_MASK]	@ fetch saved mask
	and r11, r11, r10			@ unmask all saved as unmasked
	str r11, [r12, #OMAP1510_GPIO_INT_MASK]	@ restore into the mask register

	@ Try appending the keycode to the circular buffer
	ldr r10, [r9, #BUF_KEYS_CNT]		@ get saved keystrokes count
	ldr r8, [r9, #BUF_BUF_LEN]		@ get buffer size
	cmp r10, r8				@ is buffer full?
	beq hksw				@ yes - key lost, next source

	add r10, r10, #1			@ incremet keystrokes counter
	str r10, [r9, #BUF_KEYS_CNT]

	ldr r10, [r9, #BUF_TAIL_OFFSET]		@ get buffer tail offset
	@ r8 already contains buffer size
	cmp r10, r8				@ end of buffer?
	moveq r10, #0				@ yes - rewind to buffer start

	ldr r12, [r9, #BUF_BUFFER_START]	@ get buffer start address
	add r12, r12, r10, LSL #2		@ calculate buffer tail address
	ldr r8, [r9, #BUF_KEY]			@ get last keycode
	str r8, [r12]				@ append it to the buffer tail

	add r10, r10, #1			@ increment buffer tail offset
	str r10, [r9, #BUF_TAIL_OFFSET]

	ldr r10, [r9, #BUF_CNT_INT_KEY]		@ increment interrupts counter
	add r10, r10, #1
	str r10, [r9, #BUF_CNT_INT_KEY]
	@@@@@@@@@@@@@@@@@@@@@@@@


hksw:	@Is hook switch interrupt requested?
	tst r13, #HOOK_SWITCH_MASK 		@ is hook switch status bit set?
	beq mdm					@ no - try next source


	@@@@@@@@@@@@@@@@@@@@@@@@
	@ Hook switch interrupt FIQ mode simple handler

	@ Don't toggle active edge, the switch always bounces

	@ Increment hook switch interrupt counter
	ldr r10, [r9, #BUF_CNT_INT_HSW]
	add r10, r10, #1
	str r10, [r9, #BUF_CNT_INT_HSW]
	@@@@@@@@@@@@@@@@@@@@@@@@


mdm:	@Is it a modem interrupt?
	tst r13, #MODEM_IRQ_MASK 		@ is modem status bit set?
	beq irq					@ no - check for next interrupt


	@@@@@@@@@@@@@@@@@@@@@@@@
	@ Modem FIQ mode interrupt handler stub

	@ Increment modem interrupt counter
	ldr r10, [r9, #BUF_CNT_INT_MDM]
	add r10, r10, #1
	str r10, [r9, #BUF_CNT_INT_MDM]
	@@@@@@@@@@@@@@@@@@@@@@@@


irq:	@ Place deferred_fiq interrupt request
	ldr r12, deferred_fiq_ih_base		@ set pointer to IRQ handler
	mov r10, #DEFERRED_FIQ_MASK		@ set deferred_fiq bit
	str r10, [r12, #IRQ_ISR_REG_OFFSET] 	@ place it in the ISR register

	ldr r12, omap1510_gpio_base		@ set pointer back to GPIO bank
	b restart				@ check for next GPIO interrupt
	@@@@@@@@@@@@@@@@@@@@@@@@@@@


/*
 * Virtual addresses for IO
 */
omap_ih1_base:
	.word OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
deferred_fiq_ih_base:
	.word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE)
omap1510_gpio_base:
	.word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE)
qwerty_fiqin_end:

/*
 * Check the size of the FIQ,
 * it cannot go beyond 0xffff0200, and is copied to 0xffff001c
 */
.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c)
	.err
.endif
Commit	Line	Data
d2912cb1	1	/* SPDX-License-Identifier: GPL-2.0-only */
60c3bf3f JK	2	/*
	3	* linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
	4	*
	5	* Based on linux/arch/arm/lib/floppydma.S
	6	* Renamed and modified to work with 2.6 kernel by Matt Callow
	7	* Copyright (C) 1995, 1996 Russell King
	8	* Copyright (C) 2004 Pete Trapps
	9	* Copyright (C) 2006 Matt Callow
	10	* Copyright (C) 2010 Janusz Krzysztofik
60c3bf3f JK	11	*/
	12
	13	#include <linux/linkage.h>
dc8fbeb0	14	#include <linux/platform_data/ams-delta-fiq.h>
26683316	15	#include <linux/platform_data/gpio-omap.h>
60c3bf3f	16
dc8fbeb0	17	#include <asm/assembler.h>
60c3bf3f	18
dc8fbeb0	19	#include "ams-delta-fiq.h"
0a48a413	20	#include "board-ams-delta.h"
2e3ee9f4	21	#include "iomap.h"
685e2d08	22	#include "soc.h"
2e3ee9f4	23
60c3bf3f	24	/*
26683316 JK	25	* OMAP1510 GPIO related symbol copied from arch/arm/mach-omap1/gpio15xx.c.
26683316 JK	26	* Unfortunately, it was not placed in a separate header file.
60c3bf3f JK	27	*/
60c3bf3f JK	28	#define OMAP1510_GPIO_BASE 0xFFFCE000
60c3bf3f JK	29
	30	/* GPIO register bitmasks */
	31	#define KEYBRD_DATA_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_DATA)
	32	#define KEYBRD_CLK_MASK (0x1 << AMS_DELTA_GPIO_PIN_KEYBRD_CLK)
	33	#define MODEM_IRQ_MASK (0x1 << AMS_DELTA_GPIO_PIN_MODEM_IRQ)
	34	#define HOOK_SWITCH_MASK (0x1 << AMS_DELTA_GPIO_PIN_HOOK_SWITCH)
	35	#define OTHERS_MASK (MODEM_IRQ_MASK \| HOOK_SWITCH_MASK)
	36
	37	/* IRQ handler register bitmasks */
ef5bdccf JK	38	#define DEFERRED_FIQ_MASK OMAP_IRQ_BIT(INT_DEFERRED_FIQ)
ef5bdccf JK	39	#define GPIO_BANK1_MASK OMAP_IRQ_BIT(INT_GPIO_BANK1)
60c3bf3f JK	40
	41	/* Driver buffer byte offsets */
	42	#define BUF_MASK (FIQ_MASK * 4)
	43	#define BUF_STATE (FIQ_STATE * 4)
	44	#define BUF_KEYS_CNT (FIQ_KEYS_CNT * 4)
	45	#define BUF_TAIL_OFFSET (FIQ_TAIL_OFFSET * 4)
	46	#define BUF_HEAD_OFFSET (FIQ_HEAD_OFFSET * 4)
	47	#define BUF_BUF_LEN (FIQ_BUF_LEN * 4)
	48	#define BUF_KEY (FIQ_KEY * 4)
	49	#define BUF_MISSED_KEYS (FIQ_MISSED_KEYS * 4)
	50	#define BUF_BUFFER_START (FIQ_BUFFER_START * 4)
	51	#define BUF_GPIO_INT_MASK (FIQ_GPIO_INT_MASK * 4)
	52	#define BUF_KEYS_HICNT (FIQ_KEYS_HICNT * 4)
	53	#define BUF_IRQ_PEND (FIQ_IRQ_PEND * 4)
	54	#define BUF_SIR_CODE_L1 (FIQ_SIR_CODE_L1 * 4)
	55	#define BUF_SIR_CODE_L2 (IRQ_SIR_CODE_L2 * 4)
	56	#define BUF_CNT_INT_00 (FIQ_CNT_INT_00 * 4)
	57	#define BUF_CNT_INT_KEY (FIQ_CNT_INT_KEY * 4)
	58	#define BUF_CNT_INT_MDM (FIQ_CNT_INT_MDM * 4)
	59	#define BUF_CNT_INT_03 (FIQ_CNT_INT_03 * 4)
	60	#define BUF_CNT_INT_HSW (FIQ_CNT_INT_HSW * 4)
	61	#define BUF_CNT_INT_05 (FIQ_CNT_INT_05 * 4)
	62	#define BUF_CNT_INT_06 (FIQ_CNT_INT_06 * 4)
	63	#define BUF_CNT_INT_07 (FIQ_CNT_INT_07 * 4)
	64	#define BUF_CNT_INT_08 (FIQ_CNT_INT_08 * 4)
	65	#define BUF_CNT_INT_09 (FIQ_CNT_INT_09 * 4)
	66	#define BUF_CNT_INT_10 (FIQ_CNT_INT_10 * 4)
	67	#define BUF_CNT_INT_11 (FIQ_CNT_INT_11 * 4)
	68	#define BUF_CNT_INT_12 (FIQ_CNT_INT_12 * 4)
	69	#define BUF_CNT_INT_13 (FIQ_CNT_INT_13 * 4)
	70	#define BUF_CNT_INT_14 (FIQ_CNT_INT_14 * 4)
	71	#define BUF_CNT_INT_15 (FIQ_CNT_INT_15 * 4)
	72	#define BUF_CIRC_BUFF (FIQ_CIRC_BUFF * 4)
	73
	74
	75	/*
25985edc	76	* Register usage
60c3bf3f JK	77	* r8 - temporary
	78	* r9 - the driver buffer
	79	* r10 - temporary
	80	* r11 - interrupts mask
	81	* r12 - base pointers
	82	* r13 - interrupts status
	83	*/
	84
	85	.text
	86
	87	.global qwerty_fiqin_end
	88
	89	ENTRY(qwerty_fiqin_start)
	90	@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
	91	@ FIQ intrrupt handler
	92	ldr r12, omap_ih1_base @ set pointer to level1 handler
	93
	94	ldr r11, [r12, #IRQ_MIR_REG_OFFSET] @ fetch interrupts mask
	95
	96	ldr r13, [r12, #IRQ_ITR_REG_OFFSET] @ fetch interrupts status
	97	bics r13, r13, r11 @ clear masked - any left?
	98	beq exit @ none - spurious FIQ? exit
	99
	100	ldr r10, [r12, #IRQ_SIR_FIQ_REG_OFFSET] @ get requested interrupt number
	101
	102	mov r8, #2 @ reset FIQ agreement
	103	str r8, [r12, #IRQ_CONTROL_REG_OFFSET]
	104
ef5bdccf	105	cmp r10, #(INT_GPIO_BANK1 - NR_IRQS_LEGACY) @ is it GPIO interrupt?
60c3bf3f JK	106	beq gpio @ yes - process it
	107
	108	mov r8, #1
	109	orr r8, r11, r8, lsl r10 @ mask spurious interrupt
	110	str r8, [r12, #IRQ_MIR_REG_OFFSET]
	111	exit:
	112	subs pc, lr, #4 @ return from FIQ
	113	@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
	114
	115
	116	@@@@@@@@@@@@@@@@@@@@@@@@@@@
	117	gpio: @ GPIO bank interrupt handler
	118	ldr r12, omap1510_gpio_base @ set base pointer to GPIO bank
	119
	120	ldr r11, [r12, #OMAP1510_GPIO_INT_MASK] @ fetch GPIO interrupts mask
	121	restart:
	122	ldr r13, [r12, #OMAP1510_GPIO_INT_STATUS] @ fetch status bits
	123	bics r13, r13, r11 @ clear masked - any left?
	124	beq exit @ no - spurious interrupt? exit
	125
	126	orr r11, r11, r13 @ mask all requested interrupts
	127	str r11, [r12, #OMAP1510_GPIO_INT_MASK]
	128
	129	ands r10, r13, #KEYBRD_CLK_MASK @ extract keyboard status - set?
	130	beq hksw @ no - try next source
	131
	132
	133	@@@@@@@@@@@@@@@@@@@@@@
	134	@ Keyboard clock FIQ mode interrupt handler
	135	@ r10 now contains KEYBRD_CLK_MASK, use it
	136	str r10, [r12, #OMAP1510_GPIO_INT_STATUS] @ ack the interrupt
	137	bic r11, r11, r10 @ unmask it
	138	str r11, [r12, #OMAP1510_GPIO_INT_MASK]
	139
	140	@ Process keyboard data
	141	ldr r8, [r12, #OMAP1510_GPIO_DATA_INPUT] @ fetch GPIO input
	142
	143	ldr r10, [r9, #BUF_STATE] @ fetch kbd interface state
	144	cmp r10, #0 @ are we expecting start bit?
	145	bne data @ no - go to data processing
	146
	147	ands r8, r8, #KEYBRD_DATA_MASK @ check start bit - detected?
	148	beq hksw @ no - try next source
	149
	150	@ r8 contains KEYBRD_DATA_MASK, use it
	151	str r8, [r9, #BUF_STATE] @ enter data processing state
	152	@ r10 already contains 0, reuse it
	153	str r10, [r9, #BUF_KEY] @ clear keycode
	154	mov r10, #2 @ reset input bit mask
	155	str r10, [r9, #BUF_MASK]
	156
	157	@ Mask other GPIO line interrupts till key done
	158	str r11, [r9, #BUF_GPIO_INT_MASK] @ save mask for later restore
	159	mvn r11, #KEYBRD_CLK_MASK @ prepare all except kbd mask
	160	str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ store into the mask register
	161
	162	b restart @ restart
	163
	164	data: ldr r10, [r9, #BUF_MASK] @ fetch current input bit mask
	165
	166	@ r8 still contains GPIO input bits
	167	ands r8, r8, #KEYBRD_DATA_MASK @ is keyboard data line low?
	168	ldreq r8, [r9, #BUF_KEY] @ yes - fetch collected so far,
	169	orreq r8, r8, r10 @ set 1 at current mask position
170	streq r8, [r9, #BUF_KEY] @ and save back
171
172	mov r10, r10, lsl #1 @ shift mask left
173	bics r10, r10, #0x800 @ have we got all the bits?
174	strne r10, [r9, #BUF_MASK] @ not yet - store the mask
175	bne restart @ and restart
176
177	@ r10 already contains 0, reuse it
178	str r10, [r9, #BUF_STATE] @ reset state to start
179
180	@ Key done - restore interrupt mask
181	ldr r10, [r9, #BUF_GPIO_INT_MASK] @ fetch saved mask
182	and r11, r11, r10 @ unmask all saved as unmasked
183	str r11, [r12, #OMAP1510_GPIO_INT_MASK] @ restore into the mask register
184
185	@ Try appending the keycode to the circular buffer
186	ldr r10, [r9, #BUF_KEYS_CNT] @ get saved keystrokes count
187	ldr r8, [r9, #BUF_BUF_LEN] @ get buffer size
188	cmp r10, r8 @ is buffer full?
189	beq hksw @ yes - key lost, next source
190
191	add r10, r10, #1 @ incremet keystrokes counter
192	str r10, [r9, #BUF_KEYS_CNT]
193
194	ldr r10, [r9, #BUF_TAIL_OFFSET] @ get buffer tail offset
195	@ r8 already contains buffer size
196	cmp r10, r8 @ end of buffer?
197	moveq r10, #0 @ yes - rewind to buffer start
198
199	ldr r12, [r9, #BUF_BUFFER_START] @ get buffer start address
200	add r12, r12, r10, LSL #2 @ calculate buffer tail address
201	ldr r8, [r9, #BUF_KEY] @ get last keycode
202	str r8, [r12] @ append it to the buffer tail
203
204	add r10, r10, #1 @ increment buffer tail offset
205	str r10, [r9, #BUF_TAIL_OFFSET]
206
207	ldr r10, [r9, #BUF_CNT_INT_KEY] @ increment interrupts counter
208	add r10, r10, #1
209	str r10, [r9, #BUF_CNT_INT_KEY]
210	@@@@@@@@@@@@@@@@@@@@@@@@
211
212
213	hksw: @Is hook switch interrupt requested?
214	tst r13, #HOOK_SWITCH_MASK @ is hook switch status bit set?
215	beq mdm @ no - try next source
216
217
218	@@@@@@@@@@@@@@@@@@@@@@@@
219	@ Hook switch interrupt FIQ mode simple handler
220
221	@ Don't toggle active edge, the switch always bounces
222
223	@ Increment hook switch interrupt counter
224	ldr r10, [r9, #BUF_CNT_INT_HSW]
225	add r10, r10, #1
226	str r10, [r9, #BUF_CNT_INT_HSW]
227	@@@@@@@@@@@@@@@@@@@@@@@@
228
229
230	mdm: @Is it a modem interrupt?
231	tst r13, #MODEM_IRQ_MASK @ is modem status bit set?
232	beq irq @ no - check for next interrupt
233
234
235	@@@@@@@@@@@@@@@@@@@@@@@@
236	@ Modem FIQ mode interrupt handler stub
237
238	@ Increment modem interrupt counter
239	ldr r10, [r9, #BUF_CNT_INT_MDM]
240	add r10, r10, #1
241	str r10, [r9, #BUF_CNT_INT_MDM]
242	@@@@@@@@@@@@@@@@@@@@@@@@
243
244
245	irq: @ Place deferred_fiq interrupt request
246	ldr r12, deferred_fiq_ih_base @ set pointer to IRQ handler
247	mov r10, #DEFERRED_FIQ_MASK @ set deferred_fiq bit
248	str r10, [r12, #IRQ_ISR_REG_OFFSET] @ place it in the ISR register
249
250	ldr r12, omap1510_gpio_base @ set pointer back to GPIO bank
251	b restart @ check for next GPIO interrupt
252	@@@@@@@@@@@@@@@@@@@@@@@@@@@
253
254
255	/*
256	* Virtual addresses for IO
257	*/
258	omap_ih1_base:
259	.word OMAP1_IO_ADDRESS(OMAP_IH1_BASE)
260	deferred_fiq_ih_base:
261	.word OMAP1_IO_ADDRESS(DEFERRED_FIQ_IH_BASE)
262	omap1510_gpio_base:
263	.word OMAP1_IO_ADDRESS(OMAP1510_GPIO_BASE)
264	qwerty_fiqin_end:
265
266	/*
267	* Check the size of the FIQ,
268	* it cannot go beyond 0xffff0200, and is copied to 0xffff001c
269	*/
270	.if (qwerty_fiqin_end - qwerty_fiqin_start) > (0x200 - 0x1c)
271	.err
272	.endif