Commit | Line | Data |
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9918cda5 | 1 | /* |
724ce5ee | 2 | * arch/arm/mach-ns9xxx/time-ns9360.c |
9918cda5 | 3 | * |
724ce5ee | 4 | * Copyright (C) 2006,2007 by Digi International Inc. |
9918cda5 UKK |
5 | * All rights reserved. |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License version 2 as published by | |
9 | * the Free Software Foundation. | |
10 | */ | |
11 | #include <linux/jiffies.h> | |
12 | #include <linux/interrupt.h> | |
13 | #include <linux/irq.h> | |
cef5975d UKK |
14 | #include <linux/stringify.h> |
15 | #include <linux/clocksource.h> | |
c0bb87f7 | 16 | #include <linux/clockchips.h> |
cef5975d | 17 | |
a09e64fb RK |
18 | #include <mach/processor-ns9360.h> |
19 | #include <mach/regs-sys-ns9360.h> | |
20 | #include <mach/irqs.h> | |
21 | #include <mach/system.h> | |
9918cda5 UKK |
22 | #include "generic.h" |
23 | ||
c0bb87f7 UKK |
24 | #define TIMER_CLOCKSOURCE 0 |
25 | #define TIMER_CLOCKEVENT 1 | |
26 | static u32 latch; | |
9918cda5 | 27 | |
724ce5ee | 28 | static cycle_t ns9360_clocksource_read(void) |
c0bb87f7 | 29 | { |
361c7ad6 | 30 | return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE)); |
c0bb87f7 UKK |
31 | } |
32 | ||
724ce5ee UKK |
33 | static struct clocksource ns9360_clocksource = { |
34 | .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE), | |
c0bb87f7 | 35 | .rating = 300, |
724ce5ee | 36 | .read = ns9360_clocksource_read, |
c0bb87f7 UKK |
37 | .mask = CLOCKSOURCE_MASK(32), |
38 | .shift = 20, | |
39 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
40 | }; | |
41 | ||
724ce5ee | 42 | static void ns9360_clockevent_setmode(enum clock_event_mode mode, |
c0bb87f7 UKK |
43 | struct clock_event_device *clk) |
44 | { | |
361c7ad6 | 45 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 | 46 | |
724ce5ee | 47 | switch (mode) { |
c0bb87f7 | 48 | case CLOCK_EVT_MODE_PERIODIC: |
361c7ad6 | 49 | __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT)); |
c0bb87f7 UKK |
50 | REGSET(tc, SYS_TCx, REN, EN); |
51 | REGSET(tc, SYS_TCx, INTS, EN); | |
52 | REGSET(tc, SYS_TCx, TEN, EN); | |
53 | break; | |
54 | ||
55 | case CLOCK_EVT_MODE_ONESHOT: | |
56 | REGSET(tc, SYS_TCx, REN, DIS); | |
57 | REGSET(tc, SYS_TCx, INTS, EN); | |
58 | ||
59 | /* fall through */ | |
60 | ||
61 | case CLOCK_EVT_MODE_UNUSED: | |
62 | case CLOCK_EVT_MODE_SHUTDOWN: | |
63 | case CLOCK_EVT_MODE_RESUME: | |
64 | default: | |
65 | REGSET(tc, SYS_TCx, TEN, DIS); | |
66 | break; | |
67 | } | |
68 | ||
361c7ad6 | 69 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 UKK |
70 | } |
71 | ||
724ce5ee | 72 | static int ns9360_clockevent_setnextevent(unsigned long evt, |
c0bb87f7 UKK |
73 | struct clock_event_device *clk) |
74 | { | |
361c7ad6 | 75 | u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 UKK |
76 | |
77 | if (REGGET(tc, SYS_TCx, TEN)) { | |
78 | REGSET(tc, SYS_TCx, TEN, DIS); | |
361c7ad6 | 79 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 UKK |
80 | } |
81 | ||
82 | REGSET(tc, SYS_TCx, TEN, EN); | |
83 | ||
361c7ad6 | 84 | __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT)); |
c0bb87f7 | 85 | |
361c7ad6 | 86 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 UKK |
87 | |
88 | return 0; | |
89 | } | |
90 | ||
724ce5ee UKK |
91 | static struct clock_event_device ns9360_clockevent_device = { |
92 | .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), | |
c0bb87f7 UKK |
93 | .shift = 20, |
94 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, | |
724ce5ee UKK |
95 | .set_mode = ns9360_clockevent_setmode, |
96 | .set_next_event = ns9360_clockevent_setnextevent, | |
c0bb87f7 UKK |
97 | }; |
98 | ||
724ce5ee | 99 | static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id) |
9918cda5 | 100 | { |
724ce5ee | 101 | int timerno = irq - IRQ_NS9360_TIMER0; |
bf62e862 UKK |
102 | u32 tc; |
103 | ||
724ce5ee | 104 | struct clock_event_device *evt = &ns9360_clockevent_device; |
9918cda5 | 105 | |
bf62e862 | 106 | /* clear irq */ |
361c7ad6 | 107 | tc = __raw_readl(SYS_TC(timerno)); |
bf62e862 UKK |
108 | if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) { |
109 | REGSET(tc, SYS_TCx, TEN, DIS); | |
361c7ad6 | 110 | __raw_writel(tc, SYS_TC(timerno)); |
bf62e862 UKK |
111 | } |
112 | REGSET(tc, SYS_TCx, INTC, SET); | |
361c7ad6 | 113 | __raw_writel(tc, SYS_TC(timerno)); |
bf62e862 | 114 | REGSET(tc, SYS_TCx, INTC, UNSET); |
361c7ad6 | 115 | __raw_writel(tc, SYS_TC(timerno)); |
bf62e862 | 116 | |
c0bb87f7 | 117 | evt->event_handler(evt); |
9918cda5 | 118 | |
c0bb87f7 | 119 | return IRQ_HANDLED; |
cef5975d UKK |
120 | } |
121 | ||
724ce5ee UKK |
122 | static struct irqaction ns9360_clockevent_action = { |
123 | .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT), | |
c0bb87f7 | 124 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, |
724ce5ee | 125 | .handler = ns9360_clockevent_handler, |
cef5975d UKK |
126 | }; |
127 | ||
724ce5ee | 128 | static void __init ns9360_timer_init(void) |
9918cda5 UKK |
129 | { |
130 | int tc; | |
131 | ||
361c7ad6 | 132 | tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE)); |
cef5975d UKK |
133 | if (REGGET(tc, SYS_TCx, TEN)) { |
134 | REGSET(tc, SYS_TCx, TEN, DIS); | |
361c7ad6 | 135 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); |
cef5975d UKK |
136 | } |
137 | ||
361c7ad6 | 138 | __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE)); |
cef5975d UKK |
139 | |
140 | REGSET(tc, SYS_TCx, TEN, EN); | |
141 | REGSET(tc, SYS_TCx, TDBG, STOP); | |
142 | REGSET(tc, SYS_TCx, TLCS, CPU); | |
143 | REGSET(tc, SYS_TCx, TM, IEE); | |
144 | REGSET(tc, SYS_TCx, INTS, DIS); | |
145 | REGSET(tc, SYS_TCx, UDS, UP); | |
146 | REGSET(tc, SYS_TCx, TSZ, 32); | |
147 | REGSET(tc, SYS_TCx, REN, EN); | |
148 | ||
361c7ad6 | 149 | __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE)); |
cef5975d | 150 | |
724ce5ee UKK |
151 | ns9360_clocksource.mult = clocksource_hz2mult(ns9360_cpuclock(), |
152 | ns9360_clocksource.shift); | |
cef5975d | 153 | |
724ce5ee | 154 | clocksource_register(&ns9360_clocksource); |
c0bb87f7 | 155 | |
724ce5ee | 156 | latch = SH_DIV(ns9360_cpuclock(), HZ, 0); |
c0bb87f7 | 157 | |
361c7ad6 | 158 | tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 UKK |
159 | REGSET(tc, SYS_TCx, TEN, DIS); |
160 | REGSET(tc, SYS_TCx, TDBG, STOP); | |
161 | REGSET(tc, SYS_TCx, TLCS, CPU); | |
162 | REGSET(tc, SYS_TCx, TM, IEE); | |
163 | REGSET(tc, SYS_TCx, INTS, DIS); | |
164 | REGSET(tc, SYS_TCx, UDS, DOWN); | |
165 | REGSET(tc, SYS_TCx, TSZ, 32); | |
166 | REGSET(tc, SYS_TCx, REN, EN); | |
361c7ad6 | 167 | __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT)); |
c0bb87f7 | 168 | |
724ce5ee UKK |
169 | ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(), |
170 | NSEC_PER_SEC, ns9360_clockevent_device.shift); | |
171 | ns9360_clockevent_device.max_delta_ns = | |
172 | clockevent_delta2ns(-1, &ns9360_clockevent_device); | |
173 | ns9360_clockevent_device.min_delta_ns = | |
174 | clockevent_delta2ns(1, &ns9360_clockevent_device); | |
c0bb87f7 | 175 | |
320ab2b0 | 176 | ns9360_clockevent_device.cpumask = cpumask_of(0); |
724ce5ee | 177 | clockevents_register_device(&ns9360_clockevent_device); |
c0bb87f7 | 178 | |
724ce5ee UKK |
179 | setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT, |
180 | &ns9360_clockevent_action); | |
9918cda5 UKK |
181 | } |
182 | ||
724ce5ee UKK |
183 | struct sys_timer ns9360_timer = { |
184 | .init = ns9360_timer_init, | |
9918cda5 | 185 | }; |