[linux-2.6-block.git] / arch / arm / mach-mx5 / mm.c

/*
 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * The code contained herein is licensed under the GNU General Public
 * License.  You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 *
 * Create static mapping between physical to virtual memory.
 */

#include <linux/mm.h>
#include <linux/init.h>

#include <asm/mach/map.h>

#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/devices-common.h>
#include <mach/iomux-v3.h>

static void imx5_idle(void)
{
	if (!need_resched())
		mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
	local_irq_enable();
}

/*
 * Define the MX50 memory map.
 */
static struct map_desc mx50_io_desc[] __initdata = {
	imx_map_entry(MX50, TZIC, MT_DEVICE),
	imx_map_entry(MX50, SPBA0, MT_DEVICE),
	imx_map_entry(MX50, AIPS1, MT_DEVICE),
	imx_map_entry(MX50, AIPS2, MT_DEVICE),
};

/*
 * Define the MX51 memory map.
 */
static struct map_desc mx51_io_desc[] __initdata = {
	imx_map_entry(MX51, TZIC, MT_DEVICE),
	imx_map_entry(MX51, IRAM, MT_DEVICE),
	imx_map_entry(MX51, AIPS1, MT_DEVICE),
	imx_map_entry(MX51, SPBA0, MT_DEVICE),
	imx_map_entry(MX51, AIPS2, MT_DEVICE),
};

/*
 * Define the MX53 memory map.
 */
static struct map_desc mx53_io_desc[] __initdata = {
	imx_map_entry(MX53, TZIC, MT_DEVICE),
	imx_map_entry(MX53, AIPS1, MT_DEVICE),
	imx_map_entry(MX53, SPBA0, MT_DEVICE),
	imx_map_entry(MX53, AIPS2, MT_DEVICE),
};

/*
 * This function initializes the memory map. It is called during the
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
void __init mx50_map_io(void)
{
	iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
}

void __init mx51_map_io(void)
{
	iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
}

void __init mx53_map_io(void)
{
	iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
}

void __init imx50_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX50);
	mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
}

void __init imx51_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX51);
	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
	pm_idle = imx5_idle;
}

void __init imx53_init_early(void)
{
	mxc_set_cpu_type(MXC_CPU_MX53);
	mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
}

void __init mx50_init_irq(void)
{
	tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
}

void __init mx51_init_irq(void)
{
	tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
}

void __init mx53_init_irq(void)
{
	tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
}

static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
	.ap_2_ap_addr = 642,
	.uart_2_mcu_addr = 817,
	.mcu_2_app_addr = 747,
	.mcu_2_shp_addr = 961,
	.ata_2_mcu_addr = 1473,
	.mcu_2_ata_addr = 1392,
	.app_2_per_addr = 1033,
	.app_2_mcu_addr = 683,
	.shp_2_per_addr = 1251,
	.shp_2_mcu_addr = 892,
};

static struct sdma_platform_data imx51_sdma_pdata __initdata = {
	.fw_name = "sdma-imx51.bin",
	.script_addrs = &imx51_sdma_script,
};

static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
	.ap_2_ap_addr = 642,
	.app_2_mcu_addr = 683,
	.mcu_2_app_addr = 747,
	.uart_2_mcu_addr = 817,
	.shp_2_mcu_addr = 891,
	.mcu_2_shp_addr = 960,
	.uartsh_2_mcu_addr = 1032,
	.spdif_2_mcu_addr = 1100,
	.mcu_2_spdif_addr = 1134,
	.firi_2_mcu_addr = 1193,
	.mcu_2_firi_addr = 1290,
};

static struct sdma_platform_data imx53_sdma_pdata __initdata = {
	.fw_name = "sdma-imx53.bin",
	.script_addrs = &imx53_sdma_script,
};

void __init imx50_soc_init(void)
{
	/* i.mx50 has the i.mx31 type gpio */
	mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
	mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
	mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
	mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
	mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
	mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
}

void __init imx51_soc_init(void)
{
	/* i.mx51 has the i.mx31 type gpio */
	mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
	mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
	mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
	mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);

	/* i.mx51 has the i.mx35 type sdma */
	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
}

void __init imx53_soc_init(void)
{
	/* i.mx53 has the i.mx31 type gpio */
	mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
	mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
	mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
	mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
	mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
	mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
	mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);

	/* i.mx53 has the i.mx35 type sdma */
	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
}
Commit	Line	Data
a329b48c	1	/*
b66ff7a2	2	* Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
a329b48c AK	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*
	11	* Create static mapping between physical to virtual memory.
	12	*/
	13
	14	#include <linux/mm.h>
	15	#include <linux/init.h>
	16
	17	#include <asm/mach/map.h>
	18
	19	#include <mach/hardware.h>
	20	#include <mach/common.h>
36223604	21	#include <mach/devices-common.h>
a329b48c AK	22	#include <mach/iomux-v3.h>
a329b48c AK	23
41e7daf2 SG	24	static void imx5_idle(void)
41e7daf2 SG	25	{
8c6d8319 SG	26	if (!need_resched())
	27	mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
	28	local_irq_enable();
41e7daf2 SG	29	}
41e7daf2 SG	30
abca2e10 JL	31	/*
	32	* Define the MX50 memory map.
	33	*/
	34	static struct map_desc mx50_io_desc[] __initdata = {
	35	imx_map_entry(MX50, TZIC, MT_DEVICE),
	36	imx_map_entry(MX50, SPBA0, MT_DEVICE),
	37	imx_map_entry(MX50, AIPS1, MT_DEVICE),
	38	imx_map_entry(MX50, AIPS2, MT_DEVICE),
	39	};
	40
a329b48c AK	41	/*
	42	* Define the MX51 memory map.
	43	*/
08ff97b5	44	static struct map_desc mx51_io_desc[] __initdata = {
4c542390	45	imx_map_entry(MX51, TZIC, MT_DEVICE),
08ff97b5	46	imx_map_entry(MX51, IRAM, MT_DEVICE),
08ff97b5 UKK	47	imx_map_entry(MX51, AIPS1, MT_DEVICE),
	48	imx_map_entry(MX51, SPBA0, MT_DEVICE),
	49	imx_map_entry(MX51, AIPS2, MT_DEVICE),
a329b48c AK	50	};
a329b48c AK	51
b66ff7a2 DN	52	/*
	53	* Define the MX53 memory map.
	54	*/
	55	static struct map_desc mx53_io_desc[] __initdata = {
4c542390	56	imx_map_entry(MX53, TZIC, MT_DEVICE),
b66ff7a2 DN	57	imx_map_entry(MX53, AIPS1, MT_DEVICE),
	58	imx_map_entry(MX53, SPBA0, MT_DEVICE),
	59	imx_map_entry(MX53, AIPS2, MT_DEVICE),
	60	};
	61
a329b48c AK	62	/*
	63	* This function initializes the memory map. It is called during the
	64	* system startup to create static physical to virtual memory mappings
	65	* for the IO modules.
	66	*/
abca2e10 JL	67	void __init mx50_map_io(void)
	68	{
	69	iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
	70	}
	71
a329b48c	72	void __init mx51_map_io(void)
ab130421 UKK	73	{
	74	iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
	75	}
	76
abca2e10 JL	77	void __init mx53_map_io(void)
	78	{
	79	iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
	80	}
	81
	82	void __init imx50_init_early(void)
	83	{
	84	mxc_set_cpu_type(MXC_CPU_MX50);
	85	mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
	86	mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
	87	}
	88
ab130421	89	void __init imx51_init_early(void)
a329b48c	90	{
a329b48c AK	91	mxc_set_cpu_type(MXC_CPU_MX51);
a329b48c AK	92	mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
8c2efec3	93	mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
8c6d8319	94	pm_idle = imx5_idle;
a329b48c AK	95	}
a329b48c AK	96
ab130421	97	void __init imx53_init_early(void)
b66ff7a2 DN	98	{
	99	mxc_set_cpu_type(MXC_CPU_MX53);
	100	mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
78c73591	101	mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG1_BASE_ADDR));
b66ff7a2 DN	102	}
b66ff7a2 DN	103
abca2e10	104	void __init mx50_init_irq(void)
a329b48c	105	{
abca2e10 JL	106	tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
abca2e10 JL	107	}
3d1bc862	108
a329b48c AK	109	void __init mx51_init_irq(void)
a329b48c AK	110	{
4c542390	111	tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
a329b48c	112	}
c0abefd3	113
c0abefd3 DN	114	void __init mx53_init_irq(void)
c0abefd3 DN	115	{
4c542390	116	tzic_init_irq(MX53_IO_ADDRESS(MX53_TZIC_BASE_ADDR));
b78d8e59 SG	117	}
b78d8e59 SG	118
36223604 SG	119	static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
	120	.ap_2_ap_addr = 642,
	121	.uart_2_mcu_addr = 817,
	122	.mcu_2_app_addr = 747,
	123	.mcu_2_shp_addr = 961,
	124	.ata_2_mcu_addr = 1473,
	125	.mcu_2_ata_addr = 1392,
	126	.app_2_per_addr = 1033,
	127	.app_2_mcu_addr = 683,
	128	.shp_2_per_addr = 1251,
	129	.shp_2_mcu_addr = 892,
	130	};
	131
	132	static struct sdma_platform_data imx51_sdma_pdata __initdata = {
2e534b21	133	.fw_name = "sdma-imx51.bin",
36223604 SG	134	.script_addrs = &imx51_sdma_script,
	135	};
	136
	137	static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
	138	.ap_2_ap_addr = 642,
	139	.app_2_mcu_addr = 683,
	140	.mcu_2_app_addr = 747,
	141	.uart_2_mcu_addr = 817,
	142	.shp_2_mcu_addr = 891,
	143	.mcu_2_shp_addr = 960,
	144	.uartsh_2_mcu_addr = 1032,
	145	.spdif_2_mcu_addr = 1100,
	146	.mcu_2_spdif_addr = 1134,
	147	.firi_2_mcu_addr = 1193,
	148	.mcu_2_firi_addr = 1290,
	149	};
	150
	151	static struct sdma_platform_data imx53_sdma_pdata __initdata = {
2e534b21	152	.fw_name = "sdma-imx53.bin",
36223604 SG	153	.script_addrs = &imx53_sdma_script,
	154	};
	155
abca2e10 JL	156	void __init imx50_soc_init(void)
	157	{
	158	/* i.mx50 has the i.mx31 type gpio */
	159	mxc_register_gpio("imx31-gpio", 0, MX50_GPIO1_BASE_ADDR, SZ_16K, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH);
	160	mxc_register_gpio("imx31-gpio", 1, MX50_GPIO2_BASE_ADDR, SZ_16K, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH);
	161	mxc_register_gpio("imx31-gpio", 2, MX50_GPIO3_BASE_ADDR, SZ_16K, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH);
	162	mxc_register_gpio("imx31-gpio", 3, MX50_GPIO4_BASE_ADDR, SZ_16K, MX50_INT_GPIO4_LOW, MX50_INT_GPIO4_HIGH);
	163	mxc_register_gpio("imx31-gpio", 4, MX50_GPIO5_BASE_ADDR, SZ_16K, MX50_INT_GPIO5_LOW, MX50_INT_GPIO5_HIGH);
	164	mxc_register_gpio("imx31-gpio", 5, MX50_GPIO6_BASE_ADDR, SZ_16K, MX50_INT_GPIO6_LOW, MX50_INT_GPIO6_HIGH);
	165	}
	166
b78d8e59 SG	167	void __init imx51_soc_init(void)
b78d8e59 SG	168	{
e7fc6ae7	169	/* i.mx51 has the i.mx31 type gpio */
1a195277 UKK	170	mxc_register_gpio("imx31-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
	171	mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
	172	mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
	173	mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
36223604	174
62550cd7 SG	175	/* i.mx51 has the i.mx35 type sdma */
62550cd7 SG	176	imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
b78d8e59 SG	177	}
	178
	179	void __init imx53_soc_init(void)
	180	{
e7fc6ae7 SG	181	/* i.mx53 has the i.mx31 type gpio */
	182	mxc_register_gpio("imx31-gpio", 0, MX53_GPIO1_BASE_ADDR, SZ_16K, MX53_INT_GPIO1_LOW, MX53_INT_GPIO1_HIGH);
	183	mxc_register_gpio("imx31-gpio", 1, MX53_GPIO2_BASE_ADDR, SZ_16K, MX53_INT_GPIO2_LOW, MX53_INT_GPIO2_HIGH);
	184	mxc_register_gpio("imx31-gpio", 2, MX53_GPIO3_BASE_ADDR, SZ_16K, MX53_INT_GPIO3_LOW, MX53_INT_GPIO3_HIGH);
	185	mxc_register_gpio("imx31-gpio", 3, MX53_GPIO4_BASE_ADDR, SZ_16K, MX53_INT_GPIO4_LOW, MX53_INT_GPIO4_HIGH);
	186	mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
	187	mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
	188	mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
36223604	189
62550cd7 SG	190	/* i.mx53 has the i.mx35 type sdma */
62550cd7 SG	191	imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
c0abefd3	192	}