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a329b48c AK |
1 | /* |
2 | * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com> | |
4 | * | |
5 | * The code contained herein is licensed under the GNU General Public | |
6 | * License. You may obtain a copy of the GNU General Public License | |
7 | * Version 2 or later at the following locations: | |
8 | * | |
9 | * http://www.opensource.org/licenses/gpl-license.html | |
10 | * http://www.gnu.org/copyleft/gpl.html | |
11 | */ | |
12 | ||
13 | #include <linux/mm.h> | |
14 | #include <linux/delay.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/io.h> | |
17 | ||
18 | #include <asm/clkdev.h> | |
17807f91 | 19 | #include <asm/div64.h> |
a329b48c AK |
20 | |
21 | #include <mach/hardware.h> | |
22 | #include <mach/common.h> | |
23 | #include <mach/clock.h> | |
24 | ||
25 | #include "crm_regs.h" | |
26 | ||
27 | /* External clock values passed-in by the board code */ | |
28 | static unsigned long external_high_reference, external_low_reference; | |
29 | static unsigned long oscillator_reference, ckih2_reference; | |
30 | ||
31 | static struct clk osc_clk; | |
32 | static struct clk pll1_main_clk; | |
33 | static struct clk pll1_sw_clk; | |
34 | static struct clk pll2_sw_clk; | |
35 | static struct clk pll3_sw_clk; | |
36 | static struct clk lp_apm_clk; | |
37 | static struct clk periph_apm_clk; | |
38 | static struct clk ahb_clk; | |
39 | static struct clk ipg_clk; | |
c79504e7 | 40 | static struct clk usboh3_clk; |
a329b48c AK |
41 | |
42 | #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ | |
43 | ||
79901478 | 44 | static void _clk_ccgr_setclk(struct clk *clk, unsigned mode) |
a329b48c | 45 | { |
79901478 UKK |
46 | u32 reg = __raw_readl(clk->enable_reg); |
47 | ||
48 | reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); | |
49 | reg |= mode << clk->enable_shift; | |
a329b48c | 50 | |
a329b48c | 51 | __raw_writel(reg, clk->enable_reg); |
79901478 | 52 | } |
a329b48c | 53 | |
79901478 UKK |
54 | static int _clk_ccgr_enable(struct clk *clk) |
55 | { | |
56 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON); | |
a329b48c AK |
57 | return 0; |
58 | } | |
59 | ||
60 | static void _clk_ccgr_disable(struct clk *clk) | |
61 | { | |
79901478 UKK |
62 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF); |
63 | } | |
a329b48c | 64 | |
79901478 UKK |
65 | static int _clk_ccgr_enable_inrun(struct clk *clk) |
66 | { | |
67 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); | |
68 | return 0; | |
a329b48c AK |
69 | } |
70 | ||
71 | static void _clk_ccgr_disable_inwait(struct clk *clk) | |
72 | { | |
79901478 | 73 | _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE); |
a329b48c AK |
74 | } |
75 | ||
76 | /* | |
77 | * For the 4-to-1 muxed input clock | |
78 | */ | |
79 | static inline u32 _get_mux(struct clk *parent, struct clk *m0, | |
80 | struct clk *m1, struct clk *m2, struct clk *m3) | |
81 | { | |
82 | if (parent == m0) | |
83 | return 0; | |
84 | else if (parent == m1) | |
85 | return 1; | |
86 | else if (parent == m2) | |
87 | return 2; | |
88 | else if (parent == m3) | |
89 | return 3; | |
90 | else | |
91 | BUG(); | |
92 | ||
93 | return -EINVAL; | |
94 | } | |
95 | ||
96 | static inline void __iomem *_get_pll_base(struct clk *pll) | |
97 | { | |
98 | if (pll == &pll1_main_clk) | |
99 | return MX51_DPLL1_BASE; | |
100 | else if (pll == &pll2_sw_clk) | |
101 | return MX51_DPLL2_BASE; | |
102 | else if (pll == &pll3_sw_clk) | |
103 | return MX51_DPLL3_BASE; | |
104 | else | |
105 | BUG(); | |
106 | ||
107 | return NULL; | |
108 | } | |
109 | ||
110 | static unsigned long clk_pll_get_rate(struct clk *clk) | |
111 | { | |
112 | long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; | |
113 | unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl; | |
114 | void __iomem *pllbase; | |
115 | s64 temp; | |
116 | unsigned long parent_rate; | |
117 | ||
118 | parent_rate = clk_get_rate(clk->parent); | |
119 | ||
120 | pllbase = _get_pll_base(clk); | |
121 | ||
122 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); | |
123 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; | |
124 | dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN; | |
125 | ||
126 | if (pll_hfsm == 0) { | |
127 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP); | |
128 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD); | |
129 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN); | |
130 | } else { | |
131 | dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP); | |
132 | dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD); | |
133 | dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN); | |
134 | } | |
135 | pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK; | |
136 | mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET; | |
137 | mfi = (mfi <= 5) ? 5 : mfi; | |
138 | mfd = dp_mfd & MXC_PLL_DP_MFD_MASK; | |
139 | mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK; | |
140 | /* Sign extend to 32-bits */ | |
141 | if (mfn >= 0x04000000) { | |
142 | mfn |= 0xFC000000; | |
143 | mfn_abs = -mfn; | |
144 | } | |
145 | ||
146 | ref_clk = 2 * parent_rate; | |
147 | if (dbl != 0) | |
148 | ref_clk *= 2; | |
149 | ||
150 | ref_clk /= (pdf + 1); | |
151 | temp = (u64) ref_clk * mfn_abs; | |
152 | do_div(temp, mfd + 1); | |
153 | if (mfn < 0) | |
154 | temp = -temp; | |
155 | temp = (ref_clk * mfi) + temp; | |
156 | ||
157 | return temp; | |
158 | } | |
159 | ||
160 | static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) | |
161 | { | |
162 | u32 reg; | |
163 | void __iomem *pllbase; | |
164 | ||
165 | long mfi, pdf, mfn, mfd = 999999; | |
166 | s64 temp64; | |
167 | unsigned long quad_parent_rate; | |
168 | unsigned long pll_hfsm, dp_ctl; | |
169 | unsigned long parent_rate; | |
170 | ||
171 | parent_rate = clk_get_rate(clk->parent); | |
172 | ||
173 | pllbase = _get_pll_base(clk); | |
174 | ||
175 | quad_parent_rate = 4 * parent_rate; | |
176 | pdf = mfi = -1; | |
177 | while (++pdf < 16 && mfi < 5) | |
178 | mfi = rate * (pdf+1) / quad_parent_rate; | |
179 | if (mfi > 15) | |
180 | return -EINVAL; | |
181 | pdf--; | |
182 | ||
183 | temp64 = rate * (pdf+1) - quad_parent_rate * mfi; | |
184 | do_div(temp64, quad_parent_rate/1000000); | |
185 | mfn = (long)temp64; | |
186 | ||
187 | dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL); | |
188 | /* use dpdck0_2 */ | |
189 | __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL); | |
190 | pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM; | |
191 | if (pll_hfsm == 0) { | |
192 | reg = mfi << 4 | pdf; | |
193 | __raw_writel(reg, pllbase + MXC_PLL_DP_OP); | |
194 | __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD); | |
195 | __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN); | |
196 | } else { | |
197 | reg = mfi << 4 | pdf; | |
198 | __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP); | |
199 | __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD); | |
200 | __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN); | |
201 | } | |
202 | ||
203 | return 0; | |
204 | } | |
205 | ||
206 | static int _clk_pll_enable(struct clk *clk) | |
207 | { | |
208 | u32 reg; | |
209 | void __iomem *pllbase; | |
210 | int i = 0; | |
211 | ||
212 | pllbase = _get_pll_base(clk); | |
213 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; | |
214 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); | |
215 | ||
216 | /* Wait for lock */ | |
217 | do { | |
218 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); | |
219 | if (reg & MXC_PLL_DP_CTL_LRF) | |
220 | break; | |
221 | ||
222 | udelay(1); | |
223 | } while (++i < MAX_DPLL_WAIT_TRIES); | |
224 | ||
225 | if (i == MAX_DPLL_WAIT_TRIES) { | |
226 | pr_err("MX5: pll locking failed\n"); | |
227 | return -EINVAL; | |
228 | } | |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | static void _clk_pll_disable(struct clk *clk) | |
234 | { | |
235 | u32 reg; | |
236 | void __iomem *pllbase; | |
237 | ||
238 | pllbase = _get_pll_base(clk); | |
239 | reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN; | |
240 | __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); | |
241 | } | |
242 | ||
243 | static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) | |
244 | { | |
245 | u32 reg, step; | |
246 | ||
247 | reg = __raw_readl(MXC_CCM_CCSR); | |
248 | ||
249 | /* When switching from pll_main_clk to a bypass clock, first select a | |
250 | * multiplexed clock in 'step_sel', then shift the glitchless mux | |
251 | * 'pll1_sw_clk_sel'. | |
252 | * | |
253 | * When switching back, do it in reverse order | |
254 | */ | |
255 | if (parent == &pll1_main_clk) { | |
256 | /* Switch to pll1_main_clk */ | |
257 | reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL; | |
258 | __raw_writel(reg, MXC_CCM_CCSR); | |
259 | /* step_clk mux switched to lp_apm, to save power. */ | |
260 | reg = __raw_readl(MXC_CCM_CCSR); | |
261 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; | |
262 | reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM << | |
263 | MXC_CCM_CCSR_STEP_SEL_OFFSET); | |
264 | } else { | |
265 | if (parent == &lp_apm_clk) { | |
266 | step = MXC_CCM_CCSR_STEP_SEL_LP_APM; | |
267 | } else if (parent == &pll2_sw_clk) { | |
268 | step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED; | |
269 | } else if (parent == &pll3_sw_clk) { | |
270 | step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED; | |
271 | } else | |
272 | return -EINVAL; | |
273 | ||
274 | reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK; | |
275 | reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET); | |
276 | ||
277 | __raw_writel(reg, MXC_CCM_CCSR); | |
278 | /* Switch to step_clk */ | |
279 | reg = __raw_readl(MXC_CCM_CCSR); | |
280 | reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL; | |
281 | } | |
282 | __raw_writel(reg, MXC_CCM_CCSR); | |
283 | return 0; | |
284 | } | |
285 | ||
286 | static unsigned long clk_pll1_sw_get_rate(struct clk *clk) | |
287 | { | |
288 | u32 reg, div; | |
289 | unsigned long parent_rate; | |
290 | ||
291 | parent_rate = clk_get_rate(clk->parent); | |
292 | ||
293 | reg = __raw_readl(MXC_CCM_CCSR); | |
294 | ||
295 | if (clk->parent == &pll2_sw_clk) { | |
296 | div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >> | |
297 | MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1; | |
298 | } else if (clk->parent == &pll3_sw_clk) { | |
299 | div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >> | |
300 | MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1; | |
301 | } else | |
302 | div = 1; | |
303 | return parent_rate / div; | |
304 | } | |
305 | ||
306 | static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent) | |
307 | { | |
308 | u32 reg; | |
309 | ||
310 | reg = __raw_readl(MXC_CCM_CCSR); | |
311 | ||
312 | if (parent == &pll2_sw_clk) | |
313 | reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL; | |
314 | else | |
315 | reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL; | |
316 | ||
317 | __raw_writel(reg, MXC_CCM_CCSR); | |
318 | return 0; | |
319 | } | |
320 | ||
321 | static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) | |
322 | { | |
323 | u32 reg; | |
324 | ||
325 | if (parent == &osc_clk) | |
326 | reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL; | |
327 | else | |
328 | return -EINVAL; | |
329 | ||
330 | __raw_writel(reg, MXC_CCM_CCSR); | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
335 | static unsigned long clk_arm_get_rate(struct clk *clk) | |
336 | { | |
337 | u32 cacrr, div; | |
338 | unsigned long parent_rate; | |
339 | ||
340 | parent_rate = clk_get_rate(clk->parent); | |
341 | cacrr = __raw_readl(MXC_CCM_CACRR); | |
342 | div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1; | |
343 | ||
344 | return parent_rate / div; | |
345 | } | |
346 | ||
347 | static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent) | |
348 | { | |
349 | u32 reg, mux; | |
350 | int i = 0; | |
351 | ||
352 | mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL); | |
353 | ||
354 | reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK; | |
355 | reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET; | |
356 | __raw_writel(reg, MXC_CCM_CBCMR); | |
357 | ||
358 | /* Wait for lock */ | |
359 | do { | |
360 | reg = __raw_readl(MXC_CCM_CDHIPR); | |
361 | if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY)) | |
362 | break; | |
363 | ||
364 | udelay(1); | |
365 | } while (++i < MAX_DPLL_WAIT_TRIES); | |
366 | ||
367 | if (i == MAX_DPLL_WAIT_TRIES) { | |
368 | pr_err("MX5: Set parent for periph_apm clock failed\n"); | |
369 | return -EINVAL; | |
370 | } | |
371 | ||
372 | return 0; | |
373 | } | |
374 | ||
375 | static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) | |
376 | { | |
377 | u32 reg; | |
378 | ||
379 | reg = __raw_readl(MXC_CCM_CBCDR); | |
380 | ||
381 | if (parent == &pll2_sw_clk) | |
382 | reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; | |
383 | else if (parent == &periph_apm_clk) | |
384 | reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL; | |
385 | else | |
386 | return -EINVAL; | |
387 | ||
388 | __raw_writel(reg, MXC_CCM_CBCDR); | |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
393 | static struct clk main_bus_clk = { | |
394 | .parent = &pll2_sw_clk, | |
395 | .set_parent = _clk_main_bus_set_parent, | |
396 | }; | |
397 | ||
398 | static unsigned long clk_ahb_get_rate(struct clk *clk) | |
399 | { | |
400 | u32 reg, div; | |
401 | unsigned long parent_rate; | |
402 | ||
403 | parent_rate = clk_get_rate(clk->parent); | |
404 | ||
405 | reg = __raw_readl(MXC_CCM_CBCDR); | |
406 | div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> | |
407 | MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; | |
408 | return parent_rate / div; | |
409 | } | |
410 | ||
411 | ||
412 | static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) | |
413 | { | |
414 | u32 reg, div; | |
415 | unsigned long parent_rate; | |
416 | int i = 0; | |
417 | ||
418 | parent_rate = clk_get_rate(clk->parent); | |
419 | ||
420 | div = parent_rate / rate; | |
421 | if (div > 8 || div < 1 || ((parent_rate / div) != rate)) | |
422 | return -EINVAL; | |
423 | ||
424 | reg = __raw_readl(MXC_CCM_CBCDR); | |
425 | reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; | |
426 | reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; | |
427 | __raw_writel(reg, MXC_CCM_CBCDR); | |
428 | ||
429 | /* Wait for lock */ | |
430 | do { | |
431 | reg = __raw_readl(MXC_CCM_CDHIPR); | |
432 | if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY)) | |
433 | break; | |
434 | ||
435 | udelay(1); | |
436 | } while (++i < MAX_DPLL_WAIT_TRIES); | |
437 | ||
438 | if (i == MAX_DPLL_WAIT_TRIES) { | |
439 | pr_err("MX5: clk_ahb_set_rate failed\n"); | |
440 | return -EINVAL; | |
441 | } | |
442 | ||
443 | return 0; | |
444 | } | |
445 | ||
446 | static unsigned long _clk_ahb_round_rate(struct clk *clk, | |
447 | unsigned long rate) | |
448 | { | |
449 | u32 div; | |
450 | unsigned long parent_rate; | |
451 | ||
452 | parent_rate = clk_get_rate(clk->parent); | |
453 | ||
454 | div = parent_rate / rate; | |
455 | if (div > 8) | |
456 | div = 8; | |
457 | else if (div == 0) | |
458 | div++; | |
459 | return parent_rate / div; | |
460 | } | |
461 | ||
462 | ||
463 | static int _clk_max_enable(struct clk *clk) | |
464 | { | |
465 | u32 reg; | |
466 | ||
467 | _clk_ccgr_enable(clk); | |
468 | ||
469 | /* Handshake with MAX when LPM is entered. */ | |
470 | reg = __raw_readl(MXC_CCM_CLPCR); | |
471 | reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; | |
472 | __raw_writel(reg, MXC_CCM_CLPCR); | |
473 | ||
474 | return 0; | |
475 | } | |
476 | ||
477 | static void _clk_max_disable(struct clk *clk) | |
478 | { | |
479 | u32 reg; | |
480 | ||
481 | _clk_ccgr_disable_inwait(clk); | |
482 | ||
483 | /* No Handshake with MAX when LPM is entered as its disabled. */ | |
484 | reg = __raw_readl(MXC_CCM_CLPCR); | |
485 | reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; | |
486 | __raw_writel(reg, MXC_CCM_CLPCR); | |
487 | } | |
488 | ||
489 | static unsigned long clk_ipg_get_rate(struct clk *clk) | |
490 | { | |
491 | u32 reg, div; | |
492 | unsigned long parent_rate; | |
493 | ||
494 | parent_rate = clk_get_rate(clk->parent); | |
495 | ||
496 | reg = __raw_readl(MXC_CCM_CBCDR); | |
497 | div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >> | |
498 | MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1; | |
499 | ||
500 | return parent_rate / div; | |
501 | } | |
502 | ||
503 | static unsigned long clk_ipg_per_get_rate(struct clk *clk) | |
504 | { | |
505 | u32 reg, prediv1, prediv2, podf; | |
506 | unsigned long parent_rate; | |
507 | ||
508 | parent_rate = clk_get_rate(clk->parent); | |
509 | ||
510 | if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) { | |
511 | /* the main_bus_clk is the one before the DVFS engine */ | |
512 | reg = __raw_readl(MXC_CCM_CBCDR); | |
513 | prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >> | |
514 | MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1; | |
515 | prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >> | |
516 | MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1; | |
517 | podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >> | |
518 | MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1; | |
519 | return parent_rate / (prediv1 * prediv2 * podf); | |
520 | } else if (clk->parent == &ipg_clk) | |
521 | return parent_rate; | |
522 | else | |
523 | BUG(); | |
524 | } | |
525 | ||
526 | static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent) | |
527 | { | |
528 | u32 reg; | |
529 | ||
530 | reg = __raw_readl(MXC_CCM_CBCMR); | |
531 | ||
532 | reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; | |
533 | reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; | |
534 | ||
535 | if (parent == &ipg_clk) | |
536 | reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL; | |
537 | else if (parent == &lp_apm_clk) | |
538 | reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL; | |
539 | else if (parent != &main_bus_clk) | |
540 | return -EINVAL; | |
541 | ||
542 | __raw_writel(reg, MXC_CCM_CBCMR); | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
547 | static unsigned long clk_uart_get_rate(struct clk *clk) | |
548 | { | |
549 | u32 reg, prediv, podf; | |
550 | unsigned long parent_rate; | |
551 | ||
552 | parent_rate = clk_get_rate(clk->parent); | |
553 | ||
554 | reg = __raw_readl(MXC_CCM_CSCDR1); | |
555 | prediv = ((reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >> | |
556 | MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) + 1; | |
557 | podf = ((reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >> | |
558 | MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1; | |
559 | ||
560 | return parent_rate / (prediv * podf); | |
561 | } | |
562 | ||
563 | static int _clk_uart_set_parent(struct clk *clk, struct clk *parent) | |
564 | { | |
565 | u32 reg, mux; | |
566 | ||
567 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, | |
568 | &lp_apm_clk); | |
569 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK; | |
570 | reg |= mux << MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET; | |
571 | __raw_writel(reg, MXC_CCM_CSCMR1); | |
572 | ||
573 | return 0; | |
574 | } | |
575 | ||
c79504e7 DN |
576 | static unsigned long clk_usboh3_get_rate(struct clk *clk) |
577 | { | |
578 | u32 reg, prediv, podf; | |
579 | unsigned long parent_rate; | |
580 | ||
581 | parent_rate = clk_get_rate(clk->parent); | |
582 | ||
583 | reg = __raw_readl(MXC_CCM_CSCDR1); | |
584 | prediv = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK) >> | |
585 | MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) + 1; | |
586 | podf = ((reg & MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK) >> | |
587 | MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) + 1; | |
588 | ||
589 | return parent_rate / (prediv * podf); | |
590 | } | |
591 | ||
592 | static int _clk_usboh3_set_parent(struct clk *clk, struct clk *parent) | |
593 | { | |
594 | u32 reg, mux; | |
595 | ||
596 | mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, | |
597 | &lp_apm_clk); | |
598 | reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK; | |
599 | reg |= mux << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET; | |
600 | __raw_writel(reg, MXC_CCM_CSCMR1); | |
601 | ||
602 | return 0; | |
603 | } | |
604 | ||
a329b48c AK |
605 | static unsigned long get_high_reference_clock_rate(struct clk *clk) |
606 | { | |
607 | return external_high_reference; | |
608 | } | |
609 | ||
610 | static unsigned long get_low_reference_clock_rate(struct clk *clk) | |
611 | { | |
612 | return external_low_reference; | |
613 | } | |
614 | ||
615 | static unsigned long get_oscillator_reference_clock_rate(struct clk *clk) | |
616 | { | |
617 | return oscillator_reference; | |
618 | } | |
619 | ||
620 | static unsigned long get_ckih2_reference_clock_rate(struct clk *clk) | |
621 | { | |
622 | return ckih2_reference; | |
623 | } | |
624 | ||
625 | /* External high frequency clock */ | |
626 | static struct clk ckih_clk = { | |
627 | .get_rate = get_high_reference_clock_rate, | |
628 | }; | |
629 | ||
630 | static struct clk ckih2_clk = { | |
631 | .get_rate = get_ckih2_reference_clock_rate, | |
632 | }; | |
633 | ||
634 | static struct clk osc_clk = { | |
635 | .get_rate = get_oscillator_reference_clock_rate, | |
636 | }; | |
637 | ||
638 | /* External low frequency (32kHz) clock */ | |
639 | static struct clk ckil_clk = { | |
640 | .get_rate = get_low_reference_clock_rate, | |
641 | }; | |
642 | ||
643 | static struct clk pll1_main_clk = { | |
644 | .parent = &osc_clk, | |
645 | .get_rate = clk_pll_get_rate, | |
646 | .enable = _clk_pll_enable, | |
647 | .disable = _clk_pll_disable, | |
648 | }; | |
649 | ||
650 | /* Clock tree block diagram (WIP): | |
651 | * CCM: Clock Controller Module | |
652 | * | |
653 | * PLL output -> | | |
654 | * | CCM Switcher -> CCM_CLK_ROOT_GEN -> | |
655 | * PLL bypass -> | | |
656 | * | |
657 | */ | |
658 | ||
659 | /* PLL1 SW supplies to ARM core */ | |
660 | static struct clk pll1_sw_clk = { | |
661 | .parent = &pll1_main_clk, | |
662 | .set_parent = _clk_pll1_sw_set_parent, | |
663 | .get_rate = clk_pll1_sw_get_rate, | |
664 | }; | |
665 | ||
666 | /* PLL2 SW supplies to AXI/AHB/IP buses */ | |
667 | static struct clk pll2_sw_clk = { | |
668 | .parent = &osc_clk, | |
669 | .get_rate = clk_pll_get_rate, | |
670 | .set_rate = _clk_pll_set_rate, | |
671 | .set_parent = _clk_pll2_sw_set_parent, | |
672 | .enable = _clk_pll_enable, | |
673 | .disable = _clk_pll_disable, | |
674 | }; | |
675 | ||
676 | /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */ | |
677 | static struct clk pll3_sw_clk = { | |
678 | .parent = &osc_clk, | |
679 | .set_rate = _clk_pll_set_rate, | |
680 | .get_rate = clk_pll_get_rate, | |
681 | .enable = _clk_pll_enable, | |
682 | .disable = _clk_pll_disable, | |
683 | }; | |
684 | ||
685 | /* Low-power Audio Playback Mode clock */ | |
686 | static struct clk lp_apm_clk = { | |
687 | .parent = &osc_clk, | |
688 | .set_parent = _clk_lp_apm_set_parent, | |
689 | }; | |
690 | ||
691 | static struct clk periph_apm_clk = { | |
692 | .parent = &pll1_sw_clk, | |
693 | .set_parent = _clk_periph_apm_set_parent, | |
694 | }; | |
695 | ||
696 | static struct clk cpu_clk = { | |
697 | .parent = &pll1_sw_clk, | |
698 | .get_rate = clk_arm_get_rate, | |
699 | }; | |
700 | ||
701 | static struct clk ahb_clk = { | |
702 | .parent = &main_bus_clk, | |
703 | .get_rate = clk_ahb_get_rate, | |
704 | .set_rate = _clk_ahb_set_rate, | |
705 | .round_rate = _clk_ahb_round_rate, | |
706 | }; | |
707 | ||
708 | /* Main IP interface clock for access to registers */ | |
709 | static struct clk ipg_clk = { | |
710 | .parent = &ahb_clk, | |
711 | .get_rate = clk_ipg_get_rate, | |
712 | }; | |
713 | ||
714 | static struct clk ipg_perclk = { | |
715 | .parent = &lp_apm_clk, | |
716 | .get_rate = clk_ipg_per_get_rate, | |
717 | .set_parent = _clk_ipg_per_set_parent, | |
718 | }; | |
719 | ||
720 | static struct clk uart_root_clk = { | |
721 | .parent = &pll2_sw_clk, | |
722 | .get_rate = clk_uart_get_rate, | |
723 | .set_parent = _clk_uart_set_parent, | |
724 | }; | |
725 | ||
c79504e7 DN |
726 | static struct clk usboh3_clk = { |
727 | .parent = &pll2_sw_clk, | |
728 | .get_rate = clk_usboh3_get_rate, | |
729 | .set_parent = _clk_usboh3_set_parent, | |
730 | }; | |
731 | ||
a329b48c AK |
732 | static struct clk ahb_max_clk = { |
733 | .parent = &ahb_clk, | |
734 | .enable_reg = MXC_CCM_CCGR0, | |
735 | .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET, | |
736 | .enable = _clk_max_enable, | |
737 | .disable = _clk_max_disable, | |
738 | }; | |
739 | ||
740 | static struct clk aips_tz1_clk = { | |
741 | .parent = &ahb_clk, | |
742 | .secondary = &ahb_max_clk, | |
743 | .enable_reg = MXC_CCM_CCGR0, | |
744 | .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, | |
745 | .enable = _clk_ccgr_enable, | |
746 | .disable = _clk_ccgr_disable_inwait, | |
747 | }; | |
748 | ||
749 | static struct clk aips_tz2_clk = { | |
750 | .parent = &ahb_clk, | |
751 | .secondary = &ahb_max_clk, | |
752 | .enable_reg = MXC_CCM_CCGR0, | |
753 | .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, | |
754 | .enable = _clk_ccgr_enable, | |
755 | .disable = _clk_ccgr_disable_inwait, | |
756 | }; | |
757 | ||
758 | static struct clk gpt_32k_clk = { | |
759 | .id = 0, | |
760 | .parent = &ckil_clk, | |
761 | }; | |
762 | ||
a7ebd931 JW |
763 | static struct clk kpp_clk = { |
764 | .id = 0, | |
765 | }; | |
766 | ||
74d99f39 UKK |
767 | #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \ |
768 | static struct clk name = { \ | |
769 | .id = i, \ | |
770 | .enable_reg = er, \ | |
771 | .enable_shift = es, \ | |
772 | .get_rate = gr, \ | |
773 | .set_rate = sr, \ | |
774 | .enable = e, \ | |
775 | .disable = d, \ | |
776 | .parent = p, \ | |
777 | .secondary = s, \ | |
a329b48c AK |
778 | } |
779 | ||
74d99f39 UKK |
780 | #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \ |
781 | DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s) | |
a329b48c AK |
782 | |
783 | /* Shared peripheral bus arbiter */ | |
784 | DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET, | |
785 | NULL, NULL, &ipg_clk, NULL); | |
786 | ||
787 | /* UART */ | |
788 | DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET, | |
789 | NULL, NULL, &uart_root_clk, NULL); | |
790 | DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET, | |
791 | NULL, NULL, &uart_root_clk, NULL); | |
792 | DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET, | |
793 | NULL, NULL, &uart_root_clk, NULL); | |
794 | DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET, | |
795 | NULL, NULL, &ipg_clk, &aips_tz1_clk); | |
796 | DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET, | |
797 | NULL, NULL, &ipg_clk, &aips_tz1_clk); | |
798 | DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET, | |
799 | NULL, NULL, &ipg_clk, &spba_clk); | |
800 | ||
801 | /* GPT */ | |
802 | DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET, | |
1b6a2b2d | 803 | NULL, NULL, &ipg_clk, NULL); |
a329b48c AK |
804 | DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET, |
805 | NULL, NULL, &ipg_clk, NULL); | |
806 | ||
71c2e514 DN |
807 | /* I2C */ |
808 | DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET, | |
809 | NULL, NULL, &ipg_clk, NULL); | |
810 | DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET, | |
811 | NULL, NULL, &ipg_clk, NULL); | |
812 | DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET, | |
813 | NULL, NULL, &ipg_clk, NULL); | |
814 | ||
a329b48c AK |
815 | /* FEC */ |
816 | DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET, | |
817 | NULL, NULL, &ipg_clk, NULL); | |
818 | ||
819 | #define _REGISTER_CLOCK(d, n, c) \ | |
820 | { \ | |
821 | .dev_id = d, \ | |
822 | .con_id = n, \ | |
823 | .clk = &c, \ | |
824 | }, | |
825 | ||
826 | static struct clk_lookup lookups[] = { | |
827 | _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) | |
828 | _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) | |
829 | _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) | |
830 | _REGISTER_CLOCK(NULL, "gpt", gpt_clk) | |
831 | _REGISTER_CLOCK("fec.0", NULL, fec_clk) | |
71c2e514 DN |
832 | _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) |
833 | _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) | |
834 | _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) | |
c53bdf1c DN |
835 | _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) |
836 | _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) | |
837 | _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) | |
838 | _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) | |
2ba5a2c0 DN |
839 | _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) |
840 | _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) | |
a7ebd931 | 841 | _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) |
a329b48c AK |
842 | }; |
843 | ||
844 | static void clk_tree_init(void) | |
845 | { | |
846 | u32 reg; | |
847 | ||
848 | ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk); | |
849 | ||
850 | /* | |
851 | * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at | |
852 | * 8MHz, its derived from lp_apm. | |
853 | * | |
854 | * FIXME: Verify if true for all boards | |
855 | */ | |
856 | reg = __raw_readl(MXC_CCM_CBCDR); | |
857 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK; | |
858 | reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK; | |
859 | reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK; | |
860 | reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET); | |
861 | __raw_writel(reg, MXC_CCM_CBCDR); | |
862 | } | |
863 | ||
864 | int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, | |
865 | unsigned long ckih1, unsigned long ckih2) | |
866 | { | |
867 | int i; | |
868 | ||
869 | external_low_reference = ckil; | |
870 | external_high_reference = ckih1; | |
871 | ckih2_reference = ckih2; | |
872 | oscillator_reference = osc; | |
873 | ||
874 | for (i = 0; i < ARRAY_SIZE(lookups); i++) | |
875 | clkdev_add(&lookups[i]); | |
876 | ||
877 | clk_tree_init(); | |
878 | ||
879 | clk_enable(&cpu_clk); | |
880 | clk_enable(&main_bus_clk); | |
881 | ||
c79504e7 DN |
882 | /* set the usboh3_clk parent to pll2_sw_clk */ |
883 | clk_set_parent(&usboh3_clk, &pll2_sw_clk); | |
884 | ||
a329b48c AK |
885 | /* System timer */ |
886 | mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), | |
887 | MX51_MXC_INT_GPT); | |
888 | return 0; | |
889 | } |