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9a4cd7a5 DM |
1 | /* |
2 | * Copyright (C) 2000 Deep Blue Solutions Ltd | |
3 | * Copyright (C) 2002 Shane Nay (shane@minirl.com) | |
4 | * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
84677d11 | 5 | * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de> |
9a4cd7a5 DM |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | ||
22 | #include <linux/types.h> | |
23 | #include <linux/init.h> | |
24 | #include <linux/kernel.h> | |
25 | #include <linux/memory.h> | |
3211705f ML |
26 | #include <linux/platform_device.h> |
27 | #include <linux/gpio.h> | |
28 | #include <linux/smsc911x.h> | |
84677d11 DM |
29 | #include <linux/mfd/mc13783.h> |
30 | #include <linux/spi/spi.h> | |
a050c8e9 DM |
31 | #include <linux/usb/otg.h> |
32 | #include <linux/usb/ulpi.h> | |
6d3e6601 | 33 | #include <linux/mtd/physmap.h> |
9a4cd7a5 | 34 | |
9a4cd7a5 DM |
35 | #include <asm/mach-types.h> |
36 | #include <asm/mach/arch.h> | |
9e8a30dc | 37 | #include <asm/mach/time.h> |
9a4cd7a5 | 38 | #include <asm/mach/map.h> |
9a4cd7a5 DM |
39 | #include <asm/page.h> |
40 | #include <asm/setup.h> | |
84677d11 DM |
41 | |
42 | #include <mach/hardware.h> | |
43 | #include <mach/common.h> | |
a09e64fb | 44 | #include <mach/board-mx31lite.h> |
a854b8ab ML |
45 | #include <mach/imx-uart.h> |
46 | #include <mach/iomux-mx3.h> | |
3211705f | 47 | #include <mach/irqs.h> |
183c7fff | 48 | #include <mach/mxc_nand.h> |
84677d11 | 49 | #include <mach/spi.h> |
a050c8e9 DM |
50 | #include <mach/mxc_ehci.h> |
51 | #include <mach/ulpi.h> | |
84677d11 | 52 | |
a854b8ab | 53 | #include "devices.h" |
9a4cd7a5 DM |
54 | |
55 | /* | |
b7d91a62 | 56 | * This file contains the module-specific initialization routines. |
9a4cd7a5 DM |
57 | */ |
58 | ||
a854b8ab | 59 | static unsigned int mx31lite_pins[] = { |
3211705f ML |
60 | /* LAN9117 IRQ pin */ |
61 | IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), | |
84677d11 DM |
62 | /* SPI 1 */ |
63 | MX31_PIN_CSPI2_SCLK__SCLK, | |
64 | MX31_PIN_CSPI2_MOSI__MOSI, | |
65 | MX31_PIN_CSPI2_MISO__MISO, | |
66 | MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, | |
67 | MX31_PIN_CSPI2_SS0__SS0, | |
68 | MX31_PIN_CSPI2_SS1__SS1, | |
69 | MX31_PIN_CSPI2_SS2__SS2, | |
a854b8ab ML |
70 | }; |
71 | ||
183c7fff ML |
72 | static struct mxc_nand_platform_data mx31lite_nand_board_info = { |
73 | .width = 1, | |
74 | .hw_ecc = 1, | |
75 | }; | |
76 | ||
3211705f ML |
77 | static struct smsc911x_platform_config smsc911x_config = { |
78 | .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, | |
79 | .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, | |
80 | .flags = SMSC911X_USE_16BIT, | |
81 | }; | |
82 | ||
83 | static struct resource smsc911x_resources[] = { | |
3f4f54b4 | 84 | { |
3211705f ML |
85 | .start = CS4_BASE_ADDR, |
86 | .end = CS4_BASE_ADDR + 0x100, | |
87 | .flags = IORESOURCE_MEM, | |
3f4f54b4 | 88 | }, { |
3211705f ML |
89 | .start = IOMUX_TO_IRQ(MX31_PIN_SFS6), |
90 | .end = IOMUX_TO_IRQ(MX31_PIN_SFS6), | |
91 | .flags = IORESOURCE_IRQ, | |
92 | }, | |
93 | }; | |
94 | ||
95 | static struct platform_device smsc911x_device = { | |
96 | .name = "smsc911x", | |
97 | .id = -1, | |
98 | .num_resources = ARRAY_SIZE(smsc911x_resources), | |
99 | .resource = smsc911x_resources, | |
100 | .dev = { | |
101 | .platform_data = &smsc911x_config, | |
102 | }, | |
103 | }; | |
104 | ||
84677d11 DM |
105 | /* |
106 | * SPI | |
107 | * | |
108 | * The MC13783 is the only hard-wired SPI device on the module. | |
109 | */ | |
110 | ||
111 | static int spi_internal_chipselect[] = { | |
112 | MXC_SPI_CS(0), | |
113 | }; | |
114 | ||
115 | static struct spi_imx_master spi1_pdata = { | |
116 | .chipselect = spi_internal_chipselect, | |
117 | .num_chipselect = ARRAY_SIZE(spi_internal_chipselect), | |
118 | }; | |
119 | ||
120 | static struct mc13783_platform_data mc13783_pdata __initdata = { | |
121 | .flags = MC13783_USE_RTC | | |
122 | MC13783_USE_REGULATOR, | |
123 | }; | |
124 | ||
125 | static struct spi_board_info mc13783_spi_dev __initdata = { | |
126 | .modalias = "mc13783", | |
127 | .max_speed_hz = 1000000, | |
128 | .bus_num = 1, | |
129 | .chip_select = 0, | |
130 | .platform_data = &mc13783_pdata, | |
131 | .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3), | |
132 | }; | |
133 | ||
a050c8e9 DM |
134 | /* |
135 | * USB | |
136 | */ | |
137 | ||
f9ffaa9c | 138 | #if defined(CONFIG_USB_ULPI) |
a050c8e9 DM |
139 | #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \ |
140 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) | |
141 | ||
142 | static int usbh2_init(struct platform_device *pdev) | |
143 | { | |
144 | int pins[] = { | |
145 | MX31_PIN_USBH2_DATA0__USBH2_DATA0, | |
146 | MX31_PIN_USBH2_DATA1__USBH2_DATA1, | |
147 | MX31_PIN_USBH2_CLK__USBH2_CLK, | |
148 | MX31_PIN_USBH2_DIR__USBH2_DIR, | |
149 | MX31_PIN_USBH2_NXT__USBH2_NXT, | |
150 | MX31_PIN_USBH2_STP__USBH2_STP, | |
151 | }; | |
152 | ||
153 | mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2"); | |
154 | ||
155 | mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG); | |
156 | mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG); | |
157 | mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG); | |
158 | mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG); | |
159 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG); | |
160 | mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG); | |
161 | mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG); | |
162 | mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG); | |
163 | mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG); | |
164 | mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG); | |
165 | mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG); | |
166 | mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG); | |
167 | ||
168 | mxc_iomux_set_gpr(MUX_PGP_UH2, true); | |
169 | ||
170 | /* chip select */ | |
171 | mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO), | |
172 | "USBH2_CS"); | |
173 | gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); | |
174 | gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0); | |
175 | ||
176 | return 0; | |
177 | } | |
178 | ||
179 | static struct mxc_usbh_platform_data usbh2_pdata = { | |
180 | .init = usbh2_init, | |
181 | .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, | |
182 | .flags = MXC_EHCI_POWER_PINS_ENABLED, | |
183 | }; | |
f9ffaa9c | 184 | #endif |
a050c8e9 | 185 | |
6d3e6601 DM |
186 | /* |
187 | * NOR flash | |
188 | */ | |
189 | ||
190 | static struct physmap_flash_data nor_flash_data = { | |
191 | .width = 2, | |
192 | }; | |
193 | ||
194 | static struct resource nor_flash_resource = { | |
195 | .start = 0xa0000000, | |
196 | .end = 0xa1ffffff, | |
197 | .flags = IORESOURCE_MEM, | |
198 | }; | |
199 | ||
200 | static struct platform_device physmap_flash_device = { | |
201 | .name = "physmap-flash", | |
202 | .id = 0, | |
203 | .dev = { | |
204 | .platform_data = &nor_flash_data, | |
205 | }, | |
206 | .resource = &nor_flash_resource, | |
207 | .num_resources = 1, | |
208 | }; | |
209 | ||
210 | ||
211 | ||
9a4cd7a5 DM |
212 | /* |
213 | * This structure defines the MX31 memory map. | |
214 | */ | |
215 | static struct map_desc mx31lite_io_desc[] __initdata = { | |
216 | { | |
9a4cd7a5 DM |
217 | .virtual = CS4_BASE_ADDR_VIRT, |
218 | .pfn = __phys_to_pfn(CS4_BASE_ADDR), | |
219 | .length = CS4_SIZE, | |
220 | .type = MT_DEVICE | |
221 | } | |
222 | }; | |
223 | ||
224 | /* | |
225 | * Set up static virtual mappings. | |
226 | */ | |
227 | void __init mx31lite_map_io(void) | |
228 | { | |
cd4a05f9 | 229 | mx31_map_io(); |
9a4cd7a5 DM |
230 | iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc)); |
231 | } | |
232 | ||
b7d91a62 DM |
233 | static int mx31lite_baseboard; |
234 | core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444); | |
235 | ||
9a4cd7a5 DM |
236 | static void __init mxc_board_init(void) |
237 | { | |
4f163eb8 SH |
238 | int ret; |
239 | ||
b7d91a62 DM |
240 | switch (mx31lite_baseboard) { |
241 | case MX31LITE_NOBOARD: | |
242 | break; | |
243 | case MX31LITE_DB: | |
244 | mx31lite_db_init(); | |
245 | break; | |
246 | default: | |
247 | printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n", | |
248 | mx31lite_baseboard); | |
249 | } | |
250 | ||
a854b8ab ML |
251 | mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins), |
252 | "mx31lite"); | |
253 | ||
6d3e6601 DM |
254 | /* NOR and NAND flash */ |
255 | platform_device_register(&physmap_flash_device); | |
183c7fff | 256 | mxc_register_device(&mxc_nand_device, &mx31lite_nand_board_info); |
6d3e6601 | 257 | |
84677d11 DM |
258 | mxc_register_device(&mxc_spi_device1, &spi1_pdata); |
259 | spi_register_board_info(&mc13783_spi_dev, 1); | |
3211705f | 260 | |
f9ffaa9c | 261 | #if defined(CONFIG_USB_ULPI) |
a050c8e9 DM |
262 | /* USB */ |
263 | usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | |
264 | USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT); | |
265 | ||
266 | mxc_register_device(&mxc_usbh2, &usbh2_pdata); | |
f9ffaa9c | 267 | #endif |
a050c8e9 | 268 | |
3211705f | 269 | /* SMSC9117 IRQ pin */ |
4f163eb8 SH |
270 | ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq"); |
271 | if (ret) | |
272 | pr_warning("could not get LAN irq gpio\n"); | |
273 | else { | |
274 | gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6)); | |
275 | platform_device_register(&smsc911x_device); | |
276 | } | |
9a4cd7a5 DM |
277 | } |
278 | ||
9e8a30dc JB |
279 | static void __init mx31lite_timer_init(void) |
280 | { | |
30c730f8 | 281 | mx31_clocks_init(26000000); |
9e8a30dc JB |
282 | } |
283 | ||
284 | struct sys_timer mx31lite_timer = { | |
285 | .init = mx31lite_timer_init, | |
286 | }; | |
287 | ||
b7d91a62 | 288 | MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") |
9a4cd7a5 DM |
289 | /* Maintainer: Freescale Semiconductor, Inc. */ |
290 | .phys_io = AIPS1_BASE_ADDR, | |
291 | .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | |
292 | .boot_params = PHYS_OFFSET + 0x100, | |
293 | .map_io = mx31lite_map_io, | |
c5aa0ad0 | 294 | .init_irq = mx31_init_irq, |
9a4cd7a5 | 295 | .init_machine = mxc_board_init, |
9e8a30dc | 296 | .timer = &mx31lite_timer, |
9a4cd7a5 | 297 | MACHINE_END |