[linux-2.6-block.git] / arch / arm / mach-mx3 / mm.c

/*
 *  Copyright (C) 1999,2000 Arm Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *    - add MX31 specific definitions
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/mm.h>
#include <linux/init.h>
#include <linux/err.h>

#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <asm/hardware/cache-l2x0.h>

#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>

/*!
 * @file mm.c
 *
 * @brief This file creates static virtual to physical mappings, common to all MX3 boards.
 *
 * @ingroup Memory
 */

/*!
 * This table defines static virtual address mappings for I/O regions.
 * These are the mappings common across all MX3 boards.
 */
static struct map_desc mxc_io_desc[] __initdata = {
	{
		.virtual	= X_MEMC_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(X_MEMC_BASE_ADDR),
		.length		= X_MEMC_SIZE,
		.type		= MT_DEVICE
	}, {
		.virtual	= AVIC_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(AVIC_BASE_ADDR),
		.length		= AVIC_SIZE,
		.type		= MT_DEVICE_NONSHARED
	}, {
		.virtual	= AIPS1_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(AIPS1_BASE_ADDR),
		.length		= AIPS1_SIZE,
		.type		= MT_DEVICE_NONSHARED
	}, {
		.virtual	= AIPS2_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(AIPS2_BASE_ADDR),
		.length		= AIPS2_SIZE,
		.type		= MT_DEVICE_NONSHARED
	}, {
		.virtual = SPBA0_BASE_ADDR_VIRT,
		.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
		.length = SPBA0_SIZE,
		.type = MT_DEVICE_NONSHARED
	},
};

/*!
 * This function initializes the memory map. It is called during the
 * system startup to create static physical to virtual memory mappings
 * for the IO modules.
 */
void __init mx31_map_io(void)
{
	mxc_set_cpu_type(MXC_CPU_MX31);
	mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));

	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}

#ifdef CONFIG_ARCH_MX35
void __init mx35_map_io(void)
{
	mxc_set_cpu_type(MXC_CPU_MX35);
	mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
	mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));

	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
}
#endif

void __init mx31_init_irq(void)
{
	mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
}

void __init mx35_init_irq(void)
{
	mx31_init_irq();
}

#ifdef CONFIG_CACHE_L2X0
static int mxc_init_l2x0(void)
{
	void __iomem *l2x0_base;

	l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
	if (IS_ERR(l2x0_base)) {
		printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
				PTR_ERR(l2x0_base));
		return 0;
	}

	l2x0_init(l2x0_base, 0x00030024, 0x00000000);

	return 0;
}

arch_initcall(mxc_init_l2x0);
#endif
Commit	Line	Data
52c543f9 QJ	1	/*
	2	* Copyright (C) 1999,2000 Arm Limited
	3	* Copyright (C) 2000 Deep Blue Solutions Ltd
	4	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	5	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	6	* - add MX31 specific definitions
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*/
	22
	23	#include <linux/mm.h>
	24	#include <linux/init.h>
cb88214d SH	25	#include <linux/err.h>
cb88214d SH	26
52c543f9 QJ	27	#include <asm/pgtable.h>
52c543f9 QJ	28	#include <asm/mach/map.h>
cb88214d SH	29	#include <asm/hardware/cache-l2x0.h>
cb88214d SH	30
a09e64fb	31	#include <mach/common.h>
cb88214d	32	#include <mach/hardware.h>
6134b2cb	33	#include <mach/iomux-v3.h>
52c543f9 QJ	34
	35	/*!
	36	* @file mm.c
	37	*
	38	* @brief This file creates static virtual to physical mappings, common to all MX3 boards.
	39	*
	40	* @ingroup Memory
	41	*/
	42
	43	/*!
	44	* This table defines static virtual address mappings for I/O regions.
	45	* These are the mappings common across all MX3 boards.
	46	*/
	47	static struct map_desc mxc_io_desc[] __initdata = {
	48	{
	49	.virtual = X_MEMC_BASE_ADDR_VIRT,
	50	.pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
	51	.length = X_MEMC_SIZE,
	52	.type = MT_DEVICE
	53	}, {
	54	.virtual = AVIC_BASE_ADDR_VIRT,
	55	.pfn = __phys_to_pfn(AVIC_BASE_ADDR),
	56	.length = AVIC_SIZE,
9b727abd	57	.type = MT_DEVICE_NONSHARED
fb4416ad SH	58	}, {
	59	.virtual = AIPS1_BASE_ADDR_VIRT,
	60	.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
	61	.length = AIPS1_SIZE,
	62	.type = MT_DEVICE_NONSHARED
	63	}, {
	64	.virtual = AIPS2_BASE_ADDR_VIRT,
	65	.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
	66	.length = AIPS2_SIZE,
	67	.type = MT_DEVICE_NONSHARED
e94c4c34 WD	68	}, {
	69	.virtual = SPBA0_BASE_ADDR_VIRT,
	70	.pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
	71	.length = SPBA0_SIZE,
	72	.type = MT_DEVICE_NONSHARED
52c543f9 QJ	73	},
	74	};
	75
	76	/*!
	77	* This function initializes the memory map. It is called during the
	78	* system startup to create static physical to virtual memory mappings
	79	* for the IO modules.
	80	*/
cd4a05f9	81	void __init mx31_map_io(void)
52c543f9	82	{
cd4a05f9	83	mxc_set_cpu_type(MXC_CPU_MX31);
be124c94	84	mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
cd4a05f9 SH	85
	86	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
	87	}
	88
324c1aa3	89	#ifdef CONFIG_ARCH_MX35
cd4a05f9 SH	90	void __init mx35_map_io(void)
	91	{
	92	mxc_set_cpu_type(MXC_CPU_MX35);
6134b2cb	93	mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR));
be124c94	94	mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
cd4a05f9	95
52c543f9 QJ	96	iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
52c543f9 QJ	97	}
324c1aa3	98	#endif
cb88214d	99
c5aa0ad0 SH	100	void __init mx31_init_irq(void)
	101	{
	102	mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR));
	103	}
	104
	105	void __init mx35_init_irq(void)
	106	{
	107	mx31_init_irq();
	108	}
	109
cb88214d SH	110	#ifdef CONFIG_CACHE_L2X0
	111	static int mxc_init_l2x0(void)
	112	{
	113	void __iomem *l2x0_base;
	114
	115	l2x0_base = ioremap(L2CC_BASE_ADDR, 4096);
	116	if (IS_ERR(l2x0_base)) {
	117	printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
	118	PTR_ERR(l2x0_base));
	119	return 0;
	120	}
	121
	122	l2x0_init(l2x0_base, 0x00030024, 0x00000000);
	123
	124	return 0;
	125	}
	126
	127	arch_initcall(mxc_init_l2x0);
	128	#endif
	129