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54df5268 SH |
1 | /* |
2 | * Copyright (C) 2009 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
54df5268 SH |
13 | */ |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/init.h> | |
17 | ||
18 | #include <linux/platform_device.h> | |
19 | #include <linux/mtd/physmap.h> | |
20 | #include <linux/mtd/plat-ram.h> | |
21 | #include <linux/memory.h> | |
22 | #include <linux/gpio.h> | |
23 | #include <linux/smc911x.h> | |
24 | #include <linux/interrupt.h> | |
d2831d1f | 25 | #include <linux/delay.h> |
54df5268 SH |
26 | #include <linux/i2c.h> |
27 | #include <linux/i2c/at24.h> | |
cb2dc111 SH |
28 | #include <linux/usb/otg.h> |
29 | #include <linux/usb/ulpi.h> | |
30 | #include <linux/fsl_devices.h> | |
54df5268 SH |
31 | |
32 | #include <asm/mach-types.h> | |
33 | #include <asm/mach/arch.h> | |
34 | #include <asm/mach/time.h> | |
35 | #include <asm/mach/map.h> | |
36 | ||
37 | #include <mach/hardware.h> | |
38 | #include <mach/common.h> | |
54df5268 SH |
39 | #include <mach/iomux-mx35.h> |
40 | #include <mach/ipu.h> | |
41 | #include <mach/mx3fb.h> | |
cb2dc111 SH |
42 | #include <mach/mxc_ehci.h> |
43 | #include <mach/ulpi.h> | |
d2831d1f | 44 | #include <mach/audmux.h> |
54df5268 | 45 | |
e2611ba4 | 46 | #include "devices-imx35.h" |
54df5268 SH |
47 | #include "devices.h" |
48 | ||
49 | static const struct fb_videomode fb_modedb[] = { | |
50 | { | |
51 | /* 240x320 @ 60 Hz */ | |
52 | .name = "Sharp-LQ035Q7", | |
53 | .refresh = 60, | |
54 | .xres = 240, | |
55 | .yres = 320, | |
56 | .pixclock = 185925, | |
57 | .left_margin = 9, | |
58 | .right_margin = 16, | |
59 | .upper_margin = 7, | |
60 | .lower_margin = 9, | |
61 | .hsync_len = 1, | |
62 | .vsync_len = 1, | |
63 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, | |
64 | .vmode = FB_VMODE_NONINTERLACED, | |
65 | .flag = 0, | |
66 | }, { | |
67 | /* 240x320 @ 60 Hz */ | |
68 | .name = "TX090", | |
69 | .refresh = 60, | |
70 | .xres = 240, | |
71 | .yres = 320, | |
72 | .pixclock = 38255, | |
73 | .left_margin = 144, | |
74 | .right_margin = 0, | |
75 | .upper_margin = 7, | |
76 | .lower_margin = 40, | |
77 | .hsync_len = 96, | |
78 | .vsync_len = 1, | |
79 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, | |
80 | .vmode = FB_VMODE_NONINTERLACED, | |
81 | .flag = 0, | |
82 | }, | |
83 | }; | |
84 | ||
85 | static struct ipu_platform_data mx3_ipu_data = { | |
86 | .irq_base = MXC_IPU_IRQ_START, | |
87 | }; | |
88 | ||
89 | static struct mx3fb_platform_data mx3fb_pdata = { | |
90 | .dma_dev = &mx3_ipu.dev, | |
91 | .name = "Sharp-LQ035Q7", | |
92 | .mode = fb_modedb, | |
93 | .num_modes = ARRAY_SIZE(fb_modedb), | |
94 | }; | |
95 | ||
96 | static struct physmap_flash_data pcm043_flash_data = { | |
97 | .width = 2, | |
98 | }; | |
99 | ||
100 | static struct resource pcm043_flash_resource = { | |
101 | .start = 0xa0000000, | |
102 | .end = 0xa1ffffff, | |
103 | .flags = IORESOURCE_MEM, | |
104 | }; | |
105 | ||
106 | static struct platform_device pcm043_flash = { | |
107 | .name = "physmap-flash", | |
108 | .id = 0, | |
109 | .dev = { | |
110 | .platform_data = &pcm043_flash_data, | |
111 | }, | |
112 | .resource = &pcm043_flash_resource, | |
113 | .num_resources = 1, | |
114 | }; | |
115 | ||
6eafde5f | 116 | static const struct imxuart_platform_data uart_pdata __initconst = { |
54df5268 SH |
117 | .flags = IMXUART_HAVE_RTSCTS, |
118 | }; | |
119 | ||
120 | #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE | |
7cdc8fa7 | 121 | static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { |
54df5268 SH |
122 | .bitrate = 50000, |
123 | }; | |
124 | ||
125 | static struct at24_platform_data board_eeprom = { | |
126 | .byte_len = 4096, | |
127 | .page_size = 32, | |
128 | .flags = AT24_FLAG_ADDR16, | |
129 | }; | |
130 | ||
131 | static struct i2c_board_info pcm043_i2c_devices[] = { | |
132 | { | |
133 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ | |
134 | .platform_data = &board_eeprom, | |
135 | }, { | |
cf87a6e2 | 136 | I2C_BOARD_INFO("pcf8563", 0x51), |
54df5268 SH |
137 | } |
138 | }; | |
139 | #endif | |
140 | ||
141 | static struct platform_device *devices[] __initdata = { | |
142 | &pcm043_flash, | |
143 | &mxc_fec_device, | |
3170ba54 | 144 | &imx_wdt_device0, |
54df5268 SH |
145 | }; |
146 | ||
147 | static struct pad_desc pcm043_pads[] = { | |
148 | /* UART1 */ | |
149 | MX35_PAD_CTS1__UART1_CTS, | |
150 | MX35_PAD_RTS1__UART1_RTS, | |
151 | MX35_PAD_TXD1__UART1_TXD_MUX, | |
152 | MX35_PAD_RXD1__UART1_RXD_MUX, | |
153 | /* UART2 */ | |
154 | MX35_PAD_CTS2__UART2_CTS, | |
155 | MX35_PAD_RTS2__UART2_RTS, | |
156 | MX35_PAD_TXD2__UART2_TXD_MUX, | |
157 | MX35_PAD_RXD2__UART2_RXD_MUX, | |
158 | /* FEC */ | |
159 | MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, | |
160 | MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, | |
161 | MX35_PAD_FEC_RX_DV__FEC_RX_DV, | |
162 | MX35_PAD_FEC_COL__FEC_COL, | |
163 | MX35_PAD_FEC_RDATA0__FEC_RDATA_0, | |
164 | MX35_PAD_FEC_TDATA0__FEC_TDATA_0, | |
165 | MX35_PAD_FEC_TX_EN__FEC_TX_EN, | |
166 | MX35_PAD_FEC_MDC__FEC_MDC, | |
167 | MX35_PAD_FEC_MDIO__FEC_MDIO, | |
168 | MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, | |
169 | MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, | |
170 | MX35_PAD_FEC_CRS__FEC_CRS, | |
171 | MX35_PAD_FEC_RDATA1__FEC_RDATA_1, | |
172 | MX35_PAD_FEC_TDATA1__FEC_TDATA_1, | |
173 | MX35_PAD_FEC_RDATA2__FEC_RDATA_2, | |
174 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, | |
175 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, | |
176 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, | |
177 | /* I2C1 */ | |
178 | MX35_PAD_I2C1_CLK__I2C1_SCL, | |
179 | MX35_PAD_I2C1_DAT__I2C1_SDA, | |
180 | /* Display */ | |
181 | MX35_PAD_LD0__IPU_DISPB_DAT_0, | |
182 | MX35_PAD_LD1__IPU_DISPB_DAT_1, | |
183 | MX35_PAD_LD2__IPU_DISPB_DAT_2, | |
184 | MX35_PAD_LD3__IPU_DISPB_DAT_3, | |
185 | MX35_PAD_LD4__IPU_DISPB_DAT_4, | |
186 | MX35_PAD_LD5__IPU_DISPB_DAT_5, | |
187 | MX35_PAD_LD6__IPU_DISPB_DAT_6, | |
188 | MX35_PAD_LD7__IPU_DISPB_DAT_7, | |
189 | MX35_PAD_LD8__IPU_DISPB_DAT_8, | |
190 | MX35_PAD_LD9__IPU_DISPB_DAT_9, | |
191 | MX35_PAD_LD10__IPU_DISPB_DAT_10, | |
192 | MX35_PAD_LD11__IPU_DISPB_DAT_11, | |
193 | MX35_PAD_LD12__IPU_DISPB_DAT_12, | |
194 | MX35_PAD_LD13__IPU_DISPB_DAT_13, | |
195 | MX35_PAD_LD14__IPU_DISPB_DAT_14, | |
196 | MX35_PAD_LD15__IPU_DISPB_DAT_15, | |
197 | MX35_PAD_LD16__IPU_DISPB_DAT_16, | |
198 | MX35_PAD_LD17__IPU_DISPB_DAT_17, | |
199 | MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, | |
200 | MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, | |
201 | MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, | |
202 | MX35_PAD_CONTRAST__IPU_DISPB_CONTR, | |
203 | MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, | |
204 | MX35_PAD_D3_REV__IPU_DISPB_D3_REV, | |
205 | MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, | |
8d5c1ed3 LF |
206 | /* gpio */ |
207 | MX35_PAD_ATA_CS0__GPIO2_6, | |
cb2dc111 SH |
208 | /* USB host */ |
209 | MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, | |
210 | MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, | |
d2831d1f SH |
211 | /* SSI */ |
212 | MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, | |
213 | MX35_PAD_STXD4__AUDMUX_AUD4_TXD, | |
214 | MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, | |
215 | MX35_PAD_SCK4__AUDMUX_AUD4_TXC, | |
da92e42b MKB |
216 | /* CAN2 */ |
217 | MX35_PAD_TX5_RX0__CAN2_TXCAN, | |
218 | MX35_PAD_TX4_RX1__CAN2_RXCAN, | |
d2831d1f SH |
219 | }; |
220 | ||
221 | #define AC97_GPIO_TXFS (1 * 32 + 31) | |
222 | #define AC97_GPIO_TXD (1 * 32 + 28) | |
223 | #define AC97_GPIO_RESET (1 * 32 + 0) | |
224 | ||
225 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) | |
226 | { | |
227 | struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; | |
228 | struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; | |
229 | int ret; | |
230 | ||
231 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); | |
232 | if (ret) { | |
233 | printk("failed to get GPIO_TXFS: %d\n", ret); | |
234 | return; | |
235 | } | |
236 | ||
237 | mxc_iomux_v3_setup_pad(&txfs_gpio); | |
238 | ||
239 | /* warm reset */ | |
240 | gpio_direction_output(AC97_GPIO_TXFS, 1); | |
241 | udelay(2); | |
242 | gpio_set_value(AC97_GPIO_TXFS, 0); | |
243 | ||
244 | gpio_free(AC97_GPIO_TXFS); | |
245 | mxc_iomux_v3_setup_pad(&txfs); | |
246 | } | |
247 | ||
248 | static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) | |
249 | { | |
250 | struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; | |
251 | struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; | |
252 | struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; | |
253 | struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; | |
254 | struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; | |
255 | int ret; | |
256 | ||
257 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); | |
258 | if (ret) | |
259 | goto err1; | |
260 | ||
261 | ret = gpio_request(AC97_GPIO_TXD, "SSI"); | |
262 | if (ret) | |
263 | goto err2; | |
264 | ||
265 | ret = gpio_request(AC97_GPIO_RESET, "SSI"); | |
266 | if (ret) | |
267 | goto err3; | |
268 | ||
269 | mxc_iomux_v3_setup_pad(&txfs_gpio); | |
270 | mxc_iomux_v3_setup_pad(&txd_gpio); | |
271 | mxc_iomux_v3_setup_pad(&reset_gpio); | |
272 | ||
273 | gpio_direction_output(AC97_GPIO_TXFS, 0); | |
274 | gpio_direction_output(AC97_GPIO_TXD, 0); | |
275 | ||
276 | /* cold reset */ | |
277 | gpio_direction_output(AC97_GPIO_RESET, 0); | |
278 | udelay(10); | |
279 | gpio_direction_output(AC97_GPIO_RESET, 1); | |
280 | ||
281 | mxc_iomux_v3_setup_pad(&txd); | |
282 | mxc_iomux_v3_setup_pad(&txfs); | |
283 | ||
284 | gpio_free(AC97_GPIO_RESET); | |
285 | err3: | |
286 | gpio_free(AC97_GPIO_TXD); | |
287 | err2: | |
288 | gpio_free(AC97_GPIO_TXFS); | |
289 | err1: | |
290 | if (ret) | |
291 | printk("%s failed with %d\n", __func__, ret); | |
292 | mdelay(1); | |
293 | } | |
294 | ||
4697bb92 | 295 | static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { |
d2831d1f SH |
296 | .ac97_reset = pcm043_ac97_cold_reset, |
297 | .ac97_warm_reset = pcm043_ac97_warm_reset, | |
298 | .flags = IMX_SSI_USE_AC97, | |
54df5268 SH |
299 | }; |
300 | ||
e2611ba4 UKK |
301 | static const struct mxc_nand_platform_data |
302 | pcm037_nand_board_info __initconst = { | |
4f43c2ed SH |
303 | .width = 1, |
304 | .hw_ecc = 1, | |
305 | }; | |
306 | ||
c18e8fa5 | 307 | #if defined(CONFIG_USB_ULPI) |
cb2dc111 SH |
308 | static struct mxc_usbh_platform_data otg_pdata = { |
309 | .portsc = MXC_EHCI_MODE_UTMI, | |
310 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | |
311 | }; | |
312 | ||
313 | static struct mxc_usbh_platform_data usbh1_pdata = { | |
314 | .portsc = MXC_EHCI_MODE_SERIAL, | |
315 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | | |
316 | MXC_EHCI_IPPUE_DOWN, | |
317 | }; | |
c18e8fa5 | 318 | #endif |
cb2dc111 SH |
319 | |
320 | static struct fsl_usb2_platform_data otg_device_pdata = { | |
321 | .operating_mode = FSL_USB2_DR_DEVICE, | |
322 | .phy_mode = FSL_USB2_PHY_UTMI, | |
323 | }; | |
324 | ||
325 | static int otg_mode_host; | |
326 | ||
327 | static int __init pcm043_otg_mode(char *options) | |
328 | { | |
329 | if (!strcmp(options, "host")) | |
330 | otg_mode_host = 1; | |
331 | else if (!strcmp(options, "device")) | |
332 | otg_mode_host = 0; | |
333 | else | |
334 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
335 | "Defaulting to device\n"); | |
336 | return 0; | |
337 | } | |
338 | __setup("otg_mode=", pcm043_otg_mode); | |
339 | ||
54df5268 SH |
340 | /* |
341 | * Board specific initialization. | |
342 | */ | |
343 | static void __init mxc_board_init(void) | |
344 | { | |
345 | mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); | |
346 | ||
d2831d1f SH |
347 | mxc_audmux_v2_configure_port(3, |
348 | MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ | |
349 | MXC_AUDMUX_V2_PTCR_TFSEL(0) | | |
350 | MXC_AUDMUX_V2_PTCR_TFSDIR, | |
351 | MXC_AUDMUX_V2_PDCR_RXDSEL(0)); | |
352 | ||
353 | mxc_audmux_v2_configure_port(0, | |
354 | MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ | |
355 | MXC_AUDMUX_V2_PTCR_TCSEL(3) | | |
356 | MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ | |
357 | MXC_AUDMUX_V2_PDCR_RXDSEL(3)); | |
358 | ||
54df5268 SH |
359 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
360 | ||
6eafde5f | 361 | imx35_add_imx_uart0(&uart_pdata); |
e2611ba4 | 362 | imx35_add_mxc_nand(&pcm037_nand_board_info); |
4697bb92 | 363 | imx35_add_imx_ssi(0, &pcm043_ssi_pdata); |
54df5268 | 364 | |
6eafde5f | 365 | imx35_add_imx_uart1(&uart_pdata); |
54df5268 SH |
366 | |
367 | #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE | |
368 | i2c_register_board_info(0, pcm043_i2c_devices, | |
369 | ARRAY_SIZE(pcm043_i2c_devices)); | |
370 | ||
7cdc8fa7 | 371 | imx35_add_imx_i2c0(&pcm043_i2c0_data); |
54df5268 SH |
372 | #endif |
373 | ||
374 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); | |
375 | mxc_register_device(&mx3_fb, &mx3fb_pdata); | |
cb2dc111 SH |
376 | |
377 | #if defined(CONFIG_USB_ULPI) | |
378 | if (otg_mode_host) { | |
379 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | |
13dd0c97 | 380 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
cb2dc111 SH |
381 | |
382 | mxc_register_device(&mxc_otg_host, &otg_pdata); | |
383 | } | |
384 | ||
385 | mxc_register_device(&mxc_usbh1, &usbh1_pdata); | |
386 | #endif | |
387 | if (!otg_mode_host) | |
388 | mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); | |
389 | ||
da92e42b | 390 | imx35_add_flexcan1(NULL); |
54df5268 SH |
391 | } |
392 | ||
393 | static void __init pcm043_timer_init(void) | |
394 | { | |
395 | mx35_clocks_init(); | |
396 | } | |
397 | ||
398 | struct sys_timer pcm043_timer = { | |
399 | .init = pcm043_timer_init, | |
400 | }; | |
401 | ||
402 | MACHINE_START(PCM043, "Phytec Phycore pcm043") | |
403 | /* Maintainer: Pengutronix */ | |
f568dd7f UKK |
404 | .phys_io = MX35_AIPS1_BASE_ADDR, |
405 | .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, | |
34101237 | 406 | .boot_params = MX3x_PHYS_OFFSET + 0x100, |
cd4a05f9 | 407 | .map_io = mx35_map_io, |
c5aa0ad0 | 408 | .init_irq = mx35_init_irq, |
54df5268 SH |
409 | .init_machine = mxc_board_init, |
410 | .timer = &pcm043_timer, | |
411 | MACHINE_END | |
412 |