Commit | Line | Data |
---|---|---|
54df5268 SH |
1 | /* |
2 | * Copyright (C) 2009 Sascha Hauer, Pengutronix | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
54df5268 SH |
13 | */ |
14 | ||
15 | #include <linux/types.h> | |
16 | #include <linux/init.h> | |
17 | ||
18 | #include <linux/platform_device.h> | |
19 | #include <linux/mtd/physmap.h> | |
20 | #include <linux/mtd/plat-ram.h> | |
21 | #include <linux/memory.h> | |
22 | #include <linux/gpio.h> | |
23 | #include <linux/smc911x.h> | |
24 | #include <linux/interrupt.h> | |
d2831d1f | 25 | #include <linux/delay.h> |
54df5268 SH |
26 | #include <linux/i2c.h> |
27 | #include <linux/i2c/at24.h> | |
cb2dc111 SH |
28 | #include <linux/usb/otg.h> |
29 | #include <linux/usb/ulpi.h> | |
54df5268 SH |
30 | |
31 | #include <asm/mach-types.h> | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/time.h> | |
34 | #include <asm/mach/map.h> | |
35 | ||
36 | #include <mach/hardware.h> | |
37 | #include <mach/common.h> | |
54df5268 SH |
38 | #include <mach/iomux-mx35.h> |
39 | #include <mach/ipu.h> | |
40 | #include <mach/mx3fb.h> | |
cb2dc111 | 41 | #include <mach/ulpi.h> |
d2831d1f | 42 | #include <mach/audmux.h> |
54df5268 | 43 | |
e2611ba4 | 44 | #include "devices-imx35.h" |
54df5268 SH |
45 | #include "devices.h" |
46 | ||
47 | static const struct fb_videomode fb_modedb[] = { | |
48 | { | |
49 | /* 240x320 @ 60 Hz */ | |
50 | .name = "Sharp-LQ035Q7", | |
51 | .refresh = 60, | |
52 | .xres = 240, | |
53 | .yres = 320, | |
54 | .pixclock = 185925, | |
55 | .left_margin = 9, | |
56 | .right_margin = 16, | |
57 | .upper_margin = 7, | |
58 | .lower_margin = 9, | |
59 | .hsync_len = 1, | |
60 | .vsync_len = 1, | |
61 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN, | |
62 | .vmode = FB_VMODE_NONINTERLACED, | |
63 | .flag = 0, | |
64 | }, { | |
65 | /* 240x320 @ 60 Hz */ | |
66 | .name = "TX090", | |
67 | .refresh = 60, | |
68 | .xres = 240, | |
69 | .yres = 320, | |
70 | .pixclock = 38255, | |
71 | .left_margin = 144, | |
72 | .right_margin = 0, | |
73 | .upper_margin = 7, | |
74 | .lower_margin = 40, | |
75 | .hsync_len = 96, | |
76 | .vsync_len = 1, | |
77 | .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH, | |
78 | .vmode = FB_VMODE_NONINTERLACED, | |
79 | .flag = 0, | |
80 | }, | |
81 | }; | |
82 | ||
83 | static struct ipu_platform_data mx3_ipu_data = { | |
84 | .irq_base = MXC_IPU_IRQ_START, | |
85 | }; | |
86 | ||
87 | static struct mx3fb_platform_data mx3fb_pdata = { | |
88 | .dma_dev = &mx3_ipu.dev, | |
89 | .name = "Sharp-LQ035Q7", | |
90 | .mode = fb_modedb, | |
91 | .num_modes = ARRAY_SIZE(fb_modedb), | |
92 | }; | |
93 | ||
94 | static struct physmap_flash_data pcm043_flash_data = { | |
95 | .width = 2, | |
96 | }; | |
97 | ||
98 | static struct resource pcm043_flash_resource = { | |
99 | .start = 0xa0000000, | |
100 | .end = 0xa1ffffff, | |
101 | .flags = IORESOURCE_MEM, | |
102 | }; | |
103 | ||
104 | static struct platform_device pcm043_flash = { | |
105 | .name = "physmap-flash", | |
106 | .id = 0, | |
107 | .dev = { | |
108 | .platform_data = &pcm043_flash_data, | |
109 | }, | |
110 | .resource = &pcm043_flash_resource, | |
111 | .num_resources = 1, | |
112 | }; | |
113 | ||
6eafde5f | 114 | static const struct imxuart_platform_data uart_pdata __initconst = { |
54df5268 SH |
115 | .flags = IMXUART_HAVE_RTSCTS, |
116 | }; | |
117 | ||
7cdc8fa7 | 118 | static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = { |
54df5268 SH |
119 | .bitrate = 50000, |
120 | }; | |
121 | ||
122 | static struct at24_platform_data board_eeprom = { | |
123 | .byte_len = 4096, | |
124 | .page_size = 32, | |
125 | .flags = AT24_FLAG_ADDR16, | |
126 | }; | |
127 | ||
128 | static struct i2c_board_info pcm043_i2c_devices[] = { | |
129 | { | |
130 | I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */ | |
131 | .platform_data = &board_eeprom, | |
132 | }, { | |
cf87a6e2 | 133 | I2C_BOARD_INFO("pcf8563", 0x51), |
54df5268 SH |
134 | } |
135 | }; | |
54df5268 SH |
136 | |
137 | static struct platform_device *devices[] __initdata = { | |
138 | &pcm043_flash, | |
54df5268 SH |
139 | }; |
140 | ||
8f5260c8 | 141 | static iomux_v3_cfg_t pcm043_pads[] = { |
54df5268 SH |
142 | /* UART1 */ |
143 | MX35_PAD_CTS1__UART1_CTS, | |
144 | MX35_PAD_RTS1__UART1_RTS, | |
145 | MX35_PAD_TXD1__UART1_TXD_MUX, | |
146 | MX35_PAD_RXD1__UART1_RXD_MUX, | |
147 | /* UART2 */ | |
148 | MX35_PAD_CTS2__UART2_CTS, | |
149 | MX35_PAD_RTS2__UART2_RTS, | |
150 | MX35_PAD_TXD2__UART2_TXD_MUX, | |
151 | MX35_PAD_RXD2__UART2_RXD_MUX, | |
152 | /* FEC */ | |
153 | MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, | |
154 | MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, | |
155 | MX35_PAD_FEC_RX_DV__FEC_RX_DV, | |
156 | MX35_PAD_FEC_COL__FEC_COL, | |
157 | MX35_PAD_FEC_RDATA0__FEC_RDATA_0, | |
158 | MX35_PAD_FEC_TDATA0__FEC_TDATA_0, | |
159 | MX35_PAD_FEC_TX_EN__FEC_TX_EN, | |
160 | MX35_PAD_FEC_MDC__FEC_MDC, | |
161 | MX35_PAD_FEC_MDIO__FEC_MDIO, | |
162 | MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, | |
163 | MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, | |
164 | MX35_PAD_FEC_CRS__FEC_CRS, | |
165 | MX35_PAD_FEC_RDATA1__FEC_RDATA_1, | |
166 | MX35_PAD_FEC_TDATA1__FEC_TDATA_1, | |
167 | MX35_PAD_FEC_RDATA2__FEC_RDATA_2, | |
168 | MX35_PAD_FEC_TDATA2__FEC_TDATA_2, | |
169 | MX35_PAD_FEC_RDATA3__FEC_RDATA_3, | |
170 | MX35_PAD_FEC_TDATA3__FEC_TDATA_3, | |
171 | /* I2C1 */ | |
172 | MX35_PAD_I2C1_CLK__I2C1_SCL, | |
173 | MX35_PAD_I2C1_DAT__I2C1_SDA, | |
174 | /* Display */ | |
175 | MX35_PAD_LD0__IPU_DISPB_DAT_0, | |
176 | MX35_PAD_LD1__IPU_DISPB_DAT_1, | |
177 | MX35_PAD_LD2__IPU_DISPB_DAT_2, | |
178 | MX35_PAD_LD3__IPU_DISPB_DAT_3, | |
179 | MX35_PAD_LD4__IPU_DISPB_DAT_4, | |
180 | MX35_PAD_LD5__IPU_DISPB_DAT_5, | |
181 | MX35_PAD_LD6__IPU_DISPB_DAT_6, | |
182 | MX35_PAD_LD7__IPU_DISPB_DAT_7, | |
183 | MX35_PAD_LD8__IPU_DISPB_DAT_8, | |
184 | MX35_PAD_LD9__IPU_DISPB_DAT_9, | |
185 | MX35_PAD_LD10__IPU_DISPB_DAT_10, | |
186 | MX35_PAD_LD11__IPU_DISPB_DAT_11, | |
187 | MX35_PAD_LD12__IPU_DISPB_DAT_12, | |
188 | MX35_PAD_LD13__IPU_DISPB_DAT_13, | |
189 | MX35_PAD_LD14__IPU_DISPB_DAT_14, | |
190 | MX35_PAD_LD15__IPU_DISPB_DAT_15, | |
191 | MX35_PAD_LD16__IPU_DISPB_DAT_16, | |
192 | MX35_PAD_LD17__IPU_DISPB_DAT_17, | |
193 | MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC, | |
194 | MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK, | |
195 | MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY, | |
196 | MX35_PAD_CONTRAST__IPU_DISPB_CONTR, | |
197 | MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC, | |
198 | MX35_PAD_D3_REV__IPU_DISPB_D3_REV, | |
199 | MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS, | |
8d5c1ed3 LF |
200 | /* gpio */ |
201 | MX35_PAD_ATA_CS0__GPIO2_6, | |
cb2dc111 SH |
202 | /* USB host */ |
203 | MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR, | |
204 | MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC, | |
d2831d1f SH |
205 | /* SSI */ |
206 | MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS, | |
207 | MX35_PAD_STXD4__AUDMUX_AUD4_TXD, | |
208 | MX35_PAD_SRXD4__AUDMUX_AUD4_RXD, | |
209 | MX35_PAD_SCK4__AUDMUX_AUD4_TXC, | |
da92e42b MKB |
210 | /* CAN2 */ |
211 | MX35_PAD_TX5_RX0__CAN2_TXCAN, | |
212 | MX35_PAD_TX4_RX1__CAN2_RXCAN, | |
9a545943 WS |
213 | /* esdhc */ |
214 | MX35_PAD_SD1_CMD__ESDHC1_CMD, | |
215 | MX35_PAD_SD1_CLK__ESDHC1_CLK, | |
216 | MX35_PAD_SD1_DATA0__ESDHC1_DAT0, | |
217 | MX35_PAD_SD1_DATA1__ESDHC1_DAT1, | |
218 | MX35_PAD_SD1_DATA2__ESDHC1_DAT2, | |
219 | MX35_PAD_SD1_DATA3__ESDHC1_DAT3, | |
d2831d1f SH |
220 | }; |
221 | ||
222 | #define AC97_GPIO_TXFS (1 * 32 + 31) | |
223 | #define AC97_GPIO_TXD (1 * 32 + 28) | |
224 | #define AC97_GPIO_RESET (1 * 32 + 0) | |
225 | ||
226 | static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) | |
227 | { | |
8f5260c8 LW |
228 | iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; |
229 | iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; | |
d2831d1f SH |
230 | int ret; |
231 | ||
232 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); | |
233 | if (ret) { | |
234 | printk("failed to get GPIO_TXFS: %d\n", ret); | |
235 | return; | |
236 | } | |
237 | ||
96f3e256 | 238 | mxc_iomux_v3_setup_pad(txfs_gpio); |
d2831d1f SH |
239 | |
240 | /* warm reset */ | |
241 | gpio_direction_output(AC97_GPIO_TXFS, 1); | |
242 | udelay(2); | |
243 | gpio_set_value(AC97_GPIO_TXFS, 0); | |
244 | ||
245 | gpio_free(AC97_GPIO_TXFS); | |
96f3e256 | 246 | mxc_iomux_v3_setup_pad(txfs); |
d2831d1f SH |
247 | } |
248 | ||
249 | static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) | |
250 | { | |
8f5260c8 LW |
251 | iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; |
252 | iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; | |
253 | iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28; | |
254 | iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; | |
255 | iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; | |
d2831d1f SH |
256 | int ret; |
257 | ||
258 | ret = gpio_request(AC97_GPIO_TXFS, "SSI"); | |
259 | if (ret) | |
260 | goto err1; | |
261 | ||
262 | ret = gpio_request(AC97_GPIO_TXD, "SSI"); | |
263 | if (ret) | |
264 | goto err2; | |
265 | ||
266 | ret = gpio_request(AC97_GPIO_RESET, "SSI"); | |
267 | if (ret) | |
268 | goto err3; | |
269 | ||
96f3e256 LW |
270 | mxc_iomux_v3_setup_pad(txfs_gpio); |
271 | mxc_iomux_v3_setup_pad(txd_gpio); | |
272 | mxc_iomux_v3_setup_pad(reset_gpio); | |
d2831d1f SH |
273 | |
274 | gpio_direction_output(AC97_GPIO_TXFS, 0); | |
275 | gpio_direction_output(AC97_GPIO_TXD, 0); | |
276 | ||
277 | /* cold reset */ | |
278 | gpio_direction_output(AC97_GPIO_RESET, 0); | |
279 | udelay(10); | |
280 | gpio_direction_output(AC97_GPIO_RESET, 1); | |
281 | ||
96f3e256 LW |
282 | mxc_iomux_v3_setup_pad(txd); |
283 | mxc_iomux_v3_setup_pad(txfs); | |
d2831d1f SH |
284 | |
285 | gpio_free(AC97_GPIO_RESET); | |
286 | err3: | |
287 | gpio_free(AC97_GPIO_TXD); | |
288 | err2: | |
289 | gpio_free(AC97_GPIO_TXFS); | |
290 | err1: | |
291 | if (ret) | |
292 | printk("%s failed with %d\n", __func__, ret); | |
293 | mdelay(1); | |
294 | } | |
295 | ||
4697bb92 | 296 | static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = { |
d2831d1f SH |
297 | .ac97_reset = pcm043_ac97_cold_reset, |
298 | .ac97_warm_reset = pcm043_ac97_warm_reset, | |
299 | .flags = IMX_SSI_USE_AC97, | |
54df5268 SH |
300 | }; |
301 | ||
e2611ba4 UKK |
302 | static const struct mxc_nand_platform_data |
303 | pcm037_nand_board_info __initconst = { | |
4f43c2ed SH |
304 | .width = 1, |
305 | .hw_ecc = 1, | |
306 | }; | |
307 | ||
c18e8fa5 | 308 | #if defined(CONFIG_USB_ULPI) |
2d58de28 | 309 | static struct mxc_usbh_platform_data otg_pdata __initdata = { |
cb2dc111 SH |
310 | .portsc = MXC_EHCI_MODE_UTMI, |
311 | .flags = MXC_EHCI_INTERFACE_DIFF_UNI, | |
312 | }; | |
070ed733 | 313 | #endif |
cb2dc111 | 314 | |
2d58de28 | 315 | static const struct mxc_usbh_platform_data usbh1_pdata __initconst = { |
cb2dc111 SH |
316 | .portsc = MXC_EHCI_MODE_SERIAL, |
317 | .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | | |
318 | MXC_EHCI_IPPUE_DOWN, | |
319 | }; | |
320 | ||
9e1dde33 | 321 | static const struct fsl_usb2_platform_data otg_device_pdata __initconst = { |
cb2dc111 SH |
322 | .operating_mode = FSL_USB2_DR_DEVICE, |
323 | .phy_mode = FSL_USB2_PHY_UTMI, | |
324 | }; | |
325 | ||
326 | static int otg_mode_host; | |
327 | ||
328 | static int __init pcm043_otg_mode(char *options) | |
329 | { | |
330 | if (!strcmp(options, "host")) | |
331 | otg_mode_host = 1; | |
332 | else if (!strcmp(options, "device")) | |
333 | otg_mode_host = 0; | |
334 | else | |
335 | pr_info("otg_mode neither \"host\" nor \"device\". " | |
336 | "Defaulting to device\n"); | |
337 | return 0; | |
338 | } | |
339 | __setup("otg_mode=", pcm043_otg_mode); | |
340 | ||
54df5268 SH |
341 | /* |
342 | * Board specific initialization. | |
343 | */ | |
344 | static void __init mxc_board_init(void) | |
345 | { | |
346 | mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads)); | |
347 | ||
d2831d1f SH |
348 | mxc_audmux_v2_configure_port(3, |
349 | MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ | |
350 | MXC_AUDMUX_V2_PTCR_TFSEL(0) | | |
351 | MXC_AUDMUX_V2_PTCR_TFSDIR, | |
352 | MXC_AUDMUX_V2_PDCR_RXDSEL(0)); | |
353 | ||
354 | mxc_audmux_v2_configure_port(0, | |
355 | MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */ | |
356 | MXC_AUDMUX_V2_PTCR_TCSEL(3) | | |
357 | MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */ | |
358 | MXC_AUDMUX_V2_PDCR_RXDSEL(3)); | |
359 | ||
6bd96f3c | 360 | imx35_add_fec(NULL); |
54df5268 | 361 | platform_add_devices(devices, ARRAY_SIZE(devices)); |
742269e2 | 362 | imx35_add_imx2_wdt(NULL); |
54df5268 | 363 | |
6eafde5f | 364 | imx35_add_imx_uart0(&uart_pdata); |
e2611ba4 | 365 | imx35_add_mxc_nand(&pcm037_nand_board_info); |
4697bb92 | 366 | imx35_add_imx_ssi(0, &pcm043_ssi_pdata); |
54df5268 | 367 | |
6eafde5f | 368 | imx35_add_imx_uart1(&uart_pdata); |
54df5268 | 369 | |
54df5268 SH |
370 | i2c_register_board_info(0, pcm043_i2c_devices, |
371 | ARRAY_SIZE(pcm043_i2c_devices)); | |
372 | ||
7cdc8fa7 | 373 | imx35_add_imx_i2c0(&pcm043_i2c0_data); |
54df5268 SH |
374 | |
375 | mxc_register_device(&mx3_ipu, &mx3_ipu_data); | |
376 | mxc_register_device(&mx3_fb, &mx3fb_pdata); | |
cb2dc111 SH |
377 | |
378 | #if defined(CONFIG_USB_ULPI) | |
379 | if (otg_mode_host) { | |
380 | otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, | |
13dd0c97 | 381 | ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); |
cb2dc111 | 382 | |
2d58de28 | 383 | imx35_add_mxc_ehci_otg(&otg_pdata); |
cb2dc111 | 384 | } |
cb2dc111 | 385 | #endif |
070ed733 SH |
386 | imx35_add_mxc_ehci_hs(&usbh1_pdata); |
387 | ||
cb2dc111 | 388 | if (!otg_mode_host) |
9e1dde33 | 389 | imx35_add_fsl_usb2_udc(&otg_device_pdata); |
cb2dc111 | 390 | |
da92e42b | 391 | imx35_add_flexcan1(NULL); |
124bf94a | 392 | imx35_add_sdhci_esdhc_imx(0, NULL); |
54df5268 SH |
393 | } |
394 | ||
395 | static void __init pcm043_timer_init(void) | |
396 | { | |
397 | mx35_clocks_init(); | |
398 | } | |
399 | ||
400 | struct sys_timer pcm043_timer = { | |
401 | .init = pcm043_timer_init, | |
402 | }; | |
403 | ||
404 | MACHINE_START(PCM043, "Phytec Phycore pcm043") | |
405 | /* Maintainer: Pengutronix */ | |
34101237 | 406 | .boot_params = MX3x_PHYS_OFFSET + 0x100, |
cd4a05f9 | 407 | .map_io = mx35_map_io, |
c5aa0ad0 | 408 | .init_irq = mx35_init_irq, |
54df5268 SH |
409 | .init_machine = mxc_board_init, |
410 | .timer = &pcm043_timer, | |
411 | MACHINE_END | |
412 |