[linux-2.6-block.git] / arch / arm / mach-mx3 / mach-pcm037.c

/*
 *  Copyright (C) 2008 Sascha Hauer, Pengutronix
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/smsc911x.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/i2c/at24.h>
#include <linux/delay.h>
#include <linux/spi/spi.h>
#include <linux/irq.h>
#include <linux/fsl_devices.h>
#include <linux/can/platform/sja1000.h>

#include <media/soc_camera.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/board-pcm037.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/i2c.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/ipu.h>
#include <mach/mmc.h>
#include <mach/mx3_camera.h>
#include <mach/mx3fb.h>
#include <mach/mxc_nand.h>

#include "devices.h"
#include "pcm037.h"

static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;

static int __init pcm037_variant_setup(char *str)
{
	if (!strcmp("eet", str))
		pcm037_instance = PCM037_EET;
	else if (strcmp("pcm970", str))
		pr_warning("Unknown pcm037 baseboard variant %s\n", str);

	return 1;
}

/* Supported values: "pcm970" (default) and "eet" */
__setup("pcm037_variant=", pcm037_variant_setup);

enum pcm037_board_variant pcm037_variant(void)
{
	return pcm037_instance;
}

/* UART1 with RTS/CTS handshake signals */
static unsigned int pcm037_uart1_handshake_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
};

/* UART1 without RTS/CTS handshake signals */
static unsigned int pcm037_uart1_pins[] = {
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1,
};

static unsigned int pcm037_pins[] = {
	/* I2C */
	MX31_PIN_CSPI2_MOSI__SCL,
	MX31_PIN_CSPI2_MISO__SDA,
	MX31_PIN_CSPI2_SS2__I2C3_SDA,
	MX31_PIN_CSPI2_SCLK__I2C3_SCL,
	/* SDHC1 */
	MX31_PIN_SD1_DATA3__SD1_DATA3,
	MX31_PIN_SD1_DATA2__SD1_DATA2,
	MX31_PIN_SD1_DATA1__SD1_DATA1,
	MX31_PIN_SD1_DATA0__SD1_DATA0,
	MX31_PIN_SD1_CLK__SD1_CLK,
	MX31_PIN_SD1_CMD__SD1_CMD,
	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
	/* SPI1 */
	MX31_PIN_CSPI1_MOSI__MOSI,
	MX31_PIN_CSPI1_MISO__MISO,
	MX31_PIN_CSPI1_SCLK__SCLK,
	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	MX31_PIN_CSPI1_SS0__SS0,
	MX31_PIN_CSPI1_SS1__SS1,
	MX31_PIN_CSPI1_SS2__SS2,
	/* UART2 */
	MX31_PIN_TXD2__TXD2,
	MX31_PIN_RXD2__RXD2,
	MX31_PIN_CTS2__CTS2,
	MX31_PIN_RTS2__RTS2,
	/* UART3 */
	MX31_PIN_CSPI3_MOSI__RXD3,
	MX31_PIN_CSPI3_MISO__TXD3,
	MX31_PIN_CSPI3_SCLK__RTS3,
	MX31_PIN_CSPI3_SPI_RDY__CTS3,
	/* LAN9217 irq pin */
	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
	/* Onewire */
	MX31_PIN_BATT_LINE__OWIRE,
	/* Framebuffer */
	MX31_PIN_LD0__LD0,
	MX31_PIN_LD1__LD1,
	MX31_PIN_LD2__LD2,
	MX31_PIN_LD3__LD3,
	MX31_PIN_LD4__LD4,
	MX31_PIN_LD5__LD5,
	MX31_PIN_LD6__LD6,
	MX31_PIN_LD7__LD7,
	MX31_PIN_LD8__LD8,
	MX31_PIN_LD9__LD9,
	MX31_PIN_LD10__LD10,
	MX31_PIN_LD11__LD11,
	MX31_PIN_LD12__LD12,
	MX31_PIN_LD13__LD13,
	MX31_PIN_LD14__LD14,
	MX31_PIN_LD15__LD15,
	MX31_PIN_LD16__LD16,
	MX31_PIN_LD17__LD17,
	MX31_PIN_VSYNC3__VSYNC3,
	MX31_PIN_HSYNC__HSYNC,
	MX31_PIN_FPSHIFT__FPSHIFT,
	MX31_PIN_DRDY0__DRDY0,
	MX31_PIN_D3_REV__D3_REV,
	MX31_PIN_CONTRAST__CONTRAST,
	MX31_PIN_D3_SPL__D3_SPL,
	MX31_PIN_D3_CLS__D3_CLS,
	MX31_PIN_LCS0__GPI03_23,
	/* CSI */
	IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
	MX31_PIN_CSI_D6__CSI_D6,
	MX31_PIN_CSI_D7__CSI_D7,
	MX31_PIN_CSI_D8__CSI_D8,
	MX31_PIN_CSI_D9__CSI_D9,
	MX31_PIN_CSI_D10__CSI_D10,
	MX31_PIN_CSI_D11__CSI_D11,
	MX31_PIN_CSI_D12__CSI_D12,
	MX31_PIN_CSI_D13__CSI_D13,
	MX31_PIN_CSI_D14__CSI_D14,
	MX31_PIN_CSI_D15__CSI_D15,
	MX31_PIN_CSI_HSYNC__CSI_HSYNC,
	MX31_PIN_CSI_MCLK__CSI_MCLK,
	MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
	MX31_PIN_CSI_VSYNC__CSI_VSYNC,
	/* GPIO */
	IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
};

static struct physmap_flash_data pcm037_flash_data = {
	.width  = 2,
};

static struct resource pcm037_flash_resource = {
	.start	= 0xa0000000,
	.end	= 0xa1ffffff,
	.flags	= IORESOURCE_MEM,
};

static int usbotg_pins[] = {
	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	MX31_PIN_USBOTG_STP__USBOTG_STP,
};

/* USB OTG HS port */
static int __init gpio_usbotg_hs_activate(void)
{
	int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
					ARRAY_SIZE(usbotg_pins), "usbotg");

	if (ret < 0) {
		printk(KERN_ERR "Cannot set up OTG pins\n");
		return ret;
	}

	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);
	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP,   PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST);

	return 0;
}

/* OTG config */
static struct fsl_usb2_platform_data usb_pdata = {
	.operating_mode	= FSL_USB2_DR_DEVICE,
	.phy_mode	= FSL_USB2_PHY_ULPI,
};

static struct platform_device pcm037_flash = {
	.name	= "physmap-flash",
	.id	= 0,
	.dev	= {
		.platform_data  = &pcm037_flash_data,
	},
	.resource = &pcm037_flash_resource,
	.num_resources = 1,
};

static struct imxuart_platform_data uart_pdata = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static struct resource smsc911x_resources[] = {
	{
		.start		= MX31_CS1_BASE_ADDR + 0x300,
		.end		= MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
		.flags		= IORESOURCE_MEM,
	}, {
		.start		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
		.end		= IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
		.flags		= IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
	},
};

static struct smsc911x_platform_config smsc911x_info = {
	.flags		= SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
			  SMSC911X_SAVE_MAC_ADDRESS,
	.irq_polarity	= SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	.irq_type	= SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	.phy_interface	= PHY_INTERFACE_MODE_MII,
};

static struct platform_device pcm037_eth = {
	.name		= "smsc911x",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(smsc911x_resources),
	.resource	= smsc911x_resources,
	.dev		= {
		.platform_data = &smsc911x_info,
	},
};

static struct platdata_mtd_ram pcm038_sram_data = {
	.bankwidth = 2,
};

static struct resource pcm038_sram_resource = {
	.start = MX31_CS4_BASE_ADDR,
	.end   = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
	.flags = IORESOURCE_MEM,
};

static struct platform_device pcm037_sram_device = {
	.name = "mtd-ram",
	.id = 0,
	.dev = {
		.platform_data = &pcm038_sram_data,
	},
	.num_resources = 1,
	.resource = &pcm038_sram_resource,
};

static struct mxc_nand_platform_data pcm037_nand_board_info = {
	.width = 1,
	.hw_ecc = 1,
};

static struct imxi2c_platform_data pcm037_i2c_1_data = {
	.bitrate = 100000,
};

static struct imxi2c_platform_data pcm037_i2c_2_data = {
	.bitrate = 20000,
};

static struct at24_platform_data board_eeprom = {
	.byte_len = 4096,
	.page_size = 32,
	.flags = AT24_FLAG_ADDR16,
};

static int pcm037_camera_power(struct device *dev, int on)
{
	/* disable or enable the camera in X7 or X8 PCM970 connector */
	gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
	return 0;
}

static struct i2c_board_info pcm037_i2c_camera[] = {
	{
		I2C_BOARD_INFO("mt9t031", 0x5d),
	}, {
		I2C_BOARD_INFO("mt9v022", 0x48),
	},
};

static struct soc_camera_link iclink_mt9v022 = {
	.bus_id		= 0,		/* Must match with the camera ID */
	.board_info	= &pcm037_i2c_camera[1],
	.i2c_adapter_id	= 2,
	.module_name	= "mt9v022",
};

static struct soc_camera_link iclink_mt9t031 = {
	.bus_id		= 0,		/* Must match with the camera ID */
	.power		= pcm037_camera_power,
	.board_info	= &pcm037_i2c_camera[0],
	.i2c_adapter_id	= 2,
	.module_name	= "mt9t031",
};

static struct i2c_board_info pcm037_i2c_devices[] = {
	{
		I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
		.platform_data = &board_eeprom,
	}, {
		I2C_BOARD_INFO("pcf8563", 0x51),
	}
};

static struct platform_device pcm037_mt9t031 = {
	.name	= "soc-camera-pdrv",
	.id	= 0,
	.dev	= {
		.platform_data = &iclink_mt9t031,
	},
};

static struct platform_device pcm037_mt9v022 = {
	.name	= "soc-camera-pdrv",
	.id	= 1,
	.dev	= {
		.platform_data = &iclink_mt9v022,
	},
};

/* Not connected by default */
#ifdef PCM970_SDHC_RW_SWITCH
static int pcm970_sdhc1_get_ro(struct device *dev)
{
	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
}
#endif

#define SDHC1_GPIO_WP	IOMUX_TO_GPIO(MX31_PIN_SFS6)
#define SDHC1_GPIO_DET	IOMUX_TO_GPIO(MX31_PIN_SCK6)

static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
		void *data)
{
	int ret;

	ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
	if (ret)
		return ret;

	gpio_direction_input(SDHC1_GPIO_DET);

#ifdef PCM970_SDHC_RW_SWITCH
	ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
	if (ret)
		goto err_gpio_free;
	gpio_direction_input(SDHC1_GPIO_WP);
#endif

	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
			IRQF_DISABLED | IRQF_TRIGGER_FALLING,
				"sdhc-detect", data);
	if (ret)
		goto err_gpio_free_2;

	return 0;

err_gpio_free_2:
#ifdef PCM970_SDHC_RW_SWITCH
	gpio_free(SDHC1_GPIO_WP);
err_gpio_free:
#endif
	gpio_free(SDHC1_GPIO_DET);

	return ret;
}

static void pcm970_sdhc1_exit(struct device *dev, void *data)
{
	free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
	gpio_free(SDHC1_GPIO_DET);
	gpio_free(SDHC1_GPIO_WP);
}

static struct imxmmc_platform_data sdhc_pdata = {
#ifdef PCM970_SDHC_RW_SWITCH
	.get_ro = pcm970_sdhc1_get_ro,
#endif
	.init = pcm970_sdhc1_init,
	.exit = pcm970_sdhc1_exit,
};

struct mx3_camera_pdata camera_pdata = {
	.dma_dev	= &mx3_ipu.dev,
	.flags		= MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
	.mclk_10khz	= 2000,
};

static int __init pcm037_camera_alloc_dma(const size_t buf_size)
{
	dma_addr_t dma_handle;
	void *buf;
	int dma;

	if (buf_size < 2 * 1024 * 1024)
		return -EINVAL;

	buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
	if (!buf) {
		pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
		return -ENOMEM;
	}

	memset(buf, 0, buf_size);

	dma = dma_declare_coherent_memory(&mx3_camera.dev,
					dma_handle, dma_handle, buf_size,
					DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);

	/* The way we call dma_declare_coherent_memory only a malloc can fail */
	return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
}

static struct platform_device *devices[] __initdata = {
	&pcm037_flash,
	&pcm037_sram_device,
	&pcm037_mt9t031,
	&pcm037_mt9v022,
};

static struct ipu_platform_data mx3_ipu_data = {
	.irq_base = MXC_IPU_IRQ_START,
};

static const struct fb_videomode fb_modedb[] = {
	{
		/* 240x320 @ 60 Hz Sharp */
		.name		= "Sharp-LQ035Q7DH06-QVGA",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
				  FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "TX090",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 38255,
		.left_margin	= 144,
		.right_margin	= 0,
		.upper_margin	= 7,
		.lower_margin	= 40,
		.hsync_len	= 96,
		.vsync_len	= 1,
		.sync		= FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	}, {
		/* 240x320 @ 60 Hz */
		.name		= "CMEL-OLED",
		.refresh	= 60,
		.xres		= 240,
		.yres		= 320,
		.pixclock	= 185925,
		.left_margin	= 9,
		.right_margin	= 16,
		.upper_margin	= 7,
		.lower_margin	= 9,
		.hsync_len	= 1,
		.vsync_len	= 1,
		.sync		= FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
		.vmode		= FB_VMODE_NONINTERLACED,
		.flag		= 0,
	},
};

static struct mx3fb_platform_data mx3fb_pdata = {
	.dma_dev	= &mx3_ipu.dev,
	.name		= "Sharp-LQ035Q7DH06-QVGA",
	.mode		= fb_modedb,
	.num_modes	= ARRAY_SIZE(fb_modedb),
};

static struct resource pcm970_sja1000_resources[] = {
	{
		.start   = MX31_CS5_BASE_ADDR,
		.end     = MX31_CS5_BASE_ADDR + 0x100 - 1,
		.flags   = IORESOURCE_MEM,
	}, {
		.start   = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
		.end     = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
		.flags   = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
	},
};

struct sja1000_platform_data pcm970_sja1000_platform_data = {
	.clock		= 16000000 / 2,
	.ocr		= 0x40 | 0x18,
	.cdr		= 0x40,
};

static struct platform_device pcm970_sja1000 = {
	.name = "sja1000_platform",
	.dev = {
		.platform_data = &pcm970_sja1000_platform_data,
	},
	.resource = pcm970_sja1000_resources,
	.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
};

/*
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	int ret;

	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
			"pcm037");

	if (pcm037_variant() == PCM037_EET)
		mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
			ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
	else
		mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
			ARRAY_SIZE(pcm037_uart1_handshake_pins),
			"pcm037_uart1");

	platform_add_devices(devices, ARRAY_SIZE(devices));

	mxc_register_device(&mxc_uart_device0, &uart_pdata);
	mxc_register_device(&mxc_uart_device1, &uart_pdata);
	mxc_register_device(&mxc_uart_device2, &uart_pdata);

	mxc_register_device(&mxc_w1_master_device, NULL);

	/* LAN9217 IRQ pin */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
	if (ret)
		pr_warning("could not get LAN irq gpio\n");
	else {
		gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
		platform_device_register(&pcm037_eth);
	}


	/* I2C adapters and devices */
	i2c_register_board_info(1, pcm037_i2c_devices,
			ARRAY_SIZE(pcm037_i2c_devices));

	mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
	mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);

	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
	mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
	mxc_register_device(&mx3_fb, &mx3fb_pdata);
	if (!gpio_usbotg_hs_activate())
		mxc_register_device(&mxc_otg_udc_device, &usb_pdata);

	/* CSI */
	/* Camera power: default - off */
	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
	if (!ret)
		gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
	else
		iclink_mt9t031.power = NULL;

	if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
		mxc_register_device(&mx3_camera, &camera_pdata);

	platform_device_register(&pcm970_sja1000);
}

static void __init pcm037_timer_init(void)
{
	mx31_clocks_init(26000000);
}

struct sys_timer pcm037_timer = {
	.init	= pcm037_timer_init,
};

MACHINE_START(PCM037, "Phytec Phycore pcm037")
	/* Maintainer: Pengutronix */
	.phys_io	= MX31_AIPS1_BASE_ADDR,
	.io_pg_offst	= (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31_map_io,
	.init_irq       = mx31_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &pcm037_timer,
MACHINE_END
Commit	Line	Data
ce8ffef0 SH	1	/*
	2	* Copyright (C) 2008 Sascha Hauer, Pengutronix
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	17	*/
	18
	19	#include <linux/types.h>
	20	#include <linux/init.h>
32c1ad9a	21	#include <linux/dma-mapping.h>
ce8ffef0 SH	22	#include <linux/platform_device.h>
ce8ffef0 SH	23	#include <linux/mtd/physmap.h>
3dad21a9	24	#include <linux/mtd/plat-ram.h>
ce8ffef0	25	#include <linux/memory.h>
ba54b958	26	#include <linux/gpio.h>
4353318e	27	#include <linux/smsc911x.h>
ba54b958	28	#include <linux/interrupt.h>
79206750 SH	29	#include <linux/i2c.h>
79206750 SH	30	#include <linux/i2c/at24.h>
dddd4a49 SH	31	#include <linux/delay.h>
	32	#include <linux/spi/spi.h>
	33	#include <linux/irq.h>
eb05bbeb	34	#include <linux/fsl_devices.h>
91bf9a25	35	#include <linux/can/platform/sja1000.h>
ce8ffef0	36
32c1ad9a GL	37	#include <media/soc_camera.h>
32c1ad9a GL	38
ce8ffef0 SH	39	#include <asm/mach-types.h>
	40	#include <asm/mach/arch.h>
	41	#include <asm/mach/time.h>
	42	#include <asm/mach/map.h>
32c1ad9a	43	#include <mach/board-pcm037.h>
a09e64fb	44	#include <mach/common.h>
32c1ad9a GL	45	#include <mach/hardware.h>
32c1ad9a GL	46	#include <mach/i2c.h>
a09e64fb RK	47	#include <mach/imx-uart.h>
a09e64fb RK	48	#include <mach/iomux-mx3.h>
a8df0ee8	49	#include <mach/ipu.h>
32c1ad9a GL	50	#include <mach/mmc.h>
32c1ad9a GL	51	#include <mach/mx3_camera.h>
a8df0ee8	52	#include <mach/mx3fb.h>
3287abbd	53	#include <mach/mxc_nand.h>
ce8ffef0	54
5cf09421	55	#include "devices.h"
574ec547 GL	56	#include "pcm037.h"
	57
	58	static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
	59
	60	static int __init pcm037_variant_setup(char *str)
	61	{
	62	if (!strcmp("eet", str))
	63	pcm037_instance = PCM037_EET;
	64	else if (strcmp("pcm970", str))
	65	pr_warning("Unknown pcm037 baseboard variant %s\n", str);
	66
	67	return 1;
	68	}
	69
	70	/* Supported values: "pcm970" (default) and "eet" */
	71	__setup("pcm037_variant=", pcm037_variant_setup);
	72
	73	enum pcm037_board_variant pcm037_variant(void)
	74	{
	75	return pcm037_instance;
	76	}
	77
	78	/* UART1 with RTS/CTS handshake signals */
	79	static unsigned int pcm037_uart1_handshake_pins[] = {
	80	MX31_PIN_CTS1__CTS1,
	81	MX31_PIN_RTS1__RTS1,
	82	MX31_PIN_TXD1__TXD1,
	83	MX31_PIN_RXD1__RXD1,
	84	};
	85
	86	/* UART1 without RTS/CTS handshake signals */
	87	static unsigned int pcm037_uart1_pins[] = {
	88	MX31_PIN_TXD1__TXD1,
	89	MX31_PIN_RXD1__RXD1,
	90	};
5cf09421	91
01ac7d58 SH	92	static unsigned int pcm037_pins[] = {
	93	/* I2C */
	94	MX31_PIN_CSPI2_MOSI__SCL,
	95	MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a GL	96	MX31_PIN_CSPI2_SS2__I2C3_SDA,
32c1ad9a GL	97	MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58 SH	98	/* SDHC1 */
	99	MX31_PIN_SD1_DATA3__SD1_DATA3,
	100	MX31_PIN_SD1_DATA2__SD1_DATA2,
	101	MX31_PIN_SD1_DATA1__SD1_DATA1,
	102	MX31_PIN_SD1_DATA0__SD1_DATA0,
	103	MX31_PIN_SD1_CLK__SD1_CLK,
	104	MX31_PIN_SD1_CMD__SD1_CMD,
	105	IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
	106	IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
	107	/* SPI1 */
	108	MX31_PIN_CSPI1_MOSI__MOSI,
	109	MX31_PIN_CSPI1_MISO__MISO,
	110	MX31_PIN_CSPI1_SCLK__SCLK,
	111	MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
	112	MX31_PIN_CSPI1_SS0__SS0,
	113	MX31_PIN_CSPI1_SS1__SS1,
	114	MX31_PIN_CSPI1_SS2__SS2,
01ac7d58 SH	115	/* UART2 */
	116	MX31_PIN_TXD2__TXD2,
	117	MX31_PIN_RXD2__RXD2,
	118	MX31_PIN_CTS2__CTS2,
	119	MX31_PIN_RTS2__RTS2,
	120	/* UART3 */
	121	MX31_PIN_CSPI3_MOSI__RXD3,
	122	MX31_PIN_CSPI3_MISO__TXD3,
	123	MX31_PIN_CSPI3_SCLK__RTS3,
	124	MX31_PIN_CSPI3_SPI_RDY__CTS3,
	125	/* LAN9217 irq pin */
	126	IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
	127	/* Onewire */
	128	MX31_PIN_BATT_LINE__OWIRE,
	129	/* Framebuffer */
	130	MX31_PIN_LD0__LD0,
	131	MX31_PIN_LD1__LD1,
	132	MX31_PIN_LD2__LD2,
	133	MX31_PIN_LD3__LD3,
	134	MX31_PIN_LD4__LD4,
	135	MX31_PIN_LD5__LD5,
	136	MX31_PIN_LD6__LD6,
	137	MX31_PIN_LD7__LD7,
	138	MX31_PIN_LD8__LD8,
	139	MX31_PIN_LD9__LD9,
	140	MX31_PIN_LD10__LD10,
	141	MX31_PIN_LD11__LD11,
	142	MX31_PIN_LD12__LD12,
	143	MX31_PIN_LD13__LD13,
	144	MX31_PIN_LD14__LD14,
	145	MX31_PIN_LD15__LD15,
	146	MX31_PIN_LD16__LD16,
	147	MX31_PIN_LD17__LD17,
	148	MX31_PIN_VSYNC3__VSYNC3,
	149	MX31_PIN_HSYNC__HSYNC,
	150	MX31_PIN_FPSHIFT__FPSHIFT,
	151	MX31_PIN_DRDY0__DRDY0,
	152	MX31_PIN_D3_REV__D3_REV,
	153	MX31_PIN_CONTRAST__CONTRAST,
	154	MX31_PIN_D3_SPL__D3_SPL,
	155	MX31_PIN_D3_CLS__D3_CLS,
	156	MX31_PIN_LCS0__GPI03_23,
32c1ad9a GL	157	/* CSI */
	158	IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
	159	MX31_PIN_CSI_D6__CSI_D6,
	160	MX31_PIN_CSI_D7__CSI_D7,
	161	MX31_PIN_CSI_D8__CSI_D8,
	162	MX31_PIN_CSI_D9__CSI_D9,
	163	MX31_PIN_CSI_D10__CSI_D10,
	164	MX31_PIN_CSI_D11__CSI_D11,
	165	MX31_PIN_CSI_D12__CSI_D12,
	166	MX31_PIN_CSI_D13__CSI_D13,
	167	MX31_PIN_CSI_D14__CSI_D14,
	168	MX31_PIN_CSI_D15__CSI_D15,
	169	MX31_PIN_CSI_HSYNC__CSI_HSYNC,
	170	MX31_PIN_CSI_MCLK__CSI_MCLK,
	171	MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
	172	MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3 LF	173	/* GPIO */
e0fd4db3 LF	174	IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
01ac7d58 SH	175	};
01ac7d58 SH	176
ce8ffef0 SH	177	static struct physmap_flash_data pcm037_flash_data = {
	178	.width = 2,
	179	};
	180
	181	static struct resource pcm037_flash_resource = {
	182	.start = 0xa0000000,
	183	.end = 0xa1ffffff,
	184	.flags = IORESOURCE_MEM,
	185	};
	186
eb05bbeb GL	187	static int usbotg_pins[] = {
	188	MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
	189	MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
	190	MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
	191	MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
	192	MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
	193	MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
	194	MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
	195	MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
	196	MX31_PIN_USBOTG_CLK__USBOTG_CLK,
	197	MX31_PIN_USBOTG_DIR__USBOTG_DIR,
	198	MX31_PIN_USBOTG_NXT__USBOTG_NXT,
	199	MX31_PIN_USBOTG_STP__USBOTG_STP,
	200	};
	201
	202	/* USB OTG HS port */
	203	static int __init gpio_usbotg_hs_activate(void)
	204	{
	205	int ret = mxc_iomux_setup_multiple_pins(usbotg_pins,
	206	ARRAY_SIZE(usbotg_pins), "usbotg");
	207
	208	if (ret < 0) {
	209	printk(KERN_ERR "Cannot set up OTG pins\n");
	210	return ret;
	211	}
	212
	213	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	214	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	215	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	216	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	217	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	218	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	219	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	220	mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	221	mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	222	mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	223	mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	224	mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, PAD_CTL_DRV_MAX \| PAD_CTL_SRE_FAST);
	225
	226	return 0;
	227	}
	228
	229	/* OTG config */
	230	static struct fsl_usb2_platform_data usb_pdata = {
	231	.operating_mode = FSL_USB2_DR_DEVICE,
	232	.phy_mode = FSL_USB2_PHY_ULPI,
	233	};
	234
ce8ffef0 SH	235	static struct platform_device pcm037_flash = {
	236	.name = "physmap-flash",
	237	.id = 0,
	238	.dev = {
	239	.platform_data = &pcm037_flash_data,
	240	},
	241	.resource = &pcm037_flash_resource,
	242	.num_resources = 1,
	243	};
	244
	245	static struct imxuart_platform_data uart_pdata = {
a9b06233	246	.flags = IMXUART_HAVE_RTSCTS,
ce8ffef0 SH	247	};
ce8ffef0 SH	248
4353318e	249	static struct resource smsc911x_resources[] = {
3f4f54b4	250	{
f568dd7f UKK	251	.start = MX31_CS1_BASE_ADDR + 0x300,
f568dd7f UKK	252	.end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958	253	.flags = IORESOURCE_MEM,
3f4f54b4	254	}, {
ba54b958 GL	255	.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
ba54b958 GL	256	.end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e	257	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWLEVEL,
ba54b958 GL	258	},
	259	};
	260
4353318e SG	261	static struct smsc911x_platform_config smsc911x_info = {
	262	.flags = SMSC911X_USE_32BIT \| SMSC911X_FORCE_INTERNAL_PHY \|
	263	SMSC911X_SAVE_MAC_ADDRESS,
	264	.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
	265	.irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
	266	.phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958 GL	267	};
	268
	269	static struct platform_device pcm037_eth = {
4353318e	270	.name = "smsc911x",
ba54b958	271	.id = -1,
4353318e SG	272	.num_resources = ARRAY_SIZE(smsc911x_resources),
4353318e SG	273	.resource = smsc911x_resources,
ba54b958	274	.dev = {
4353318e	275	.platform_data = &smsc911x_info,
ba54b958 GL	276	},
	277	};
	278
3dad21a9 SH	279	static struct platdata_mtd_ram pcm038_sram_data = {
	280	.bankwidth = 2,
	281	};
	282
	283	static struct resource pcm038_sram_resource = {
f568dd7f UKK	284	.start = MX31_CS4_BASE_ADDR,
f568dd7f UKK	285	.end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9 SH	286	.flags = IORESOURCE_MEM,
	287	};
	288
	289	static struct platform_device pcm037_sram_device = {
	290	.name = "mtd-ram",
	291	.id = 0,
	292	.dev = {
	293	.platform_data = &pcm038_sram_data,
	294	},
	295	.num_resources = 1,
	296	.resource = &pcm038_sram_resource,
	297	};
	298
3287abbd SH	299	static struct mxc_nand_platform_data pcm037_nand_board_info = {
	300	.width = 1,
	301	.hw_ecc = 1,
	302	};
	303
79206750 SH	304	static struct imxi2c_platform_data pcm037_i2c_1_data = {
79206750 SH	305	.bitrate = 100000,
79206750 SH	306	};
79206750 SH	307
32c1ad9a GL	308	static struct imxi2c_platform_data pcm037_i2c_2_data = {
	309	.bitrate = 20000,
	310	};
	311
79206750 SH	312	static struct at24_platform_data board_eeprom = {
	313	.byte_len = 4096,
	314	.page_size = 32,
	315	.flags = AT24_FLAG_ADDR16,
	316	};
	317
32c1ad9a GL	318	static int pcm037_camera_power(struct device *dev, int on)
	319	{
	320	/* disable or enable the camera in X7 or X8 PCM970 connector */
	321	gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
	322	return 0;
	323	}
	324
9d00278d	325	static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a GL	326	{
32c1ad9a GL	327	I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d GL	328	}, {
9d00278d GL	329	I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a GL	330	},
	331	};
	332
9d00278d GL	333	static struct soc_camera_link iclink_mt9v022 = {
	334	.bus_id = 0, /* Must match with the camera ID */
	335	.board_info = &pcm037_i2c_camera[1],
	336	.i2c_adapter_id = 2,
	337	.module_name = "mt9v022",
	338	};
	339
	340	static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a GL	341	.bus_id = 0, /* Must match with the camera ID */
32c1ad9a GL	342	.power = pcm037_camera_power,
9d00278d	343	.board_info = &pcm037_i2c_camera[0],
32c1ad9a GL	344	.i2c_adapter_id = 2,
	345	.module_name = "mt9t031",
	346	};
	347
79206750	348	static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a	349	{
79206750 SH	350	I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
	351	.platform_data = &board_eeprom,
	352	}, {
cf87a6e2	353	I2C_BOARD_INFO("pcf8563", 0x51),
79206750 SH	354	}
79206750 SH	355	};
32c1ad9a	356
9d00278d	357	static struct platform_device pcm037_mt9t031 = {
32c1ad9a GL	358	.name = "soc-camera-pdrv",
	359	.id = 0,
	360	.dev = {
9d00278d GL	361	.platform_data = &iclink_mt9t031,
	362	},
	363	};
	364
	365	static struct platform_device pcm037_mt9v022 = {
	366	.name = "soc-camera-pdrv",
	367	.id = 1,
	368	.dev = {
	369	.platform_data = &iclink_mt9v022,
32c1ad9a GL	370	},
32c1ad9a GL	371	};
79206750	372
dddd4a49 SH	373	/* Not connected by default */
	374	#ifdef PCM970_SDHC_RW_SWITCH
	375	static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f	376	{
dddd4a49 SH	377	return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
	378	}
	379	#endif
	380
4f163eb8 SH	381	#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
	382	#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
	383
dddd4a49 SH	384	static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
	385	void *data)
	386	{
	387	int ret;
dddd4a49	388
4f163eb8 SH	389	ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
	390	if (ret)
	391	return ret;
	392
	393	gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49	394
4f163eb8 SH	395	#ifdef PCM970_SDHC_RW_SWITCH
	396	ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
	397	if (ret)
	398	goto err_gpio_free;
	399	gpio_direction_input(SDHC1_GPIO_WP);
	400	#endif
dddd4a49 SH	401
	402	ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
	403	IRQF_DISABLED \| IRQF_TRIGGER_FALLING,
	404	"sdhc-detect", data);
4f163eb8 SH	405	if (ret)
	406	goto err_gpio_free_2;
	407
	408	return 0;
	409
	410	err_gpio_free_2:
	411	#ifdef PCM970_SDHC_RW_SWITCH
	412	gpio_free(SDHC1_GPIO_WP);
	413	err_gpio_free:
	414	#endif
	415	gpio_free(SDHC1_GPIO_DET);
	416
dddd4a49	417	return ret;
f2cb641f SH	418	}
	419
	420	static void pcm970_sdhc1_exit(struct device dev, void data)
	421	{
dddd4a49	422	free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
4f163eb8 SH	423	gpio_free(SDHC1_GPIO_DET);
4f163eb8 SH	424	gpio_free(SDHC1_GPIO_WP);
f2cb641f SH	425	}
f2cb641f SH	426
f2cb641f	427	static struct imxmmc_platform_data sdhc_pdata = {
dddd4a49 SH	428	#ifdef PCM970_SDHC_RW_SWITCH
	429	.get_ro = pcm970_sdhc1_get_ro,
	430	#endif
f2cb641f SH	431	.init = pcm970_sdhc1_init,
	432	.exit = pcm970_sdhc1_exit,
	433	};
	434
32c1ad9a GL	435	struct mx3_camera_pdata camera_pdata = {
	436	.dma_dev = &mx3_ipu.dev,
	437	.flags = MX3_CAMERA_DATAWIDTH_8 \| MX3_CAMERA_DATAWIDTH_10,
	438	.mclk_10khz = 2000,
	439	};
	440
	441	static int __init pcm037_camera_alloc_dma(const size_t buf_size)
	442	{
	443	dma_addr_t dma_handle;
	444	void *buf;
	445	int dma;
	446
	447	if (buf_size < 2 * 1024 * 1024)
	448	return -EINVAL;
	449
	450	buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
	451	if (!buf) {
	452	pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
	453	return -ENOMEM;
	454	}
	455
	456	memset(buf, 0, buf_size);
	457
	458	dma = dma_declare_coherent_memory(&mx3_camera.dev,
	459	dma_handle, dma_handle, buf_size,
	460	DMA_MEMORY_MAP \| DMA_MEMORY_EXCLUSIVE);
	461
	462	/* The way we call dma_declare_coherent_memory only a malloc can fail */
	463	return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
	464	}
	465
ce8ffef0 SH	466	static struct platform_device *devices[] __initdata = {
ce8ffef0 SH	467	&pcm037_flash,
3dad21a9	468	&pcm037_sram_device,
9d00278d GL	469	&pcm037_mt9t031,
9d00278d GL	470	&pcm037_mt9v022,
ce8ffef0 SH	471	};
ce8ffef0 SH	472
a8df0ee8 GL	473	static struct ipu_platform_data mx3_ipu_data = {
	474	.irq_base = MXC_IPU_IRQ_START,
	475	};
	476
	477	static const struct fb_videomode fb_modedb[] = {
	478	{
	479	/* 240x320 @ 60 Hz Sharp */
	480	.name = "Sharp-LQ035Q7DH06-QVGA",
	481	.refresh = 60,
	482	.xres = 240,
	483	.yres = 320,
	484	.pixclock = 185925,
	485	.left_margin = 9,
	486	.right_margin = 16,
	487	.upper_margin = 7,
	488	.lower_margin = 9,
	489	.hsync_len = 1,
	490	.vsync_len = 1,
	491	.sync = FB_SYNC_HOR_HIGH_ACT \| FB_SYNC_SHARP_MODE \|
	492	FB_SYNC_CLK_INVERT \| FB_SYNC_CLK_IDLE_EN,
	493	.vmode = FB_VMODE_NONINTERLACED,
	494	.flag = 0,
	495	}, {
	496	/* 240x320 @ 60 Hz */
	497	.name = "TX090",
	498	.refresh = 60,
	499	.xres = 240,
	500	.yres = 320,
	501	.pixclock = 38255,
	502	.left_margin = 144,
	503	.right_margin = 0,
	504	.upper_margin = 7,
	505	.lower_margin = 40,
	506	.hsync_len = 96,
	507	.vsync_len = 1,
	508	.sync = FB_SYNC_VERT_HIGH_ACT \| FB_SYNC_OE_ACT_HIGH,
	509	.vmode = FB_VMODE_NONINTERLACED,
	510	.flag = 0,
574ec547 GL	511	}, {
	512	/* 240x320 @ 60 Hz */
	513	.name = "CMEL-OLED",
	514	.refresh = 60,
	515	.xres = 240,
	516	.yres = 320,
	517	.pixclock = 185925,
	518	.left_margin = 9,
	519	.right_margin = 16,
	520	.upper_margin = 7,
	521	.lower_margin = 9,
	522	.hsync_len = 1,
	523	.vsync_len = 1,
	524	.sync = FB_SYNC_OE_ACT_HIGH \| FB_SYNC_CLK_INVERT,
	525	.vmode = FB_VMODE_NONINTERLACED,
	526	.flag = 0,
a8df0ee8 GL	527	},
	528	};
	529
	530	static struct mx3fb_platform_data mx3fb_pdata = {
	531	.dma_dev = &mx3_ipu.dev,
	532	.name = "Sharp-LQ035Q7DH06-QVGA",
	533	.mode = fb_modedb,
	534	.num_modes = ARRAY_SIZE(fb_modedb),
	535	};
	536
91bf9a25 SH	537	static struct resource pcm970_sja1000_resources[] = {
91bf9a25 SH	538	{
f568dd7f UKK	539	.start = MX31_CS5_BASE_ADDR,
f568dd7f UKK	540	.end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25 SH	541	.flags = IORESOURCE_MEM,
	542	}, {
	543	.start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
	544	.end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
	545	.flags = IORESOURCE_IRQ \| IORESOURCE_IRQ_LOWEDGE,
	546	},
	547	};
	548
	549	struct sja1000_platform_data pcm970_sja1000_platform_data = {
	550	.clock = 16000000 / 2,
	551	.ocr = 0x40 \| 0x18,
	552	.cdr = 0x40,
	553	};
	554
	555	static struct platform_device pcm970_sja1000 = {
	556	.name = "sja1000_platform",
	557	.dev = {
	558	.platform_data = &pcm970_sja1000_platform_data,
	559	},
	560	.resource = pcm970_sja1000_resources,
	561	.num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
	562	};
	563
ce8ffef0 SH	564	/*
	565	* Board specific initialization.
	566	*/
	567	static void __init mxc_board_init(void)
	568	{
4f163eb8 SH	569	int ret;
4f163eb8 SH	570
01ac7d58 SH	571	mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
	572	"pcm037");
	573
574ec547 GL	574	if (pcm037_variant() == PCM037_EET)
	575	mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
	576	ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
	577	else
	578	mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
	579	ARRAY_SIZE(pcm037_uart1_handshake_pins),
	580	"pcm037_uart1");
	581
ce8ffef0 SH	582	platform_add_devices(devices, ARRAY_SIZE(devices));
ce8ffef0 SH	583
5cf09421	584	mxc_register_device(&mxc_uart_device0, &uart_pdata);
13e9f612	585	mxc_register_device(&mxc_uart_device1, &uart_pdata);
5cf09421	586	mxc_register_device(&mxc_uart_device2, &uart_pdata);
d517cab1	587
d517cab1	588	mxc_register_device(&mxc_w1_master_device, NULL);
ba54b958	589
f8e5143b	590	/* LAN9217 IRQ pin */
4f163eb8 SH	591	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
	592	if (ret)
	593	pr_warning("could not get LAN irq gpio\n");
	594	else {
	595	gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
	596	platform_device_register(&pcm037_eth);
	597	}
	598
3287abbd	599
32c1ad9a	600	/* I2C adapters and devices */
79206750 SH	601	i2c_register_board_info(1, pcm037_i2c_devices,
	602	ARRAY_SIZE(pcm037_i2c_devices));
	603
	604	mxc_register_device(&mxc_i2c_device1, &pcm037_i2c_1_data);
32c1ad9a GL	605	mxc_register_device(&mxc_i2c_device2, &pcm037_i2c_2_data);
32c1ad9a GL	606
3287abbd	607	mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
f2cb641f	608	mxc_register_device(&mxcsdhc_device0, &sdhc_pdata);
a8df0ee8 GL	609	mxc_register_device(&mx3_ipu, &mx3_ipu_data);
a8df0ee8 GL	610	mxc_register_device(&mx3_fb, &mx3fb_pdata);
eb05bbeb GL	611	if (!gpio_usbotg_hs_activate())
eb05bbeb GL	612	mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
32c1ad9a GL	613
	614	/* CSI */
	615	/* Camera power: default - off */
	616	ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
	617	if (!ret)
	618	gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
	619	else
9d00278d	620	iclink_mt9t031.power = NULL;
32c1ad9a GL	621
	622	if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
	623	mxc_register_device(&mx3_camera, &camera_pdata);
91bf9a25 SH	624
91bf9a25 SH	625	platform_device_register(&pcm970_sja1000);
ce8ffef0 SH	626	}
ce8ffef0 SH	627
ce8ffef0 SH	628	static void __init pcm037_timer_init(void)
ce8ffef0 SH	629	{
30c730f8	630	mx31_clocks_init(26000000);
ce8ffef0 SH	631	}
	632
	633	struct sys_timer pcm037_timer = {
	634	.init = pcm037_timer_init,
	635	};
	636
	637	MACHINE_START(PCM037, "Phytec Phycore pcm037")
	638	/* Maintainer: Pengutronix */
f568dd7f	639	.phys_io = MX31_AIPS1_BASE_ADDR,
321ed164	640	.io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
34101237	641	.boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9	642	.map_io = mx31_map_io,
c5aa0ad0	643	.init_irq = mx31_init_irq,
ce8ffef0 SH	644	.init_machine = mxc_board_init,
	645	.timer = &pcm037_timer,
	646	MACHINE_END