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ARM: mx3: dynamically allocate mxc_rnga devices
[linux-2.6-block.git] / arch / arm / mach-mx3 / mach-pcm037.c
CommitLineData
ce8ffef0
SH		 1/*
2 * Copyright (C) 2008 Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
ce8ffef0
SH		 13 */
14
15#include <linux/types.h>
16#include <linux/init.h>
32c1ad9a 17#include <linux/dma-mapping.h>
ce8ffef0
SH		 18#include <linux/platform_device.h>
19#include <linux/mtd/physmap.h>
3dad21a9 20#include <linux/mtd/plat-ram.h>
ce8ffef0 21#include <linux/memory.h>
ba54b958 22#include <linux/gpio.h>
4353318e 23#include <linux/smsc911x.h>
ba54b958 24#include <linux/interrupt.h>
79206750
SH		 25#include <linux/i2c.h>
26#include <linux/i2c/at24.h>
dddd4a49
SH		 27#include <linux/delay.h>
28#include <linux/spi/spi.h>
29#include <linux/irq.h>
eb05bbeb 30#include <linux/fsl_devices.h>
91bf9a25 31#include <linux/can/platform/sja1000.h>
ee14373c
SH		 32#include <linux/usb/otg.h>
33#include <linux/usb/ulpi.h>
5a0e3ad6 34#include <linux/gfp.h>
ce8ffef0 35
32c1ad9a
GL		 36#include <media/soc_camera.h>
37
ce8ffef0
SH		 38#include <asm/mach-types.h>
39#include <asm/mach/arch.h>
40#include <asm/mach/time.h>
41#include <asm/mach/map.h>
a09e64fb 42#include <mach/common.h>
32c1ad9a 43#include <mach/hardware.h>
a09e64fb 44#include <mach/iomux-mx3.h>
a8df0ee8 45#include <mach/ipu.h>
32c1ad9a 46#include <mach/mx3_camera.h>
a8df0ee8 47#include <mach/mx3fb.h>
ee14373c
SH		 48#include <mach/mxc_ehci.h>
49#include <mach/ulpi.h>
ce8ffef0 50
a2ceeef5 51#include "devices-imx31.h"
5cf09421 52#include "devices.h"
574ec547
GL		 53#include "pcm037.h"
54
55static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
56
57static int __init pcm037_variant_setup(char *str)
58{
59 if (!strcmp("eet", str))
60 pcm037_instance = PCM037_EET;
61 else if (strcmp("pcm970", str))
62 pr_warning("Unknown pcm037 baseboard variant %s\n", str);
63
64 return 1;
65}
66
67/* Supported values: "pcm970" (default) and "eet" */
68__setup("pcm037_variant=", pcm037_variant_setup);
69
70enum pcm037_board_variant pcm037_variant(void)
71{
72 return pcm037_instance;
73}
74
75/* UART1 with RTS/CTS handshake signals */
76static unsigned int pcm037_uart1_handshake_pins[] = {
77 MX31_PIN_CTS1__CTS1,
78 MX31_PIN_RTS1__RTS1,
79 MX31_PIN_TXD1__TXD1,
80 MX31_PIN_RXD1__RXD1,
81};
82
83/* UART1 without RTS/CTS handshake signals */
84static unsigned int pcm037_uart1_pins[] = {
85 MX31_PIN_TXD1__TXD1,
86 MX31_PIN_RXD1__RXD1,
87};
5cf09421 88
01ac7d58
SH		 89static unsigned int pcm037_pins[] = {
90 /* I2C */
91 MX31_PIN_CSPI2_MOSI__SCL,
92 MX31_PIN_CSPI2_MISO__SDA,
32c1ad9a
GL		 93 MX31_PIN_CSPI2_SS2__I2C3_SDA,
94 MX31_PIN_CSPI2_SCLK__I2C3_SCL,
01ac7d58
SH		 95 /* SDHC1 */
96 MX31_PIN_SD1_DATA3__SD1_DATA3,
97 MX31_PIN_SD1_DATA2__SD1_DATA2,
98 MX31_PIN_SD1_DATA1__SD1_DATA1,
99 MX31_PIN_SD1_DATA0__SD1_DATA0,
100 MX31_PIN_SD1_CLK__SD1_CLK,
101 MX31_PIN_SD1_CMD__SD1_CMD,
102 IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
103 IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
104 /* SPI1 */
105 MX31_PIN_CSPI1_MOSI__MOSI,
106 MX31_PIN_CSPI1_MISO__MISO,
107 MX31_PIN_CSPI1_SCLK__SCLK,
108 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
109 MX31_PIN_CSPI1_SS0__SS0,
110 MX31_PIN_CSPI1_SS1__SS1,
111 MX31_PIN_CSPI1_SS2__SS2,
01ac7d58
SH		 112 /* UART2 */
113 MX31_PIN_TXD2__TXD2,
114 MX31_PIN_RXD2__RXD2,
115 MX31_PIN_CTS2__CTS2,
116 MX31_PIN_RTS2__RTS2,
117 /* UART3 */
118 MX31_PIN_CSPI3_MOSI__RXD3,
119 MX31_PIN_CSPI3_MISO__TXD3,
120 MX31_PIN_CSPI3_SCLK__RTS3,
121 MX31_PIN_CSPI3_SPI_RDY__CTS3,
122 /* LAN9217 irq pin */
123 IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
124 /* Onewire */
125 MX31_PIN_BATT_LINE__OWIRE,
126 /* Framebuffer */
127 MX31_PIN_LD0__LD0,
128 MX31_PIN_LD1__LD1,
129 MX31_PIN_LD2__LD2,
130 MX31_PIN_LD3__LD3,
131 MX31_PIN_LD4__LD4,
132 MX31_PIN_LD5__LD5,
133 MX31_PIN_LD6__LD6,
134 MX31_PIN_LD7__LD7,
135 MX31_PIN_LD8__LD8,
136 MX31_PIN_LD9__LD9,
137 MX31_PIN_LD10__LD10,
138 MX31_PIN_LD11__LD11,
139 MX31_PIN_LD12__LD12,
140 MX31_PIN_LD13__LD13,
141 MX31_PIN_LD14__LD14,
142 MX31_PIN_LD15__LD15,
143 MX31_PIN_LD16__LD16,
144 MX31_PIN_LD17__LD17,
145 MX31_PIN_VSYNC3__VSYNC3,
146 MX31_PIN_HSYNC__HSYNC,
147 MX31_PIN_FPSHIFT__FPSHIFT,
148 MX31_PIN_DRDY0__DRDY0,
149 MX31_PIN_D3_REV__D3_REV,
150 MX31_PIN_CONTRAST__CONTRAST,
151 MX31_PIN_D3_SPL__D3_SPL,
152 MX31_PIN_D3_CLS__D3_CLS,
153 MX31_PIN_LCS0__GPI03_23,
32c1ad9a
GL		 154 /* CSI */
155 IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
156 MX31_PIN_CSI_D6__CSI_D6,
157 MX31_PIN_CSI_D7__CSI_D7,
158 MX31_PIN_CSI_D8__CSI_D8,
159 MX31_PIN_CSI_D9__CSI_D9,
160 MX31_PIN_CSI_D10__CSI_D10,
161 MX31_PIN_CSI_D11__CSI_D11,
162 MX31_PIN_CSI_D12__CSI_D12,
163 MX31_PIN_CSI_D13__CSI_D13,
164 MX31_PIN_CSI_D14__CSI_D14,
165 MX31_PIN_CSI_D15__CSI_D15,
166 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
167 MX31_PIN_CSI_MCLK__CSI_MCLK,
168 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
169 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
e0fd4db3
LF		 170 /* GPIO */
171 IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
ee14373c 172 /* OTG */
eb05bbeb
GL		 173 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
174 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
175 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
176 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
177 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
178 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
179 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
180 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
181 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
182 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
183 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
184 MX31_PIN_USBOTG_STP__USBOTG_STP,
ee14373c
SH		 185 /* USB host 2 */
186 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
187 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
188 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
189 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
190 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
191 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
192 IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
193 IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
194 IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
195 IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
196 IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
197 IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
eb05bbeb
GL		 198};
199
ee14373c
SH		 200static struct physmap_flash_data pcm037_flash_data = {
201 .width = 2,
202};
eb05bbeb 203
ee14373c
SH		 204static struct resource pcm037_flash_resource = {
205 .start = 0xa0000000,
206 .end = 0xa1ffffff,
207 .flags = IORESOURCE_MEM,
eb05bbeb
GL		 208};
209
ce8ffef0
SH		 210static struct platform_device pcm037_flash = {
211 .name = "physmap-flash",
212 .id = 0,
213 .dev = {
214 .platform_data = &pcm037_flash_data,
215 },
216 .resource = &pcm037_flash_resource,
217 .num_resources = 1,
218};
219
16cf5c41 220static const struct imxuart_platform_data uart_pdata __initconst = {
a9b06233 221 .flags = IMXUART_HAVE_RTSCTS,
ce8ffef0
SH		 222};
223
4353318e 224static struct resource smsc911x_resources[] = {
3f4f54b4 225 {
f568dd7f
UKK		 226 .start = MX31_CS1_BASE_ADDR + 0x300,
227 .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
ba54b958 228 .flags = IORESOURCE_MEM,
3f4f54b4 229 }, {
ba54b958
GL		 230 .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
231 .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
4353318e 232 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
ba54b958
GL		 233 },
234};
235
4353318e
SG		 236static struct smsc911x_platform_config smsc911x_info = {
237 .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
238 SMSC911X_SAVE_MAC_ADDRESS,
239 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
240 .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
241 .phy_interface = PHY_INTERFACE_MODE_MII,
ba54b958
GL		 242};
243
244static struct platform_device pcm037_eth = {
4353318e 245 .name = "smsc911x",
ba54b958 246 .id = -1,
4353318e
SG		 247 .num_resources = ARRAY_SIZE(smsc911x_resources),
248 .resource = smsc911x_resources,
ba54b958 249 .dev = {
4353318e 250 .platform_data = &smsc911x_info,
ba54b958
GL		 251 },
252};
253
3dad21a9
SH		 254static struct platdata_mtd_ram pcm038_sram_data = {
255 .bankwidth = 2,
256};
257
258static struct resource pcm038_sram_resource = {
f568dd7f
UKK		 259 .start = MX31_CS4_BASE_ADDR,
260 .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
3dad21a9
SH		 261 .flags = IORESOURCE_MEM,
262};
263
264static struct platform_device pcm037_sram_device = {
265 .name = "mtd-ram",
266 .id = 0,
267 .dev = {
268 .platform_data = &pcm038_sram_data,
269 },
270 .num_resources = 1,
271 .resource = &pcm038_sram_resource,
272};
273
a2ceeef5
UKK		 274static const struct mxc_nand_platform_data
275pcm037_nand_board_info __initconst = {
3287abbd
SH		 276 .width = 1,
277 .hw_ecc = 1,
278};
279
4a9b8b0b 280static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
79206750 281 .bitrate = 100000,
79206750
SH		 282};
283
4a9b8b0b 284static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
32c1ad9a
GL		 285 .bitrate = 20000,
286};
287
79206750
SH		 288static struct at24_platform_data board_eeprom = {
289 .byte_len = 4096,
290 .page_size = 32,
291 .flags = AT24_FLAG_ADDR16,
292};
293
32c1ad9a
GL		 294static int pcm037_camera_power(struct device *dev, int on)
295{
296 /* disable or enable the camera in X7 or X8 PCM970 connector */
297 gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
298 return 0;
299}
300
9d00278d 301static struct i2c_board_info pcm037_i2c_camera[] = {
32c1ad9a
GL		 302 {
303 I2C_BOARD_INFO("mt9t031", 0x5d),
9d00278d
GL		 304 }, {
305 I2C_BOARD_INFO("mt9v022", 0x48),
32c1ad9a
GL		 306 },
307};
308
9d00278d
GL		 309static struct soc_camera_link iclink_mt9v022 = {
310 .bus_id = 0, /* Must match with the camera ID */
311 .board_info = &pcm037_i2c_camera[1],
312 .i2c_adapter_id = 2,
313 .module_name = "mt9v022",
314};
315
316static struct soc_camera_link iclink_mt9t031 = {
32c1ad9a
GL		 317 .bus_id = 0, /* Must match with the camera ID */
318 .power = pcm037_camera_power,
9d00278d 319 .board_info = &pcm037_i2c_camera[0],
32c1ad9a
GL		 320 .i2c_adapter_id = 2,
321 .module_name = "mt9t031",
322};
323
79206750 324static struct i2c_board_info pcm037_i2c_devices[] = {
32c1ad9a 325 {
79206750
SH		 326 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
327 .platform_data = &board_eeprom,
328 }, {
cf87a6e2 329 I2C_BOARD_INFO("pcf8563", 0x51),
79206750
SH		 330 }
331};
32c1ad9a 332
9d00278d 333static struct platform_device pcm037_mt9t031 = {
32c1ad9a
GL		 334 .name = "soc-camera-pdrv",
335 .id = 0,
336 .dev = {
9d00278d
GL		 337 .platform_data = &iclink_mt9t031,
338 },
339};
340
341static struct platform_device pcm037_mt9v022 = {
342 .name = "soc-camera-pdrv",
343 .id = 1,
344 .dev = {
345 .platform_data = &iclink_mt9v022,
32c1ad9a
GL		 346 },
347};
79206750 348
dddd4a49
SH		 349/* Not connected by default */
350#ifdef PCM970_SDHC_RW_SWITCH
351static int pcm970_sdhc1_get_ro(struct device *dev)
f2cb641f 352{
dddd4a49
SH		 353 return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
354}
355#endif
356
4f163eb8
SH		 357#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
358#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
359
dddd4a49
SH		 360static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
361 void *data)
362{
363 int ret;
dddd4a49 364
4f163eb8
SH		 365 ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
366 if (ret)
367 return ret;
368
369 gpio_direction_input(SDHC1_GPIO_DET);
dddd4a49 370
4f163eb8
SH		 371#ifdef PCM970_SDHC_RW_SWITCH
372 ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
373 if (ret)
374 goto err_gpio_free;
375 gpio_direction_input(SDHC1_GPIO_WP);
376#endif
dddd4a49
SH		 377
378 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
379 IRQF_DISABLED | IRQF_TRIGGER_FALLING,
380 "sdhc-detect", data);
4f163eb8
SH		 381 if (ret)
382 goto err_gpio_free_2;
383
384 return 0;
385
386err_gpio_free_2:
387#ifdef PCM970_SDHC_RW_SWITCH
388 gpio_free(SDHC1_GPIO_WP);
389err_gpio_free:
390#endif
391 gpio_free(SDHC1_GPIO_DET);
392
dddd4a49 393 return ret;
f2cb641f
SH		 394}
395
396static void pcm970_sdhc1_exit(struct device *dev, void *data)
397{
dddd4a49 398 free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
4f163eb8
SH		 399 gpio_free(SDHC1_GPIO_DET);
400 gpio_free(SDHC1_GPIO_WP);
f2cb641f
SH		 401}
402
6a697e3d 403static const struct imxmmc_platform_data sdhc_pdata __initconst = {
dddd4a49
SH		 404#ifdef PCM970_SDHC_RW_SWITCH
405 .get_ro = pcm970_sdhc1_get_ro,
406#endif
f2cb641f
SH		 407 .init = pcm970_sdhc1_init,
408 .exit = pcm970_sdhc1_exit,
409};
410
32c1ad9a
GL		 411struct mx3_camera_pdata camera_pdata = {
412 .dma_dev = &mx3_ipu.dev,
413 .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
414 .mclk_10khz = 2000,
415};
416
417static int __init pcm037_camera_alloc_dma(const size_t buf_size)
418{
419 dma_addr_t dma_handle;
420 void *buf;
421 int dma;
422
423 if (buf_size < 2 * 1024 * 1024)
424 return -EINVAL;
425
426 buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
427 if (!buf) {
428 pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
429 return -ENOMEM;
430 }
431
432 memset(buf, 0, buf_size);
433
434 dma = dma_declare_coherent_memory(&mx3_camera.dev,
435 dma_handle, dma_handle, buf_size,
436 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
437
438 /* The way we call dma_declare_coherent_memory only a malloc can fail */
439 return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
440}
441
ce8ffef0
SH		 442static struct platform_device *devices[] __initdata = {
443 &pcm037_flash,
3dad21a9 444 &pcm037_sram_device,
3170ba54 445 &imx_wdt_device0,
9d00278d
GL		 446 &pcm037_mt9t031,
447 &pcm037_mt9v022,
ce8ffef0
SH		 448};
449
a8df0ee8
GL		 450static struct ipu_platform_data mx3_ipu_data = {
451 .irq_base = MXC_IPU_IRQ_START,
452};
453
454static const struct fb_videomode fb_modedb[] = {
455 {
456 /* 240x320 @ 60 Hz Sharp */
457 .name = "Sharp-LQ035Q7DH06-QVGA",
458 .refresh = 60,
459 .xres = 240,
460 .yres = 320,
461 .pixclock = 185925,
462 .left_margin = 9,
463 .right_margin = 16,
464 .upper_margin = 7,
465 .lower_margin = 9,
466 .hsync_len = 1,
467 .vsync_len = 1,
468 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
469 FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
470 .vmode = FB_VMODE_NONINTERLACED,
471 .flag = 0,
472 }, {
473 /* 240x320 @ 60 Hz */
474 .name = "TX090",
475 .refresh = 60,
476 .xres = 240,
477 .yres = 320,
478 .pixclock = 38255,
479 .left_margin = 144,
480 .right_margin = 0,
481 .upper_margin = 7,
482 .lower_margin = 40,
483 .hsync_len = 96,
484 .vsync_len = 1,
485 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
486 .vmode = FB_VMODE_NONINTERLACED,
487 .flag = 0,
574ec547
GL		 488 }, {
489 /* 240x320 @ 60 Hz */
490 .name = "CMEL-OLED",
491 .refresh = 60,
492 .xres = 240,
493 .yres = 320,
494 .pixclock = 185925,
495 .left_margin = 9,
496 .right_margin = 16,
497 .upper_margin = 7,
498 .lower_margin = 9,
499 .hsync_len = 1,
500 .vsync_len = 1,
501 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
502 .vmode = FB_VMODE_NONINTERLACED,
503 .flag = 0,
a8df0ee8
GL		 504 },
505};
506
507static struct mx3fb_platform_data mx3fb_pdata = {
508 .dma_dev = &mx3_ipu.dev,
509 .name = "Sharp-LQ035Q7DH06-QVGA",
510 .mode = fb_modedb,
511 .num_modes = ARRAY_SIZE(fb_modedb),
512};
513
91bf9a25
SH		 514static struct resource pcm970_sja1000_resources[] = {
515 {
f568dd7f
UKK		 516 .start = MX31_CS5_BASE_ADDR,
517 .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
91bf9a25
SH		 518 .flags = IORESOURCE_MEM,
519 }, {
520 .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
521 .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
522 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
523 },
524};
525
526struct sja1000_platform_data pcm970_sja1000_platform_data = {
56e6943b
WG		 527 .osc_freq = 16000000,
528 .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
529 .cdr = CDR_CBP,
91bf9a25
SH		 530};
531
532static struct platform_device pcm970_sja1000 = {
533 .name = "sja1000_platform",
534 .dev = {
535 .platform_data = &pcm970_sja1000_platform_data,
536 },
537 .resource = pcm970_sja1000_resources,
538 .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
539};
540
c18e8fa5 541#if defined(CONFIG_USB_ULPI)
ee14373c
SH		 542static struct mxc_usbh_platform_data otg_pdata = {
543 .portsc = MXC_EHCI_MODE_ULPI,
544 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
545};
546
547static struct mxc_usbh_platform_data usbh2_pdata = {
548 .portsc = MXC_EHCI_MODE_ULPI,
549 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
550};
c18e8fa5 551#endif
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SH		 552
553static struct fsl_usb2_platform_data otg_device_pdata = {
554 .operating_mode = FSL_USB2_DR_DEVICE,
555 .phy_mode = FSL_USB2_PHY_ULPI,
556};
557
558static int otg_mode_host;
559
560static int __init pcm037_otg_mode(char *options)
561{
562 if (!strcmp(options, "host"))
563 otg_mode_host = 1;
564 else if (!strcmp(options, "device"))
565 otg_mode_host = 0;
566 else
567 pr_info("otg_mode neither \"host\" nor \"device\". "
568 "Defaulting to device\n");
569 return 0;
570}
571__setup("otg_mode=", pcm037_otg_mode);
572
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SH		 573/*
574 * Board specific initialization.
575 */
576static void __init mxc_board_init(void)
577{
4f163eb8 578 int ret;
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SH		 579
580 mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
4f163eb8 581
01ac7d58
SH		 582 mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
583 "pcm037");
584
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SH		 585#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
586 | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
587
588 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
589 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
590 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
591 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
592 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
593 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
594 mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
595 mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
596 mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
597 mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
598 mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
599 mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
600
574ec547
GL		 601 if (pcm037_variant() == PCM037_EET)
602 mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
603 ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
604 else
605 mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
606 ARRAY_SIZE(pcm037_uart1_handshake_pins),
607 "pcm037_uart1");
608
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SH		 609 platform_add_devices(devices, ARRAY_SIZE(devices));
610
16cf5c41
UKK		 611 imx31_add_imx_uart0(&uart_pdata);
612 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
613 imx31_add_imx_uart1(&uart_pdata);
614 imx31_add_imx_uart2(&uart_pdata);
d517cab1 615
ae71a562 616 imx31_add_mxc_w1(NULL);
ba54b958 617
f8e5143b 618 /* LAN9217 IRQ pin */
4f163eb8
SH		 619 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
620 if (ret)
621 pr_warning("could not get LAN irq gpio\n");
622 else {
623 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
624 platform_device_register(&pcm037_eth);
625 }
626
3287abbd 627
32c1ad9a 628 /* I2C adapters and devices */
79206750
SH		 629 i2c_register_board_info(1, pcm037_i2c_devices,
630 ARRAY_SIZE(pcm037_i2c_devices));
631
4a9b8b0b
UKK		 632 imx31_add_imx_i2c1(&pcm037_i2c1_data);
633 imx31_add_imx_i2c2(&pcm037_i2c2_data);
32c1ad9a 634
a2ceeef5 635 imx31_add_mxc_nand(&pcm037_nand_board_info);
6a697e3d 636 imx31_add_mxc_mmc(0, &sdhc_pdata);
a8df0ee8
GL		 637 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
638 mxc_register_device(&mx3_fb, &mx3fb_pdata);
32c1ad9a
GL		 639
640 /* CSI */
641 /* Camera power: default - off */
642 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
643 if (!ret)
644 gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
645 else
9d00278d 646 iclink_mt9t031.power = NULL;
32c1ad9a
GL		 647
648 if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
649 mxc_register_device(&mx3_camera, &camera_pdata);
91bf9a25
SH		 650
651 platform_device_register(&pcm970_sja1000);
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SH		 652
653#if defined(CONFIG_USB_ULPI)
654 if (otg_mode_host) {
655 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 656 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
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SH		 657
658 mxc_register_device(&mxc_otg_host, &otg_pdata);
659 }
660
661 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
13dd0c97 662 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
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SH		 663
664 mxc_register_device(&mxc_usbh2, &usbh2_pdata);
665#endif
666 if (!otg_mode_host)
667 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
668
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SH		 669}
670
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SH		 671static void __init pcm037_timer_init(void)
672{
30c730f8 673 mx31_clocks_init(26000000);
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SH		 674}
675
676struct sys_timer pcm037_timer = {
677 .init = pcm037_timer_init,
678};
679
680MACHINE_START(PCM037, "Phytec Phycore pcm037")
681 /* Maintainer: Pengutronix */
34101237 682 .boot_params = MX3x_PHYS_OFFSET + 0x100,
cd4a05f9 683 .map_io = mx31_map_io,
c5aa0ad0 684 .init_irq = mx31_init_irq,
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SH		 685 .init_machine = mxc_board_init,
686 .timer = &pcm037_timer,
687MACHINE_END
Linux 6.x block layer and io_uring tree(s)