[linux-2.6-block.git] / arch / arm / mach-mx3 / mach-mx31ads.c

/*
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/irq.h>

#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31ads.h>
#include <mach/iomux-mx3.h>

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
#include <linux/mfd/wm8350/audio.h>
#include <linux/mfd/wm8350/core.h>
#include <linux/mfd/wm8350/pmic.h>
#endif

#include "devices-imx31.h"
#include "devices.h"

/* PBC Board interrupt status register */
#define PBC_INTSTATUS           0x000016

/* PBC Board interrupt current status register */
#define PBC_INTCURR_STATUS      0x000018

/* PBC Interrupt mask register set address */
#define PBC_INTMASK_SET         0x00001A

/* PBC Interrupt mask register clear address */
#define PBC_INTMASK_CLEAR       0x00001C

/* External UART A */
#define PBC_SC16C652_UARTA      0x010000

/* External UART B */
#define PBC_SC16C652_UARTB      0x010010

#define PBC_INTSTATUS_REG	(PBC_INTSTATUS + PBC_BASE_ADDRESS)
#define PBC_INTMASK_SET_REG	(PBC_INTMASK_SET + PBC_BASE_ADDRESS)
#define PBC_INTMASK_CLEAR_REG	(PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
#define EXPIO_PARENT_INT	IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)

#define MXC_IRQ_TO_EXPIO(irq)	((irq) - MXC_EXP_IO_BASE)

#define EXPIO_INT_XUART_INTA	(MXC_EXP_IO_BASE + 10)
#define EXPIO_INT_XUART_INTB	(MXC_EXP_IO_BASE + 11)

#define MXC_MAX_EXP_IO_LINES	16
/*
 * This file contains the board-specific initialization routines.
 */

#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
/*!
 * The serial port definition structure.
 */
static struct plat_serial8250_port serial_platform_data[] = {
	{
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
		.irq      = EXPIO_INT_XUART_INTA,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	}, {
		.membase  = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
		.mapbase  = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
		.irq      = EXPIO_INT_XUART_INTB,
		.uartclk  = 14745600,
		.regshift = 0,
		.iotype   = UPIO_MEM,
		.flags    = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
	},
	{},
};

static struct platform_device serial_device = {
	.name	= "serial8250",
	.id	= 0,
	.dev	= {
		.platform_data = serial_platform_data,
	},
};

static int __init mxc_init_extuart(void)
{
	return platform_device_register(&serial_device);
}
#else
static inline int mxc_init_extuart(void)
{
	return 0;
}
#endif

static const struct imxuart_platform_data uart_pdata __initconst = {
	.flags = IMXUART_HAVE_RTSCTS,
};

static unsigned int uart_pins[] = {
	MX31_PIN_CTS1__CTS1,
	MX31_PIN_RTS1__RTS1,
	MX31_PIN_TXD1__TXD1,
	MX31_PIN_RXD1__RXD1
};

static inline void mxc_init_imx_uart(void)
{
	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
	imx31_add_imx_uart0(&uart_pdata);
}

static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
{
	u32 imr_val;
	u32 int_valid;
	u32 expio_irq;

	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;

	expio_irq = MXC_EXP_IO_BASE;
	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
		if ((int_valid & 1) == 0)
			continue;

		generic_handle_irq(expio_irq);
	}
}

/*
 * Disable an expio pin's interrupt by setting the bit in the imr.
 * @param irq           an expio virtual irq number
 */
static void expio_mask_irq(struct irq_data *d)
{
	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
	/* mask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	__raw_readw(PBC_INTMASK_CLEAR_REG);
}

/*
 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
 * @param irq           an expanded io virtual irq number
 */
static void expio_ack_irq(struct irq_data *d)
{
	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
	/* clear the interrupt status */
	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
}

/*
 * Enable a expio pin's interrupt by clearing the bit in the imr.
 * @param irq           a expio virtual irq number
 */
static void expio_unmask_irq(struct irq_data *d)
{
	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
	/* unmask the interrupt */
	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
}

static struct irq_chip expio_irq_chip = {
	.name = "EXPIO(CPLD)",
	.irq_ack = expio_ack_irq,
	.irq_mask = expio_mask_irq,
	.irq_unmask = expio_unmask_irq,
};

static void __init mx31ads_init_expio(void)
{
	int i;

	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");

	/*
	 * Configure INT line as GPIO input
	 */
	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");

	/* disable the interrupt and clear the status */
	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	     i++) {
		set_irq_chip(i, &expio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
}

#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
/* This section defines setup for the Wolfson Microelectronics
 * 1133-EV1 PMU/audio board.  When other PMU boards are supported the
 * regulator definitions may be shared with them, but for now they can
 * only be used with this board so would generate warnings about
 * unused statics and some of the configuration is specific to this
 * module.
 */

/* CPU */
static struct regulator_consumer_supply sw1a_consumers[] = {
	{
		.supply = "cpu_vcc",
	}
};

static struct regulator_init_data sw1a_data = {
	.constraints = {
		.name = "SW1A",
		.min_uV = 1275000,
		.max_uV = 1600000,
		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
				  REGULATOR_CHANGE_MODE,
		.valid_modes_mask = REGULATOR_MODE_NORMAL |
				    REGULATOR_MODE_FAST,
		.state_mem = {
			 .uV = 1400000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	.consumer_supplies = sw1a_consumers,
};

/* System IO - High */
static struct regulator_init_data viohi_data = {
	.constraints = {
		.name = "VIOHO",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.state_mem = {
			 .uV = 2800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* System IO - Low */
static struct regulator_init_data violo_data = {
	.constraints = {
		.name = "VIOLO",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.initial_state = PM_SUSPEND_MEM,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* DDR RAM */
static struct regulator_init_data sw2a_data = {
	.constraints = {
		.name = "SW2A",
		.min_uV = 1800000,
		.max_uV = 1800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.state_mem = {
			 .uV = 1800000,
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 1,
		 },
		.state_disk = {
			 .mode = REGULATOR_MODE_NORMAL,
			 .enabled = 0,
		 },
		.always_on = 1,
		.boot_on = 1,
		.initial_state = PM_SUSPEND_MEM,
	},
};

static struct regulator_init_data ldo1_data = {
	.constraints = {
		.name = "VCAM/VMMC1/VMMC2",
		.min_uV = 2800000,
		.max_uV = 2800000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
};

static struct regulator_consumer_supply ldo2_consumers[] = {
	{ .supply = "AVDD", .dev_name = "1-001a" },
	{ .supply = "HPVDD", .dev_name = "1-001a" },
};

/* CODEC and SIM */
static struct regulator_init_data ldo2_data = {
	.constraints = {
		.name = "VESIM/VSIM/AVDD",
		.min_uV = 3300000,
		.max_uV = 3300000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.valid_ops_mask = REGULATOR_CHANGE_STATUS,
		.apply_uV = 1,
	},
	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	.consumer_supplies = ldo2_consumers,
};

/* General */
static struct regulator_init_data vdig_data = {
	.constraints = {
		.name = "VDIG",
		.min_uV = 1500000,
		.max_uV = 1500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

/* Tranceivers */
static struct regulator_init_data ldo4_data = {
	.constraints = {
		.name = "VRF1/CVDD_2.775",
		.min_uV = 2500000,
		.max_uV = 2500000,
		.valid_modes_mask = REGULATOR_MODE_NORMAL,
		.apply_uV = 1,
		.always_on = 1,
		.boot_on = 1,
	},
};

static struct wm8350_led_platform_data wm8350_led_data = {
	.name            = "wm8350:white",
	.default_trigger = "heartbeat",
	.max_uA          = 27899,
};

static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	.vmid_discharge_msecs = 1000,
	.drain_msecs = 30,
	.cap_discharge_msecs = 700,
	.vmid_charge_msecs = 700,
	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	.dis_out4 = WM8350_DISCHARGE_SLOW,
	.dis_out3 = WM8350_DISCHARGE_SLOW,
	.dis_out2 = WM8350_DISCHARGE_SLOW,
	.dis_out1 = WM8350_DISCHARGE_SLOW,
	.vroi_out4 = WM8350_TIE_OFF_500R,
	.vroi_out3 = WM8350_TIE_OFF_500R,
	.vroi_out2 = WM8350_TIE_OFF_500R,
	.vroi_out1 = WM8350_TIE_OFF_500R,
	.vroi_enable = 0,
	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
};

static int mx31_wm8350_init(struct wm8350 *wm8350)
{
	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_ON);

	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
			   WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
			   WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
			   WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
			   WM8350_GPIO_DEBOUNCE_OFF);

	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);

	/* LEDs */
	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
			     WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
			       WM8350_ISINK_FLASH_DISABLE,
			       WM8350_ISINK_FLASH_TRIG_BIT,
			       WM8350_ISINK_FLASH_DUR_32MS,
			       WM8350_ISINK_FLASH_ON_INSTANT,
			       WM8350_ISINK_FLASH_OFF_INSTANT,
			       WM8350_ISINK_FLASH_MODE_EN);
	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
			       WM8350_ISINK_MODE_BOOST,
			       WM8350_ISINK_ILIM_NORMAL,
			       WM8350_DC5_RMP_20V,
			       WM8350_DC5_FBSRC_ISINKA);
	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
			    &wm8350_led_data);

	wm8350->codec.platform_data = &imx32ads_wm8350_setup;

	regulator_has_full_constraints();

	return 0;
}

static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	.init = mx31_wm8350_init,
	.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
};
#endif

static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	{
		I2C_BOARD_INFO("wm8350", 0x1a),
		.platform_data = &mx31_wm8350_pdata,
		.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	},
#endif
};

static void mxc_init_i2c(void)
{
	i2c_register_board_info(1, mx31ads_i2c1_devices,
				ARRAY_SIZE(mx31ads_i2c1_devices));

	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));

	imx31_add_imx_i2c1(NULL);
}

static unsigned int ssi_pins[] = {
	MX31_PIN_SFS5__SFS5,
	MX31_PIN_SCK5__SCK5,
	MX31_PIN_SRXD5__SRXD5,
	MX31_PIN_STXD5__STXD5,
};

static void mxc_init_audio(void)
{
	imx31_add_imx_ssi(0, NULL);
	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
}

/*!
 * This structure defines static mappings for the i.MX31ADS board.
 */
static struct map_desc mx31ads_io_desc[] __initdata = {
	{
		.virtual	= MX31_CS4_BASE_ADDR_VIRT,
		.pfn		= __phys_to_pfn(MX31_CS4_BASE_ADDR),
		.length		= MX31_CS4_SIZE / 2,
		.type		= MT_DEVICE
	},
};

/*!
 * Set up static virtual mappings.
 */
static void __init mx31ads_map_io(void)
{
	mx31_map_io();
	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
}

static void __init mx31ads_init_irq(void)
{
	mx31_init_irq();
	mx31ads_init_expio();
}

/*!
 * Board specific initialization.
 */
static void __init mxc_board_init(void)
{
	mxc_init_extuart();
	mxc_init_imx_uart();
	mxc_init_i2c();
	mxc_init_audio();
}

static void __init mx31ads_timer_init(void)
{
	mx31_clocks_init(26000000);
}

static struct sys_timer mx31ads_timer = {
	.init	= mx31ads_timer_init,
};

/*
 * The following uses standard kernel macros defined in arch.h in order to
 * initialize __mach_desc_MX31ADS data structure.
 */
MACHINE_START(MX31ADS, "Freescale MX31ADS")
	/* Maintainer: Freescale Semiconductor, Inc. */
	.boot_params    = MX3x_PHYS_OFFSET + 0x100,
	.map_io         = mx31ads_map_io,
	.init_irq       = mx31ads_init_irq,
	.init_machine   = mxc_board_init,
	.timer          = &mx31ads_timer,
MACHINE_END
Commit	Line	Data
52c543f9 QJ	1	/*
	2	* Copyright (C) 2000 Deep Blue Solutions Ltd
	3	* Copyright (C) 2002 Shane Nay (shane@minirl.com)
	4	* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
52c543f9 QJ	15	*/
	16
	17	#include <linux/types.h>
	18	#include <linux/init.h>
	19	#include <linux/clk.h>
	20	#include <linux/serial_8250.h>
fe7316bf MB	21	#include <linux/gpio.h>
fe7316bf MB	22	#include <linux/i2c.h>
d7568f79	23	#include <linux/irq.h>
52c543f9	24
52c543f9 QJ	25	#include <asm/mach-types.h>
52c543f9 QJ	26	#include <asm/mach/arch.h>
d0f349fb	27	#include <asm/mach/time.h>
52c543f9 QJ	28	#include <asm/memory.h>
52c543f9 QJ	29	#include <asm/mach/map.h>
a09e64fb	30	#include <mach/common.h>
d24d96e0	31	#include <mach/board-mx31ads.h>
0741794c	32	#include <mach/iomux-mx3.h>
52c543f9	33
fe7316bf MB	34	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	35	#include <linux/mfd/wm8350/audio.h>
	36	#include <linux/mfd/wm8350/core.h>
	37	#include <linux/mfd/wm8350/pmic.h>
	38	#endif
	39
4a9b8b0b	40	#include "devices-imx31.h"
2eca047b SH	41	#include "devices.h"
2eca047b SH	42
ccfa7c26 UKK	43	/* PBC Board interrupt status register */
	44	#define PBC_INTSTATUS 0x000016
	45
	46	/* PBC Board interrupt current status register */
	47	#define PBC_INTCURR_STATUS 0x000018
	48
	49	/* PBC Interrupt mask register set address */
	50	#define PBC_INTMASK_SET 0x00001A
	51
	52	/* PBC Interrupt mask register clear address */
	53	#define PBC_INTMASK_CLEAR 0x00001C
	54
	55	/* External UART A */
	56	#define PBC_SC16C652_UARTA 0x010000
	57
	58	/* External UART B */
	59	#define PBC_SC16C652_UARTB 0x010010
	60
	61	#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
	62	#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
	63	#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
	64	#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
	65
ccfa7c26 UKK	66	#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
	67
	68	#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
	69	#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
	70
	71	#define MXC_MAX_EXP_IO_LINES 16
	72	/*
	73	* This file contains the board-specific initialization routines.
52c543f9 QJ	74	*/
	75
	76	#if defined(CONFIG_SERIAL_8250) \|\| defined(CONFIG_SERIAL_8250_MODULE)
	77	/*!
	78	* The serial port definition structure.
	79	*/
	80	static struct plat_serial8250_port serial_platform_data[] = {
	81	{
	82	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
f568dd7f	83	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
52c543f9 QJ	84	.irq = EXPIO_INT_XUART_INTA,
	85	.uartclk = 14745600,
	86	.regshift = 0,
	87	.iotype = UPIO_MEM,
	88	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	89	}, {
	90	.membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
f568dd7f	91	.mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
52c543f9 QJ	92	.irq = EXPIO_INT_XUART_INTB,
	93	.uartclk = 14745600,
	94	.regshift = 0,
	95	.iotype = UPIO_MEM,
	96	.flags = UPF_BOOT_AUTOCONF \| UPF_SKIP_TEST \| UPF_AUTO_IRQ,
	97	},
	98	{},
	99	};
	100
	101	static struct platform_device serial_device = {
	102	.name = "serial8250",
	103	.id = 0,
	104	.dev = {
	105	.platform_data = serial_platform_data,
	106	},
	107	};
	108
	109	static int __init mxc_init_extuart(void)
	110	{
	111	return platform_device_register(&serial_device);
	112	}
	113	#else
	114	static inline int mxc_init_extuart(void)
	115	{
	116	return 0;
	117	}
	118	#endif
	119
16cf5c41	120	static const struct imxuart_platform_data uart_pdata __initconst = {
0741794c GC	121	.flags = IMXUART_HAVE_RTSCTS,
	122	};
	123
9070e7af	124	static unsigned int uart_pins[] = {
945c10b8 VL	125	MX31_PIN_CTS1__CTS1,
	126	MX31_PIN_RTS1__RTS1,
	127	MX31_PIN_TXD1__TXD1,
	128	MX31_PIN_RXD1__RXD1
	129	};
	130
0741794c GC	131	static inline void mxc_init_imx_uart(void)
0741794c GC	132	{
945c10b8	133	mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
16cf5c41	134	imx31_add_imx_uart0(&uart_pdata);
0741794c	135	}
0741794c	136
d7568f79 GC	137	static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
	138	{
	139	u32 imr_val;
	140	u32 int_valid;
	141	u32 expio_irq;
	142
	143	imr_val = __raw_readw(PBC_INTMASK_SET_REG);
	144	int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
	145
	146	expio_irq = MXC_EXP_IO_BASE;
	147	for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
	148	if ((int_valid & 1) == 0)
	149	continue;
	150
	151	generic_handle_irq(expio_irq);
	152	}
	153	}
	154
	155	/*
	156	* Disable an expio pin's interrupt by setting the bit in the imr.
	157	* @param irq an expio virtual irq number
	158	*/
e981a302	159	static void expio_mask_irq(struct irq_data *d)
d7568f79	160	{
e981a302	161	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
d7568f79 GC	162	/* mask the interrupt */
	163	__raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
	164	__raw_readw(PBC_INTMASK_CLEAR_REG);
	165	}
	166
	167	/*
	168	* Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
	169	* @param irq an expanded io virtual irq number
	170	*/
e981a302	171	static void expio_ack_irq(struct irq_data *d)
d7568f79	172	{
e981a302	173	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
d7568f79 GC	174	/* clear the interrupt status */
	175	__raw_writew(1 << expio, PBC_INTSTATUS_REG);
	176	}
	177
	178	/*
	179	* Enable a expio pin's interrupt by clearing the bit in the imr.
	180	* @param irq a expio virtual irq number
	181	*/
e981a302	182	static void expio_unmask_irq(struct irq_data *d)
d7568f79	183	{
e981a302	184	u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
d7568f79 GC	185	/* unmask the interrupt */
	186	__raw_writew(1 << expio, PBC_INTMASK_SET_REG);
	187	}
	188
	189	static struct irq_chip expio_irq_chip = {
bd02acdb	190	.name = "EXPIO(CPLD)",
e981a302 LB	191	.irq_ack = expio_ack_irq,
	192	.irq_mask = expio_mask_irq,
	193	.irq_unmask = expio_unmask_irq,
d7568f79 GC	194	};
	195
	196	static void __init mx31ads_init_expio(void)
	197	{
	198	int i;
	199
	200	printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
	201
	202	/*
	203	* Configure INT line as GPIO input
	204	*/
4f163eb8	205	mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
d7568f79 GC	206
	207	/* disable the interrupt and clear the status */
	208	__raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
	209	__raw_writew(0xFFFF, PBC_INTSTATUS_REG);
	210	for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
	211	i++) {
	212	set_irq_chip(i, &expio_irq_chip);
	213	set_irq_handler(i, handle_level_irq);
	214	set_irq_flags(i, IRQF_VALID);
	215	}
	216	set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
	217	set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
	218	}
	219
fe7316bf MB	220	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	221	/* This section defines setup for the Wolfson Microelectronics
	222	* 1133-EV1 PMU/audio board. When other PMU boards are supported the
	223	* regulator definitions may be shared with them, but for now they can
	224	* only be used with this board so would generate warnings about
	225	* unused statics and some of the configuration is specific to this
	226	* module.
	227	*/
	228
	229	/* CPU */
	230	static struct regulator_consumer_supply sw1a_consumers[] = {
	231	{
	232	.supply = "cpu_vcc",
	233	}
	234	};
	235
	236	static struct regulator_init_data sw1a_data = {
	237	.constraints = {
	238	.name = "SW1A",
	239	.min_uV = 1275000,
	240	.max_uV = 1600000,
	241	.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE \|
	242	REGULATOR_CHANGE_MODE,
	243	.valid_modes_mask = REGULATOR_MODE_NORMAL \|
	244	REGULATOR_MODE_FAST,
	245	.state_mem = {
	246	.uV = 1400000,
	247	.mode = REGULATOR_MODE_NORMAL,
	248	.enabled = 1,
	249	},
	250	.initial_state = PM_SUSPEND_MEM,
	251	.always_on = 1,
	252	.boot_on = 1,
	253	},
	254	.num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
	255	.consumer_supplies = sw1a_consumers,
	256	};
	257
	258	/* System IO - High */
	259	static struct regulator_init_data viohi_data = {
	260	.constraints = {
	261	.name = "VIOHO",
	262	.min_uV = 2800000,
	263	.max_uV = 2800000,
	264	.state_mem = {
	265	.uV = 2800000,
	266	.mode = REGULATOR_MODE_NORMAL,
	267	.enabled = 1,
	268	},
	269	.initial_state = PM_SUSPEND_MEM,
	270	.always_on = 1,
	271	.boot_on = 1,
	272	},
	273	};
	274
	275	/* System IO - Low */
	276	static struct regulator_init_data violo_data = {
	277	.constraints = {
	278	.name = "VIOLO",
	279	.min_uV = 1800000,
	280	.max_uV = 1800000,
	281	.state_mem = {
	282	.uV = 1800000,
	283	.mode = REGULATOR_MODE_NORMAL,
284	.enabled = 1,
285	},
286	.initial_state = PM_SUSPEND_MEM,
287	.always_on = 1,
288	.boot_on = 1,
289	},
290	};
291
292	/* DDR RAM */
293	static struct regulator_init_data sw2a_data = {
294	.constraints = {
295	.name = "SW2A",
296	.min_uV = 1800000,
297	.max_uV = 1800000,
298	.valid_modes_mask = REGULATOR_MODE_NORMAL,
299	.state_mem = {
300	.uV = 1800000,
301	.mode = REGULATOR_MODE_NORMAL,
302	.enabled = 1,
303	},
304	.state_disk = {
305	.mode = REGULATOR_MODE_NORMAL,
306	.enabled = 0,
307	},
308	.always_on = 1,
309	.boot_on = 1,
310	.initial_state = PM_SUSPEND_MEM,
311	},
312	};
313
314	static struct regulator_init_data ldo1_data = {
315	.constraints = {
316	.name = "VCAM/VMMC1/VMMC2",
317	.min_uV = 2800000,
318	.max_uV = 2800000,
319	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	320	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	321	.apply_uV = 1,
	322	},
	323	};
	324
	325	static struct regulator_consumer_supply ldo2_consumers[] = {
edc34a90 MB	326	{ .supply = "AVDD", .dev_name = "1-001a" },
edc34a90 MB	327	{ .supply = "HPVDD", .dev_name = "1-001a" },
fe7316bf MB	328	};
	329
	330	/* CODEC and SIM */
	331	static struct regulator_init_data ldo2_data = {
	332	.constraints = {
	333	.name = "VESIM/VSIM/AVDD",
	334	.min_uV = 3300000,
	335	.max_uV = 3300000,
	336	.valid_modes_mask = REGULATOR_MODE_NORMAL,
becc670a	337	.valid_ops_mask = REGULATOR_CHANGE_STATUS,
fe7316bf MB	338	.apply_uV = 1,
	339	},
	340	.num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
	341	.consumer_supplies = ldo2_consumers,
	342	};
	343
	344	/* General */
	345	static struct regulator_init_data vdig_data = {
	346	.constraints = {
	347	.name = "VDIG",
	348	.min_uV = 1500000,
	349	.max_uV = 1500000,
	350	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	351	.apply_uV = 1,
	352	.always_on = 1,
	353	.boot_on = 1,
	354	},
	355	};
	356
	357	/* Tranceivers */
	358	static struct regulator_init_data ldo4_data = {
	359	.constraints = {
	360	.name = "VRF1/CVDD_2.775",
	361	.min_uV = 2500000,
	362	.max_uV = 2500000,
	363	.valid_modes_mask = REGULATOR_MODE_NORMAL,
	364	.apply_uV = 1,
	365	.always_on = 1,
	366	.boot_on = 1,
	367	},
	368	};
	369
	370	static struct wm8350_led_platform_data wm8350_led_data = {
	371	.name = "wm8350:white",
	372	.default_trigger = "heartbeat",
	373	.max_uA = 27899,
	374	};
	375
	376	static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
	377	.vmid_discharge_msecs = 1000,
	378	.drain_msecs = 30,
	379	.cap_discharge_msecs = 700,
	380	.vmid_charge_msecs = 700,
	381	.vmid_s_curve = WM8350_S_CURVE_SLOW,
	382	.dis_out4 = WM8350_DISCHARGE_SLOW,
	383	.dis_out3 = WM8350_DISCHARGE_SLOW,
	384	.dis_out2 = WM8350_DISCHARGE_SLOW,
	385	.dis_out1 = WM8350_DISCHARGE_SLOW,
	386	.vroi_out4 = WM8350_TIE_OFF_500R,
	387	.vroi_out3 = WM8350_TIE_OFF_500R,
	388	.vroi_out2 = WM8350_TIE_OFF_500R,
	389	.vroi_out1 = WM8350_TIE_OFF_500R,
	390	.vroi_enable = 0,
	391	.codec_current_on = WM8350_CODEC_ISEL_1_0,
	392	.codec_current_standby = WM8350_CODEC_ISEL_0_5,
	393	.codec_current_charge = WM8350_CODEC_ISEL_1_5,
	394	};
	395
	396	static int mx31_wm8350_init(struct wm8350 *wm8350)
	397	{
fe7316bf MB	398	wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
	399	WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
	400	WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
	401	WM8350_GPIO_DEBOUNCE_ON);
	402
	403	wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
	404	WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
	405	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	406	WM8350_GPIO_DEBOUNCE_ON);
	407
	408	wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
	409	WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
	410	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	411	WM8350_GPIO_DEBOUNCE_OFF);
	412
	413	wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
	414	WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
	415	WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
	416	WM8350_GPIO_DEBOUNCE_OFF);
	417
	418	wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
	419	WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
	420	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	421	WM8350_GPIO_DEBOUNCE_OFF);
	422
	423	wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
	424	WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	425	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	426	WM8350_GPIO_DEBOUNCE_OFF);
	427
	428	wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
	429	WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
	430	WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
	431	WM8350_GPIO_DEBOUNCE_OFF);
	432
fe7316bf MB	433	wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
	434	wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
	435	wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
	436	wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
	437	wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
	438	wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
	439	wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
	440	wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
	441
	442	/* LEDs */
	443	wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
	444	WM8350_DC5_ERRACT_SHUTDOWN_CONV);
	445	wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
	446	WM8350_ISINK_FLASH_DISABLE,
	447	WM8350_ISINK_FLASH_TRIG_BIT,
	448	WM8350_ISINK_FLASH_DUR_32MS,
	449	WM8350_ISINK_FLASH_ON_INSTANT,
	450	WM8350_ISINK_FLASH_OFF_INSTANT,
	451	WM8350_ISINK_FLASH_MODE_EN);
	452	wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
	453	WM8350_ISINK_MODE_BOOST,
	454	WM8350_ISINK_ILIM_NORMAL,
	455	WM8350_DC5_RMP_20V,
	456	WM8350_DC5_FBSRC_ISINKA);
	457	wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
	458	&wm8350_led_data);
	459
	460	wm8350->codec.platform_data = &imx32ads_wm8350_setup;
	461
0ac402fd MB	462	regulator_has_full_constraints();
0ac402fd MB	463
fe7316bf MB	464	return 0;
	465	}
	466
	467	static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
	468	.init = mx31_wm8350_init,
3d661ac1	469	.irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
fe7316bf MB	470	};
	471	#endif
	472
fe7316bf MB	473	static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
	474	#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
	475	{
	476	I2C_BOARD_INFO("wm8350", 0x1a),
	477	.platform_data = &mx31_wm8350_pdata,
	478	.irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
	479	},
	480	#endif
	481	};
	482
	483	static void mxc_init_i2c(void)
	484	{
	485	i2c_register_board_info(1, mx31ads_i2c1_devices,
	486	ARRAY_SIZE(mx31ads_i2c1_devices));
	487
	488	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
	489	mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
	490
4a9b8b0b	491	imx31_add_imx_i2c1(NULL);
fe7316bf	492	}
fe7316bf	493
cd6eb980 MB	494	static unsigned int ssi_pins[] = {
	495	MX31_PIN_SFS5__SFS5,
	496	MX31_PIN_SCK5__SCK5,
	497	MX31_PIN_SRXD5__SRXD5,
	498	MX31_PIN_STXD5__STXD5,
	499	};
	500
	501	static void mxc_init_audio(void)
	502	{
4697bb92	503	imx31_add_imx_ssi(0, NULL);
cd6eb980 MB	504	mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
	505	}
	506
52c543f9 QJ	507	/*!
	508	* This structure defines static mappings for the i.MX31ADS board.
	509	*/
	510	static struct map_desc mx31ads_io_desc[] __initdata = {
	511	{
f568dd7f UKK	512	.virtual = MX31_CS4_BASE_ADDR_VIRT,
	513	.pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
	514	.length = MX31_CS4_SIZE / 2,
52c543f9 QJ	515	.type = MT_DEVICE
	516	},
	517	};
	518
	519	/*!
	520	* Set up static virtual mappings.
	521	*/
8b785b9d	522	static void __init mx31ads_map_io(void)
52c543f9	523	{
cd4a05f9	524	mx31_map_io();
52c543f9 QJ	525	iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
	526	}
	527
8b785b9d	528	static void __init mx31ads_init_irq(void)
d7568f79	529	{
c5aa0ad0	530	mx31_init_irq();
d7568f79 GC	531	mx31ads_init_expio();
	532	}
	533
52c543f9 QJ	534	/*!
	535	* Board specific initialization.
	536	*/
	537	static void __init mxc_board_init(void)
	538	{
	539	mxc_init_extuart();
0741794c	540	mxc_init_imx_uart();
fe7316bf	541	mxc_init_i2c();
cd6eb980	542	mxc_init_audio();
52c543f9 QJ	543	}
52c543f9 QJ	544
d0f349fb JB	545	static void __init mx31ads_timer_init(void)
d0f349fb JB	546	{
30c730f8	547	mx31_clocks_init(26000000);
d0f349fb JB	548	}
d0f349fb JB	549
8b785b9d	550	static struct sys_timer mx31ads_timer = {
d0f349fb JB	551	.init = mx31ads_timer_init,
	552	};
	553
52c543f9 QJ	554	/*
	555	* The following uses standard kernel macros defined in arch.h in order to
	556	* initialize __mach_desc_MX31ADS data structure.
	557	*/
	558	MACHINE_START(MX31ADS, "Freescale MX31ADS")
	559	/* Maintainer: Freescale Semiconductor, Inc. */
34101237	560	.boot_params = MX3x_PHYS_OFFSET + 0x100,
52c543f9	561	.map_io = mx31ads_map_io,
d7568f79	562	.init_irq = mx31ads_init_irq,
52c543f9	563	.init_machine = mxc_board_init,
d0f349fb	564	.timer = &mx31ads_timer,
52c543f9	565	MACHINE_END