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ARM i.MX31 lilly: remove incomplete otg support
[linux-2.6-block.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
1553a1ec
FE		 16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/irq.h>
135cad36 20#include <linux/gpio.h>
2b0c3677 21#include <linux/platform_device.h>
ae7a3f13
AP		 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h>
24#include <linux/regulator/machine.h>
1c50e672
FE		 25#include <linux/usb/otg.h>
26#include <linux/usb/ulpi.h>
1553a1ec
FE		 27
28#include <mach/hardware.h>
29#include <asm/mach-types.h>
30#include <asm/mach/arch.h>
31#include <asm/mach/time.h>
32#include <asm/memory.h>
33#include <asm/mach/map.h>
34#include <mach/common.h>
1553a1ec 35#include <mach/iomux-mx3.h>
c5d38f08 36#include <mach/3ds_debugboard.h>
1c50e672 37#include <mach/ulpi.h>
a2ceeef5
UKK		 38
39#include "devices-imx31.h"
1553a1ec
FE		 40#include "devices.h"
41
b396dc45
UKK		 42/* CPLD IRQ line for external uart, external ethernet etc */
43#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
44
11a332ad 45static int mx31_3ds_pins[] = {
153fa1d8 46 /* UART1 */
63d97667
VL		 47 MX31_PIN_CTS1__CTS1,
48 MX31_PIN_RTS1__RTS1,
49 MX31_PIN_TXD1__TXD1,
135cad36
ML		 50 MX31_PIN_RXD1__RXD1,
51 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
a1ac4424
AP		 52 /* SPI 1 */
53 MX31_PIN_CSPI2_SCLK__SCLK,
54 MX31_PIN_CSPI2_MOSI__MOSI,
55 MX31_PIN_CSPI2_MISO__MISO,
56 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
57 MX31_PIN_CSPI2_SS0__SS0,
58 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 59 /* MC13783 IRQ */
60 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 61 /* USB OTG reset */
62 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
63 /* USB OTG */
64 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
65 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
66 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
67 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
68 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
69 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
70 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
71 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
72 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
73 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
74 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
75 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 76 /*Keyboard*/
77 MX31_PIN_KEY_ROW0_KEY_ROW0,
78 MX31_PIN_KEY_ROW1_KEY_ROW1,
79 MX31_PIN_KEY_ROW2_KEY_ROW2,
80 MX31_PIN_KEY_COL0_KEY_COL0,
81 MX31_PIN_KEY_COL1_KEY_COL1,
82 MX31_PIN_KEY_COL2_KEY_COL2,
83 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 84 /* USB Host 2 */
85 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
86 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
87 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
88 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
89 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
90 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
91 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
92 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
93 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
94 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
95 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
96 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
97 /* USB Host2 reset */
98 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 99 /* I2C1 */
100 MX31_PIN_I2C_CLK__I2C1_SCL,
101 MX31_PIN_I2C_DAT__I2C1_SDA,
54c1f636
AP		 102};
103
104/*
105 * Matrix keyboard
106 */
107
108static const uint32_t mx31_3ds_keymap[] = {
109 KEY(0, 0, KEY_UP),
110 KEY(0, 1, KEY_DOWN),
111 KEY(1, 0, KEY_RIGHT),
112 KEY(1, 1, KEY_LEFT),
113 KEY(1, 2, KEY_ENTER),
114 KEY(2, 0, KEY_F6),
115 KEY(2, 1, KEY_F8),
116 KEY(2, 2, KEY_F9),
117 KEY(2, 3, KEY_F10),
118};
119
d690b4c4 120static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 121 .keymap = mx31_3ds_keymap,
122 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 123};
124
125/* Regulators */
126static struct regulator_init_data pwgtx_init = {
127 .constraints = {
128 .boot_on = 1,
129 .always_on = 1,
130 },
131};
132
0d95b75e
FE		 133static struct regulator_init_data gpo_init = {
134 .constraints = {
135 .boot_on = 1,
136 .always_on = 1,
137 }
138};
139
5836372e 140static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 141 {
57c78e35 142 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 143 .init_data = &pwgtx_init,
144 }, {
57c78e35 145 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 146 .init_data = &pwgtx_init,
0d95b75e
FE		 147 }, {
148
c97b7393 149 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 150 .init_data = &gpo_init,
151 }, {
c97b7393 152 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 153 .init_data = &gpo_init,
ae7a3f13
AP		 154 },
155};
156
157/* MC13783 */
5836372e 158static struct mc13xxx_platform_data mc13783_pdata __initdata = {
ae7a3f13
AP		 159 .regulators = mx31_3ds_regulators,
160 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
5836372e 161 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
a1ac4424
AP		 162};
163
164/* SPI */
165static int spi1_internal_chipselect[] = {
166 MXC_SPI_CS(0),
167 MXC_SPI_CS(2),
168};
169
06606ff1 170static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 171 .chipselect = spi1_internal_chipselect,
172 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 173};
174
ae7a3f13
AP		 175static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
176 {
177 .modalias = "mc13783",
178 .max_speed_hz = 1000000,
179 .bus_num = 1,
180 .chip_select = 1, /* SS2 */
181 .platform_data = &mc13783_pdata,
182 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
183 .mode = SPI_CS_HIGH,
184 },
185};
186
a1b67b95
AP		 187/*
188 * NAND Flash
189 */
a2ceeef5
UKK		 190static const struct mxc_nand_platform_data
191mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 192 .width = 1,
193 .hw_ecc = 1,
194#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
195 .flash_bbt = 1,
196#endif
197};
198
a2ef4562
ML		 199/*
200 * USB OTG
201 */
202
203#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
204 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
205
206#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 207#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 208
41f63475 209static int mx31_3ds_usbotg_init(void)
a2ef4562 210{
41f63475
FE		 211 int err;
212
a2ef4562
ML		 213 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
214 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
215 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
216 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
217 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
218 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
219 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
220 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
221 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
222 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
223 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
224 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
225
41f63475
FE		 226 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
227 if (err) {
228 pr_err("Failed to request the USB OTG reset gpio\n");
229 return err;
230 }
231
232 err = gpio_direction_output(USBOTG_RST_B, 0);
233 if (err) {
234 pr_err("Failed to drive the USB OTG reset gpio\n");
235 goto usbotg_free_reset;
236 }
237
a2ef4562
ML		 238 mdelay(1);
239 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 240 return 0;
241
242usbotg_free_reset:
243 gpio_free(USBOTG_RST_B);
244 return err;
a2ef4562
ML		 245}
246
4bd597b6
SH		 247#if defined(CONFIG_USB_ULPI)
248static int mx31_3ds_otg_init(struct platform_device *pdev)
249{
250 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
251}
252
253static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 254{
255 int err;
256
257 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
258 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
259 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
260 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
261 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
262 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
263 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
264 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
265 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
266 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
267 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
268 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
269
270 err = gpio_request(USBH2_RST_B, "usbh2-reset");
271 if (err) {
272 pr_err("Failed to request the USB Host 2 reset gpio\n");
273 return err;
274 }
275
276 err = gpio_direction_output(USBH2_RST_B, 0);
277 if (err) {
278 pr_err("Failed to drive the USB Host 2 reset gpio\n");
279 goto usbotg_free_reset;
280 }
281
282 mdelay(1);
283 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 284
285 mdelay(10);
286
287 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 288
289usbotg_free_reset:
290 gpio_free(USBH2_RST_B);
291 return err;
292}
293
1c50e672 294static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 295 .init = mx31_3ds_otg_init,
1c50e672 296 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 297};
0d95b75e
FE		 298
299static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
300 .init = mx31_3ds_host2_init,
301 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 302};
1c50e672
FE		 303#endif
304
9e1dde33 305static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 306 .operating_mode = FSL_USB2_DR_DEVICE,
307 .phy_mode = FSL_USB2_PHY_ULPI,
308};
309
1c50e672
FE		 310static int otg_mode_host;
311
312static int __init mx31_3ds_otg_mode(char *options)
313{
314 if (!strcmp(options, "host"))
315 otg_mode_host = 1;
316 else if (!strcmp(options, "device"))
317 otg_mode_host = 0;
318 else
319 pr_info("otg_mode neither \"host\" nor \"device\". "
320 "Defaulting to device\n");
321 return 0;
322}
323__setup("otg_mode=", mx31_3ds_otg_mode);
324
16cf5c41 325static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 326 .flags = IMXUART_HAVE_RTSCTS,
327};
1553a1ec 328
3d943024
FE		 329static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
330 .bitrate = 100000,
331};
332
e134fb2b 333static void __init mx31_3ds_init(void)
1553a1ec 334{
11a332ad
AP		 335 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
336 "mx31_3ds");
153fa1d8 337
16cf5c41 338 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 339 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 340
4a74bddc 341 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 342 spi_register_board_info(mx31_3ds_spi_devs,
343 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 344
d690b4c4 345 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 346
a2ef4562 347 mx31_3ds_usbotg_init();
1c50e672
FE		 348#if defined(CONFIG_USB_ULPI)
349 if (otg_mode_host) {
350 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
351 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
352
353 imx31_add_mxc_ehci_otg(&otg_pdata);
354 }
0d95b75e
FE		 355 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
356 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
357 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
1c50e672
FE		 358#endif
359 if (!otg_mode_host)
360 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 361
b8be7b9a
RP		 362 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
363 printk(KERN_WARNING "Init of the debug board failed, all "
364 "devices on the debug board are unusable.\n");
bfdde3a9 365 imx31_add_imx2_wdt(NULL);
3d943024 366 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
1553a1ec
FE		 367}
368
11a332ad 369static void __init mx31_3ds_timer_init(void)
1553a1ec 370{
30c730f8 371 mx31_clocks_init(26000000);
1553a1ec
FE		 372}
373
11a332ad
AP		 374static struct sys_timer mx31_3ds_timer = {
375 .init = mx31_3ds_timer_init,
1553a1ec
FE		 376};
377
1553a1ec
FE		 378MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
379 /* Maintainer: Freescale Semiconductor, Inc. */
97976e22
UKK		 380 .boot_params = MX3x_PHYS_OFFSET + 0x100,
381 .map_io = mx31_map_io,
382 .init_early = imx31_init_early,
383 .init_irq = mx31_init_irq,
384 .timer = &mx31_3ds_timer,
e134fb2b 385 .init_machine = mx31_3ds_init,
1553a1ec 386MACHINE_END
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