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mfd: mfd_cell is now implicitly available to janz drivers
[linux-2.6-block.git] / arch / arm / mach-mx3 / mach-mx31_3ds.c
CommitLineData
1553a1ec
FE		 1/*
2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
1553a1ec
FE		 13 */
14
a2ef4562 15#include <linux/delay.h>
1553a1ec
FE		 16#include <linux/types.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/irq.h>
135cad36 20#include <linux/gpio.h>
2b0c3677 21#include <linux/platform_device.h>
ae7a3f13
AP		 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h>
e42010e0 24#include <linux/spi/l4f00242t03.h>
ae7a3f13 25#include <linux/regulator/machine.h>
1c50e672
FE		 26#include <linux/usb/otg.h>
27#include <linux/usb/ulpi.h>
164f7b52
AP		 28#include <linux/memblock.h>
29
30#include <media/soc_camera.h>
1553a1ec
FE		 31
32#include <mach/hardware.h>
33#include <asm/mach-types.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/time.h>
36#include <asm/memory.h>
37#include <asm/mach/map.h>
38#include <mach/common.h>
1553a1ec 39#include <mach/iomux-mx3.h>
c5d38f08 40#include <mach/3ds_debugboard.h>
1c50e672 41#include <mach/ulpi.h>
0ce88b34 42#include <mach/mmc.h>
e42010e0
AP		 43#include <mach/ipu.h>
44#include <mach/mx3fb.h>
164f7b52 45#include <mach/mx3_camera.h>
a2ceeef5
UKK		 46
47#include "devices-imx31.h"
1553a1ec
FE		 48#include "devices.h"
49
b396dc45
UKK		 50/* CPLD IRQ line for external uart, external ethernet etc */
51#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
52
11a332ad 53static int mx31_3ds_pins[] = {
153fa1d8 54 /* UART1 */
63d97667
VL		 55 MX31_PIN_CTS1__CTS1,
56 MX31_PIN_RTS1__RTS1,
57 MX31_PIN_TXD1__TXD1,
135cad36
ML		 58 MX31_PIN_RXD1__RXD1,
59 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
e42010e0
AP		 60 /*SPI0*/
61 MX31_PIN_CSPI1_SCLK__SCLK,
62 MX31_PIN_CSPI1_MOSI__MOSI,
63 MX31_PIN_CSPI1_MISO__MISO,
64 MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
65 MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
a1ac4424
AP		 66 /* SPI 1 */
67 MX31_PIN_CSPI2_SCLK__SCLK,
68 MX31_PIN_CSPI2_MOSI__MOSI,
69 MX31_PIN_CSPI2_MISO__MISO,
70 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
71 MX31_PIN_CSPI2_SS0__SS0,
72 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
ae7a3f13
AP		 73 /* MC13783 IRQ */
74 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
a2ef4562
ML		 75 /* USB OTG reset */
76 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
77 /* USB OTG */
78 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
79 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
80 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
81 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
82 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
83 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
84 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
85 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
86 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
87 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
88 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
89 MX31_PIN_USBOTG_STP__USBOTG_STP,
54c1f636
AP		 90 /*Keyboard*/
91 MX31_PIN_KEY_ROW0_KEY_ROW0,
92 MX31_PIN_KEY_ROW1_KEY_ROW1,
93 MX31_PIN_KEY_ROW2_KEY_ROW2,
94 MX31_PIN_KEY_COL0_KEY_COL0,
95 MX31_PIN_KEY_COL1_KEY_COL1,
96 MX31_PIN_KEY_COL2_KEY_COL2,
97 MX31_PIN_KEY_COL3_KEY_COL3,
0d95b75e
FE		 98 /* USB Host 2 */
99 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
100 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
101 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
102 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
103 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
104 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
105 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
106 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
107 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
108 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
109 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
110 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
111 /* USB Host2 reset */
112 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
3d943024
FE		 113 /* I2C1 */
114 MX31_PIN_I2C_CLK__I2C1_SCL,
115 MX31_PIN_I2C_DAT__I2C1_SDA,
0ce88b34
AP		 116 /* SDHC1 */
117 MX31_PIN_SD1_DATA3__SD1_DATA3,
118 MX31_PIN_SD1_DATA2__SD1_DATA2,
119 MX31_PIN_SD1_DATA1__SD1_DATA1,
120 MX31_PIN_SD1_DATA0__SD1_DATA0,
121 MX31_PIN_SD1_CLK__SD1_CLK,
122 MX31_PIN_SD1_CMD__SD1_CMD,
123 MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
124 MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
e42010e0
AP		 125 /* Framebuffer */
126 MX31_PIN_LD0__LD0,
127 MX31_PIN_LD1__LD1,
128 MX31_PIN_LD2__LD2,
129 MX31_PIN_LD3__LD3,
130 MX31_PIN_LD4__LD4,
131 MX31_PIN_LD5__LD5,
132 MX31_PIN_LD6__LD6,
133 MX31_PIN_LD7__LD7,
134 MX31_PIN_LD8__LD8,
135 MX31_PIN_LD9__LD9,
136 MX31_PIN_LD10__LD10,
137 MX31_PIN_LD11__LD11,
138 MX31_PIN_LD12__LD12,
139 MX31_PIN_LD13__LD13,
140 MX31_PIN_LD14__LD14,
141 MX31_PIN_LD15__LD15,
142 MX31_PIN_LD16__LD16,
143 MX31_PIN_LD17__LD17,
144 MX31_PIN_VSYNC3__VSYNC3,
145 MX31_PIN_HSYNC__HSYNC,
146 MX31_PIN_FPSHIFT__FPSHIFT,
147 MX31_PIN_CONTRAST__CONTRAST,
164f7b52
AP		 148 /* CSI */
149 MX31_PIN_CSI_D6__CSI_D6,
150 MX31_PIN_CSI_D7__CSI_D7,
151 MX31_PIN_CSI_D8__CSI_D8,
152 MX31_PIN_CSI_D9__CSI_D9,
153 MX31_PIN_CSI_D10__CSI_D10,
154 MX31_PIN_CSI_D11__CSI_D11,
155 MX31_PIN_CSI_D12__CSI_D12,
156 MX31_PIN_CSI_D13__CSI_D13,
157 MX31_PIN_CSI_D14__CSI_D14,
158 MX31_PIN_CSI_D15__CSI_D15,
159 MX31_PIN_CSI_HSYNC__CSI_HSYNC,
160 MX31_PIN_CSI_MCLK__CSI_MCLK,
161 MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
162 MX31_PIN_CSI_VSYNC__CSI_VSYNC,
163 MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
164 IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
165};
166
167/*
168 * Camera support
169 */
170static phys_addr_t mx3_camera_base __initdata;
171#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
172
173#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
174#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
175
176static struct gpio mx31_3ds_camera_gpios[] = {
177 { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
178 { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
179};
180
181static int __init mx31_3ds_camera_alloc_dma(void)
182{
183 int dma;
184
185 if (!mx3_camera_base)
186 return -ENOMEM;
187
188 dma = dma_declare_coherent_memory(&mx3_camera.dev,
189 mx3_camera_base, mx3_camera_base,
190 MX31_3DS_CAMERA_BUF_SIZE,
191 DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
192
193 if (!(dma & DMA_MEMORY_MAP))
194 return -ENOMEM;
195
196 return 0;
197}
198
199static int mx31_3ds_camera_power(struct device *dev, int on)
200{
201 /* enable or disable the camera */
202 pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
203 gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
204
205 if (!on)
206 goto out;
207
208 /* If enabled, give a reset impulse */
209 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
210 msleep(20);
211 gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
212 msleep(100);
213
214out:
215 return 0;
216}
217
218static struct i2c_board_info mx31_3ds_i2c_camera = {
219 I2C_BOARD_INFO("ov2640", 0x30),
220};
221
222static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
223 { .supply = "cmos_vcore" },
224 { .supply = "cmos_2v8" },
225};
226
227static struct soc_camera_link iclink_ov2640 = {
228 .bus_id = 0,
229 .board_info = &mx31_3ds_i2c_camera,
230 .i2c_adapter_id = 0,
231 .power = mx31_3ds_camera_power,
232 .regulators = mx31_3ds_camera_regs,
233 .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
234};
235
236static struct platform_device mx31_3ds_ov2640 = {
237 .name = "soc-camera-pdrv",
238 .id = 0,
239 .dev = {
240 .platform_data = &iclink_ov2640,
241 },
242};
243
244struct mx3_camera_pdata mx31_3ds_camera_pdata = {
245 .dma_dev = &mx3_ipu.dev,
246 .flags = MX3_CAMERA_DATAWIDTH_10,
247 .mclk_10khz = 2600,
e42010e0
AP		 248};
249
250/*
251 * FB support
252 */
253static const struct fb_videomode fb_modedb[] = {
254 { /* 480x640 @ 60 Hz */
255 .name = "Epson-VGA",
256 .refresh = 60,
257 .xres = 480,
258 .yres = 640,
259 .pixclock = 41701,
260 .left_margin = 20,
261 .right_margin = 41,
262 .upper_margin = 10,
263 .lower_margin = 5,
264 .hsync_len = 20,
265 .vsync_len = 10,
266 .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
267 .vmode = FB_VMODE_NONINTERLACED,
268 .flag = 0,
269 },
270};
271
272static struct ipu_platform_data mx3_ipu_data = {
273 .irq_base = MXC_IPU_IRQ_START,
274};
275
276static struct mx3fb_platform_data mx3fb_pdata = {
277 .dma_dev = &mx3_ipu.dev,
278 .name = "Epson-VGA",
279 .mode = fb_modedb,
280 .num_modes = ARRAY_SIZE(fb_modedb),
281};
282
283/* LCD */
284static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
285 .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
286 .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
287 .core_supply = "lcd_2v8",
288 .io_supply = "vdd_lcdio",
0ce88b34
AP		 289};
290
291/*
292 * Support for SD card slot in personality board
293 */
294#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
295#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
296
297static struct gpio mx31_3ds_sdhc1_gpios[] = {
298 { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
299 { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
300};
301
302static int mx31_3ds_sdhc1_init(struct device *dev,
303 irq_handler_t detect_irq,
304 void *data)
305{
306 int ret;
307
308 ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
309 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
310 if (ret) {
311 pr_warning("Unable to request the SD/MMC GPIOs.\n");
312 return ret;
313 }
314
315 ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
316 detect_irq, IRQF_DISABLED |
317 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
318 "sdhc1-detect", data);
319 if (ret) {
320 pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
321 goto gpio_free;
322 }
323
324 return 0;
325
326gpio_free:
327 gpio_free_array(mx31_3ds_sdhc1_gpios,
328 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
329 return ret;
330}
331
332static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
333{
334 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
335 gpio_free_array(mx31_3ds_sdhc1_gpios,
336 ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
337}
338
339static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
340{
341 /*
342 * While the voltage stuff is done by the driver, activate the
343 * Buffer Enable Pin only if there is a card in slot to fix the card
344 * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
345 * Done here because at this stage we have for sure a debounced value
346 * of the presence of the card, showed by the value of vdd.
347 * 7 == ilog2(MMC_VDD_165_195)
348 */
349 if (vdd > 7)
350 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
351 else
352 gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
353}
354
355static struct imxmmc_platform_data sdhc1_pdata = {
356 .init = mx31_3ds_sdhc1_init,
357 .exit = mx31_3ds_sdhc1_exit,
358 .setpower = mx31_3ds_sdhc1_setpower,
54c1f636
AP		 359};
360
361/*
362 * Matrix keyboard
363 */
364
365static const uint32_t mx31_3ds_keymap[] = {
366 KEY(0, 0, KEY_UP),
367 KEY(0, 1, KEY_DOWN),
368 KEY(1, 0, KEY_RIGHT),
369 KEY(1, 1, KEY_LEFT),
370 KEY(1, 2, KEY_ENTER),
371 KEY(2, 0, KEY_F6),
372 KEY(2, 1, KEY_F8),
373 KEY(2, 2, KEY_F9),
374 KEY(2, 3, KEY_F10),
375};
376
d690b4c4 377static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
54c1f636
AP		 378 .keymap = mx31_3ds_keymap,
379 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
ae7a3f13
AP		 380};
381
382/* Regulators */
383static struct regulator_init_data pwgtx_init = {
384 .constraints = {
385 .boot_on = 1,
386 .always_on = 1,
387 },
388};
389
0d95b75e
FE		 390static struct regulator_init_data gpo_init = {
391 .constraints = {
392 .boot_on = 1,
393 .always_on = 1,
394 }
395};
396
0ce88b34
AP		 397static struct regulator_consumer_supply vmmc2_consumers[] = {
398 REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
399};
400
401static struct regulator_init_data vmmc2_init = {
402 .constraints = {
403 .min_uV = 3000000,
404 .max_uV = 3000000,
405 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
406 REGULATOR_CHANGE_STATUS,
407 },
408 .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
409 .consumer_supplies = vmmc2_consumers,
410};
411
e42010e0
AP		 412static struct regulator_consumer_supply vmmc1_consumers[] = {
413 REGULATOR_SUPPLY("lcd_2v8", NULL),
164f7b52 414 REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
e42010e0
AP		 415};
416
417static struct regulator_init_data vmmc1_init = {
418 .constraints = {
419 .min_uV = 2800000,
420 .max_uV = 2800000,
421 .apply_uV = 1,
422 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
423 REGULATOR_CHANGE_STATUS,
424 },
425 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
426 .consumer_supplies = vmmc1_consumers,
427};
428
429static struct regulator_consumer_supply vgen_consumers[] = {
430 REGULATOR_SUPPLY("vdd_lcdio", NULL),
431};
432
433static struct regulator_init_data vgen_init = {
434 .constraints = {
435 .min_uV = 1800000,
436 .max_uV = 1800000,
437 .apply_uV = 1,
438 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
439 REGULATOR_CHANGE_STATUS,
440 },
441 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
442 .consumer_supplies = vgen_consumers,
443};
444
164f7b52
AP		 445static struct regulator_consumer_supply vvib_consumers[] = {
446 REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
447};
448
449static struct regulator_init_data vvib_init = {
450 .constraints = {
451 .min_uV = 1300000,
452 .max_uV = 1300000,
453 .apply_uV = 1,
454 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
455 REGULATOR_CHANGE_STATUS,
456 },
457 .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
458 .consumer_supplies = vvib_consumers,
459};
460
5836372e 461static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
ae7a3f13 462 {
57c78e35 463 .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
ae7a3f13
AP		 464 .init_data = &pwgtx_init,
465 }, {
57c78e35 466 .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
ae7a3f13 467 .init_data = &pwgtx_init,
0d95b75e
FE		 468 }, {
469
c97b7393 470 .id = MC13783_REG_GPO1, /* Turn on 1.8V */
0d95b75e
FE		 471 .init_data = &gpo_init,
472 }, {
c97b7393 473 .id = MC13783_REG_GPO3, /* Turn on 3.3V */
0d95b75e 474 .init_data = &gpo_init,
0ce88b34
AP		 475 }, {
476 .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
477 .init_data = &vmmc2_init,
e42010e0
AP		 478 }, {
479 .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
480 .init_data = &vmmc1_init,
481 }, {
482 .id = MC13783_REG_VGEN, /* Power LCD */
483 .init_data = &vgen_init,
164f7b52
AP		 484 }, {
485 .id = MC13783_REG_VVIB, /* Power CMOS */
486 .init_data = &vvib_init,
ae7a3f13
AP		 487 },
488};
489
490/* MC13783 */
5836372e 491static struct mc13xxx_platform_data mc13783_pdata __initdata = {
ae7a3f13
AP		 492 .regulators = mx31_3ds_regulators,
493 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
5836372e 494 .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_TOUCHSCREEN
a1ac4424
AP		 495};
496
497/* SPI */
e42010e0
AP		 498static int spi0_internal_chipselect[] = {
499 MXC_SPI_CS(2),
500};
501
502static const struct spi_imx_master spi0_pdata __initconst = {
503 .chipselect = spi0_internal_chipselect,
504 .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
505};
506
a1ac4424
AP		 507static int spi1_internal_chipselect[] = {
508 MXC_SPI_CS(0),
509 MXC_SPI_CS(2),
510};
511
06606ff1 512static const struct spi_imx_master spi1_pdata __initconst = {
a1ac4424
AP		 513 .chipselect = spi1_internal_chipselect,
514 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
63d97667
VL		 515};
516
ae7a3f13
AP		 517static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
518 {
519 .modalias = "mc13783",
520 .max_speed_hz = 1000000,
521 .bus_num = 1,
522 .chip_select = 1, /* SS2 */
523 .platform_data = &mc13783_pdata,
524 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
525 .mode = SPI_CS_HIGH,
e42010e0
AP		 526 }, {
527 .modalias = "l4f00242t03",
528 .max_speed_hz = 5000000,
529 .bus_num = 0,
530 .chip_select = 0, /* SS2 */
531 .platform_data = &mx31_3ds_l4f00242t03_pdata,
ae7a3f13
AP		 532 },
533};
534
a1b67b95
AP		 535/*
536 * NAND Flash
537 */
a2ceeef5
UKK		 538static const struct mxc_nand_platform_data
539mx31_3ds_nand_board_info __initconst = {
a1b67b95
AP		 540 .width = 1,
541 .hw_ecc = 1,
542#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
543 .flash_bbt = 1,
544#endif
545};
546
a2ef4562
ML		 547/*
548 * USB OTG
549 */
550
551#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
552 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
553
554#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
0d95b75e 555#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
a2ef4562 556
41f63475 557static int mx31_3ds_usbotg_init(void)
a2ef4562 558{
41f63475
FE		 559 int err;
560
a2ef4562
ML		 561 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
562 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
563 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
564 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
565 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
566 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
567 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
568 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
569 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
570 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
571 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
572 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
573
41f63475
FE		 574 err = gpio_request(USBOTG_RST_B, "otgusb-reset");
575 if (err) {
576 pr_err("Failed to request the USB OTG reset gpio\n");
577 return err;
578 }
579
580 err = gpio_direction_output(USBOTG_RST_B, 0);
581 if (err) {
582 pr_err("Failed to drive the USB OTG reset gpio\n");
583 goto usbotg_free_reset;
584 }
585
a2ef4562
ML		 586 mdelay(1);
587 gpio_set_value(USBOTG_RST_B, 1);
41f63475
FE		 588 return 0;
589
590usbotg_free_reset:
591 gpio_free(USBOTG_RST_B);
592 return err;
a2ef4562
ML		 593}
594
4bd597b6
SH		 595static int mx31_3ds_otg_init(struct platform_device *pdev)
596{
597 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
598}
599
600static int mx31_3ds_host2_init(struct platform_device *pdev)
0d95b75e
FE		 601{
602 int err;
603
604 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
605 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
606 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
607 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
608 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
609 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
610 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
611 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
612 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
613 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
614 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
615 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
616
617 err = gpio_request(USBH2_RST_B, "usbh2-reset");
618 if (err) {
619 pr_err("Failed to request the USB Host 2 reset gpio\n");
620 return err;
621 }
622
623 err = gpio_direction_output(USBH2_RST_B, 0);
624 if (err) {
625 pr_err("Failed to drive the USB Host 2 reset gpio\n");
626 goto usbotg_free_reset;
627 }
628
629 mdelay(1);
630 gpio_set_value(USBH2_RST_B, 1);
4bd597b6
SH		 631
632 mdelay(10);
633
634 return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
0d95b75e
FE		 635
636usbotg_free_reset:
637 gpio_free(USBH2_RST_B);
638 return err;
639}
640
1c50e672 641static struct mxc_usbh_platform_data otg_pdata __initdata = {
4bd597b6 642 .init = mx31_3ds_otg_init,
1c50e672 643 .portsc = MXC_EHCI_MODE_ULPI,
1c50e672 644};
0d95b75e
FE		 645
646static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
647 .init = mx31_3ds_host2_init,
648 .portsc = MXC_EHCI_MODE_ULPI,
0d95b75e 649};
1c50e672 650
9e1dde33 651static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
a2ef4562
ML		 652 .operating_mode = FSL_USB2_DR_DEVICE,
653 .phy_mode = FSL_USB2_PHY_ULPI,
654};
655
1c50e672
FE		 656static int otg_mode_host;
657
658static int __init mx31_3ds_otg_mode(char *options)
659{
660 if (!strcmp(options, "host"))
661 otg_mode_host = 1;
662 else if (!strcmp(options, "device"))
663 otg_mode_host = 0;
664 else
665 pr_info("otg_mode neither \"host\" nor \"device\". "
666 "Defaulting to device\n");
667 return 0;
668}
669__setup("otg_mode=", mx31_3ds_otg_mode);
670
16cf5c41 671static const struct imxuart_platform_data uart_pdata __initconst = {
153fa1d8
ML		 672 .flags = IMXUART_HAVE_RTSCTS,
673};
1553a1ec 674
3d943024
FE		 675static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
676 .bitrate = 100000,
677};
678
164f7b52
AP		 679static struct platform_device *devices[] __initdata = {
680 &mx31_3ds_ov2640,
681};
682
e134fb2b 683static void __init mx31_3ds_init(void)
1553a1ec 684{
164f7b52
AP		 685 int ret;
686
11a332ad
AP		 687 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
688 "mx31_3ds");
153fa1d8 689
16cf5c41 690 imx31_add_imx_uart0(&uart_pdata);
a2ceeef5 691 imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
ae7a3f13 692
4a74bddc 693 imx31_add_spi_imx1(&spi1_pdata);
ae7a3f13
AP		 694 spi_register_board_info(mx31_3ds_spi_devs,
695 ARRAY_SIZE(mx31_3ds_spi_devs));
135cad36 696
164f7b52
AP		 697 platform_add_devices(devices, ARRAY_SIZE(devices));
698
d690b4c4 699 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
54c1f636 700
a2ef4562 701 mx31_3ds_usbotg_init();
1c50e672 702 if (otg_mode_host) {
48f6b099
SH		 703 otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
704 ULPI_OTG_DRVVBUS_EXT);
705 if (otg_pdata.otg)
706 imx31_add_mxc_ehci_otg(&otg_pdata);
1c50e672 707 }
48f6b099
SH		 708 usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
709 ULPI_OTG_DRVVBUS_EXT);
710 if (usbh2_pdata.otg)
711 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
712
1c50e672
FE		 713 if (!otg_mode_host)
714 imx31_add_fsl_usb2_udc(&usbotg_pdata);
a2ef4562 715
b8be7b9a
RP		 716 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
717 printk(KERN_WARNING "Init of the debug board failed, all "
718 "devices on the debug board are unusable.\n");
bfdde3a9 719 imx31_add_imx2_wdt(NULL);
3d943024 720 imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
0ce88b34 721 imx31_add_mxc_mmc(0, &sdhc1_pdata);
e42010e0
AP		 722
723 imx31_add_spi_imx0(&spi0_pdata);
724 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
725 mxc_register_device(&mx3_fb, &mx3fb_pdata);
164f7b52
AP		 726
727 /* CSI */
728 /* Camera power: default - off */
729 ret = gpio_request_array(mx31_3ds_camera_gpios,
730 ARRAY_SIZE(mx31_3ds_camera_gpios));
731 if (ret) {
732 pr_err("Failed to request camera gpios");
733 iclink_ov2640.power = NULL;
734 }
735
736 if (!mx31_3ds_camera_alloc_dma())
737 mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
738 else
739 pr_err("Failed to allocate dma memory for camera");
1553a1ec
FE		 740}
741
11a332ad 742static void __init mx31_3ds_timer_init(void)
1553a1ec 743{
30c730f8 744 mx31_clocks_init(26000000);
1553a1ec
FE		 745}
746
11a332ad
AP		 747static struct sys_timer mx31_3ds_timer = {
748 .init = mx31_3ds_timer_init,
1553a1ec
FE		 749};
750
164f7b52
AP		 751static void __init mx31_3ds_reserve(void)
752{
753 /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
754 mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
755 MX31_3DS_CAMERA_BUF_SIZE);
756 memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
757 memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
758}
759
1553a1ec
FE		 760MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
761 /* Maintainer: Freescale Semiconductor, Inc. */
97976e22
UKK		 762 .boot_params = MX3x_PHYS_OFFSET + 0x100,
763 .map_io = mx31_map_io,
764 .init_early = imx31_init_early,
765 .init_irq = mx31_init_irq,
766 .timer = &mx31_3ds_timer,
e134fb2b 767 .init_machine = mx31_3ds_init,
164f7b52 768 .reserve = mx31_3ds_reserve,
1553a1ec 769MACHINE_END
Linux 6.x block layer and io_uring tree(s)