[linux-2.6-block.git] / arch / arm / mach-mx3 / iomux-imx31.c

/*
 * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
 * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA 02110-1301, USA.
 */

#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
#include <mach/iomux-mx3.h>

/*
 * IOMUX register (base) addresses
 */
#define IOMUX_BASE	MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
#define IOMUXINT_OBS1	(IOMUX_BASE + 0x000)
#define IOMUXINT_OBS2	(IOMUX_BASE + 0x004)
#define IOMUXGPR	(IOMUX_BASE + 0x008)
#define IOMUXSW_MUX_CTL	(IOMUX_BASE + 0x00C)
#define IOMUXSW_PAD_CTL	(IOMUX_BASE + 0x154)

static DEFINE_SPINLOCK(gpio_mux_lock);

#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)

unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
/*
 * set the mode for a IOMUX pin.
 */
int mxc_iomux_mode(unsigned int pin_mode)
{
	u32 field, l, mode, ret = 0;
	void __iomem *reg;

	reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
	field = pin_mode & 0x3;
	mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;

	spin_lock(&gpio_mux_lock);

	l = __raw_readl(reg);
	l &= ~(0xff << (field * 8));
	l |= mode << (field * 8);
	__raw_writel(l, reg);

	spin_unlock(&gpio_mux_lock);

	return ret;
}
EXPORT_SYMBOL(mxc_iomux_mode);

/*
 * This function configures the pad value for a IOMUX pin.
 */
void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
{
	u32 field, l;
	void __iomem *reg;

	pin &= IOMUX_PADNUM_MASK;
	reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
	field = (pin + 2) % 3;

	pr_debug("%s: reg offset = 0x%x, field = %d\n",
			__func__, (pin + 2) / 3, field);

	spin_lock(&gpio_mux_lock);

	l = __raw_readl(reg);
	l &= ~(0x1ff << (field * 10));
	l |= config << (field * 10);
	__raw_writel(l, reg);

	spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_pad);

/*
 * allocs a single pin:
 * 	- reserves the pin so that it is not claimed by another driver
 * 	- setups the iomux according to the configuration
 */
int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
{
	unsigned pad = pin & IOMUX_PADNUM_MASK;

	if (pad >= (PIN_MAX + 1)) {
		printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
			pad, label ? label : "?");
		return -EINVAL;
	}

	if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
		printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
			pad, label ? label : "?");
		return -EBUSY;
	}
	mxc_iomux_mode(pin);

	return 0;
}
EXPORT_SYMBOL(mxc_iomux_alloc_pin);

int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
		const char *label)
{
	unsigned int *p = pin_list;
	int i;
	int ret = -EINVAL;

	for (i = 0; i < count; i++) {
		ret = mxc_iomux_alloc_pin(*p, label);
		if (ret)
			goto setup_error;
		p++;
	}
	return 0;

setup_error:
	mxc_iomux_release_multiple_pins(pin_list, i);
	return ret;
}
EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);

void mxc_iomux_release_pin(const unsigned int pin)
{
	unsigned pad = pin & IOMUX_PADNUM_MASK;

	if (pad < (PIN_MAX + 1))
		clear_bit(pad, mxc_pin_alloc_map);
}
EXPORT_SYMBOL(mxc_iomux_release_pin);

void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
{
	unsigned int *p = pin_list;
	int i;

	for (i = 0; i < count; i++) {
		mxc_iomux_release_pin(*p);
		p++;
	}
}
EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);

/*
 * This function enables/disables the general purpose function for a particular
 * signal.
 */
void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
{
	u32 l;

	spin_lock(&gpio_mux_lock);
	l = __raw_readl(IOMUXGPR);
	if (en)
		l |= gp;
	else
		l &= ~gp;

	__raw_writel(l, IOMUXGPR);
	spin_unlock(&gpio_mux_lock);
}
EXPORT_SYMBOL(mxc_iomux_set_gpr);
Commit	Line	Data
90292ea6 SH	1	/*
	2	* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
b7222631	4	* Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
90292ea6 SH	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	18	* MA 02110-1301, USA.
	19	*/
	20
	21	#include <linux/module.h>
	22	#include <linux/spinlock.h>
	23	#include <linux/io.h>
b7222631	24	#include <linux/kernel.h>
a09e64fb RK	25	#include <mach/hardware.h>
	26	#include <mach/gpio.h>
	27	#include <mach/iomux-mx3.h>
90292ea6 SH	28
	29	/*
	30	* IOMUX register (base) addresses
	31	*/
1273e768	32	#define IOMUX_BASE MX31_IO_ADDRESS(MX31_IOMUXC_BASE_ADDR)
90292ea6 SH	33	#define IOMUXINT_OBS1 (IOMUX_BASE + 0x000)
	34	#define IOMUXINT_OBS2 (IOMUX_BASE + 0x004)
	35	#define IOMUXGPR (IOMUX_BASE + 0x008)
	36	#define IOMUXSW_MUX_CTL (IOMUX_BASE + 0x00C)
	37	#define IOMUXSW_PAD_CTL (IOMUX_BASE + 0x154)
	38
	39	static DEFINE_SPINLOCK(gpio_mux_lock);
	40
	41	#define IOMUX_REG_MASK (IOMUX_PADNUM_MASK & ~0x3)
b7222631 VL	42
b7222631 VL	43	unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
90292ea6 SH	44	/*
	45	* set the mode for a IOMUX pin.
	46	*/
	47	int mxc_iomux_mode(unsigned int pin_mode)
	48	{
defa8c30 LF	49	u32 field, l, mode, ret = 0;
defa8c30 LF	50	void __iomem *reg;
90292ea6 SH	51
	52	reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK);
	53	field = pin_mode & 0x3;
	54	mode = (pin_mode & IOMUX_MODE_MASK) >> IOMUX_MODE_SHIFT;
	55
90292ea6 SH	56	spin_lock(&gpio_mux_lock);
	57
	58	l = __raw_readl(reg);
	59	l &= ~(0xff << (field * 8));
	60	l \|= mode << (field * 8);
	61	__raw_writel(l, reg);
	62
	63	spin_unlock(&gpio_mux_lock);
	64
	65	return ret;
	66	}
	67	EXPORT_SYMBOL(mxc_iomux_mode);
	68
	69	/*
	70	* This function configures the pad value for a IOMUX pin.
	71	*/
	72	void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
	73	{
defa8c30 LF	74	u32 field, l;
defa8c30 LF	75	void __iomem *reg;
90292ea6	76
4a7b98d7 GL	77	pin &= IOMUX_PADNUM_MASK;
4a7b98d7 GL	78	reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
90292ea6 SH	79	field = (pin + 2) % 3;
90292ea6 SH	80
4a7b98d7	81	pr_debug("%s: reg offset = 0x%x, field = %d\n",
90292ea6 SH	82	__func__, (pin + 2) / 3, field);
	83
	84	spin_lock(&gpio_mux_lock);
	85
	86	l = __raw_readl(reg);
4a7b98d7 GL	87	l &= ~(0x1ff << (field * 10));
4a7b98d7 GL	88	l \|= config << (field * 10);
90292ea6 SH	89	__raw_writel(l, reg);
	90
	91	spin_unlock(&gpio_mux_lock);
	92	}
	93	EXPORT_SYMBOL(mxc_iomux_set_pad);
	94
b7222631	95	/*
ef754d63	96	* allocs a single pin:
b7222631 VL	97	* - reserves the pin so that it is not claimed by another driver
b7222631 VL	98	* - setups the iomux according to the configuration
b7222631	99	*/
ef754d63	100	int mxc_iomux_alloc_pin(const unsigned int pin, const char *label)
b7222631 VL	101	{
b7222631 VL	102	unsigned pad = pin & IOMUX_PADNUM_MASK;
b7222631 VL	103
	104	if (pad >= (PIN_MAX + 1)) {
	105	printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
	106	pad, label ? label : "?");
	107	return -EINVAL;
	108	}
	109
	110	if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
	111	printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
	112	pad, label ? label : "?");
ef754d63	113	return -EBUSY;
b7222631 VL	114	}
	115	mxc_iomux_mode(pin);
	116
b7222631 VL	117	return 0;
b7222631 VL	118	}
ef754d63	119	EXPORT_SYMBOL(mxc_iomux_alloc_pin);
b7222631 VL	120
	121	int mxc_iomux_setup_multiple_pins(unsigned int *pin_list, unsigned count,
	122	const char *label)
	123	{
	124	unsigned int *p = pin_list;
	125	int i;
	126	int ret = -EINVAL;
	127
	128	for (i = 0; i < count; i++) {
ef754d63 VL	129	ret = mxc_iomux_alloc_pin(*p, label);
ef754d63 VL	130	if (ret)
b7222631 VL	131	goto setup_error;
	132	p++;
	133	}
	134	return 0;
	135
	136	setup_error:
	137	mxc_iomux_release_multiple_pins(pin_list, i);
	138	return ret;
	139	}
	140	EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
	141
	142	void mxc_iomux_release_pin(const unsigned int pin)
	143	{
	144	unsigned pad = pin & IOMUX_PADNUM_MASK;
b7222631 VL	145
	146	if (pad < (PIN_MAX + 1))
	147	clear_bit(pad, mxc_pin_alloc_map);
b7222631 VL	148	}
	149	EXPORT_SYMBOL(mxc_iomux_release_pin);
	150
	151	void mxc_iomux_release_multiple_pins(unsigned int *pin_list, int count)
	152	{
	153	unsigned int *p = pin_list;
	154	int i;
	155
	156	for (i = 0; i < count; i++) {
	157	mxc_iomux_release_pin(*p);
	158	p++;
	159	}
	160	}
	161	EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
	162
90292ea6 SH	163	/*
	164	* This function enables/disables the general purpose function for a particular
	165	* signal.
	166	*/
	167	void mxc_iomux_set_gpr(enum iomux_gp_func gp, bool en)
	168	{
	169	u32 l;
	170
	171	spin_lock(&gpio_mux_lock);
	172	l = __raw_readl(IOMUXGPR);
	173	if (en)
	174	l \|= gp;
	175	else
	176	l &= ~gp;
	177
	178	__raw_writel(l, IOMUXGPR);
	179	spin_unlock(&gpio_mux_lock);
	180	}
	181	EXPORT_SYMBOL(mxc_iomux_set_gpr);