Commit | Line | Data |
---|---|---|
e3d13ff4 SH |
1 | /* |
2 | * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Sascha Hauer, kernel@pengutronix.de | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
17 | * Boston, MA 02110-1301, USA. | |
18 | */ | |
19 | ||
eb05bbeb | 20 | #include <linux/dma-mapping.h> |
e3d13ff4 SH |
21 | #include <linux/module.h> |
22 | #include <linux/platform_device.h> | |
23 | #include <linux/serial.h> | |
07bd1a6c | 24 | #include <linux/gpio.h> |
a09e64fb | 25 | #include <mach/hardware.h> |
80b02c17 | 26 | #include <mach/irqs.h> |
45001e92 | 27 | #include <mach/common.h> |
9c70e227 | 28 | #include <mach/mx3_camera.h> |
e3d13ff4 | 29 | |
87bbb197 SH |
30 | #include "devices.h" |
31 | ||
16cf5c41 | 32 | #if defined(CONFIG_ARCH_MX35) |
e3d13ff4 SH |
33 | static struct resource uart0[] = { |
34 | { | |
35 | .start = UART1_BASE_ADDR, | |
36 | .end = UART1_BASE_ADDR + 0x0B5, | |
37 | .flags = IORESOURCE_MEM, | |
38 | }, { | |
39 | .start = MXC_INT_UART1, | |
40 | .end = MXC_INT_UART1, | |
41 | .flags = IORESOURCE_IRQ, | |
42 | }, | |
43 | }; | |
44 | ||
5cf09421 | 45 | struct platform_device mxc_uart_device0 = { |
e3d13ff4 SH |
46 | .name = "imx-uart", |
47 | .id = 0, | |
48 | .resource = uart0, | |
49 | .num_resources = ARRAY_SIZE(uart0), | |
50 | }; | |
51 | ||
52 | static struct resource uart1[] = { | |
53 | { | |
54 | .start = UART2_BASE_ADDR, | |
55 | .end = UART2_BASE_ADDR + 0x0B5, | |
56 | .flags = IORESOURCE_MEM, | |
57 | }, { | |
58 | .start = MXC_INT_UART2, | |
59 | .end = MXC_INT_UART2, | |
60 | .flags = IORESOURCE_IRQ, | |
61 | }, | |
62 | }; | |
63 | ||
5cf09421 | 64 | struct platform_device mxc_uart_device1 = { |
e3d13ff4 SH |
65 | .name = "imx-uart", |
66 | .id = 1, | |
67 | .resource = uart1, | |
68 | .num_resources = ARRAY_SIZE(uart1), | |
69 | }; | |
70 | ||
71 | static struct resource uart2[] = { | |
72 | { | |
73 | .start = UART3_BASE_ADDR, | |
74 | .end = UART3_BASE_ADDR + 0x0B5, | |
75 | .flags = IORESOURCE_MEM, | |
76 | }, { | |
77 | .start = MXC_INT_UART3, | |
78 | .end = MXC_INT_UART3, | |
79 | .flags = IORESOURCE_IRQ, | |
80 | }, | |
81 | }; | |
82 | ||
5cf09421 | 83 | struct platform_device mxc_uart_device2 = { |
e3d13ff4 SH |
84 | .name = "imx-uart", |
85 | .id = 2, | |
86 | .resource = uart2, | |
87 | .num_resources = ARRAY_SIZE(uart2), | |
88 | }; | |
16cf5c41 | 89 | #endif |
e3d13ff4 | 90 | |
07bd1a6c JB |
91 | /* GPIO port description */ |
92 | static struct mxc_gpio_port imx_gpio_ports[] = { | |
3f4f54b4 | 93 | { |
07bd1a6c JB |
94 | .chip.label = "gpio-0", |
95 | .base = IO_ADDRESS(GPIO1_BASE_ADDR), | |
96 | .irq = MXC_INT_GPIO1, | |
9d631b83 | 97 | .virtual_irq_start = MXC_GPIO_IRQ_START, |
3f4f54b4 | 98 | }, { |
07bd1a6c JB |
99 | .chip.label = "gpio-1", |
100 | .base = IO_ADDRESS(GPIO2_BASE_ADDR), | |
101 | .irq = MXC_INT_GPIO2, | |
9d631b83 | 102 | .virtual_irq_start = MXC_GPIO_IRQ_START + 32, |
3f4f54b4 | 103 | }, { |
07bd1a6c JB |
104 | .chip.label = "gpio-2", |
105 | .base = IO_ADDRESS(GPIO3_BASE_ADDR), | |
106 | .irq = MXC_INT_GPIO3, | |
9d631b83 | 107 | .virtual_irq_start = MXC_GPIO_IRQ_START + 64, |
07bd1a6c JB |
108 | } |
109 | }; | |
110 | ||
9a763bfb | 111 | int __init imx3x_register_gpios(void) |
07bd1a6c JB |
112 | { |
113 | return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports)); | |
114 | } | |
a8405929 SH |
115 | |
116 | static struct resource mxc_w1_master_resources[] = { | |
117 | { | |
118 | .start = OWIRE_BASE_ADDR, | |
119 | .end = OWIRE_BASE_ADDR + SZ_4K - 1, | |
120 | .flags = IORESOURCE_MEM, | |
121 | }, | |
122 | }; | |
123 | ||
124 | struct platform_device mxc_w1_master_device = { | |
125 | .name = "mxc_w1", | |
126 | .id = 0, | |
127 | .num_resources = ARRAY_SIZE(mxc_w1_master_resources), | |
128 | .resource = mxc_w1_master_resources, | |
129 | }; | |
cb96cf1a | 130 | |
2adc1d65 SH |
131 | #ifdef CONFIG_ARCH_MX31 |
132 | static struct resource mxcsdhc0_resources[] = { | |
133 | { | |
134 | .start = MMC_SDHC1_BASE_ADDR, | |
135 | .end = MMC_SDHC1_BASE_ADDR + SZ_16K - 1, | |
136 | .flags = IORESOURCE_MEM, | |
137 | }, { | |
138 | .start = MXC_INT_MMC_SDHC1, | |
139 | .end = MXC_INT_MMC_SDHC1, | |
140 | .flags = IORESOURCE_IRQ, | |
141 | }, | |
142 | }; | |
143 | ||
144 | static struct resource mxcsdhc1_resources[] = { | |
145 | { | |
146 | .start = MMC_SDHC2_BASE_ADDR, | |
147 | .end = MMC_SDHC2_BASE_ADDR + SZ_16K - 1, | |
148 | .flags = IORESOURCE_MEM, | |
149 | }, { | |
150 | .start = MXC_INT_MMC_SDHC2, | |
151 | .end = MXC_INT_MMC_SDHC2, | |
152 | .flags = IORESOURCE_IRQ, | |
153 | }, | |
154 | }; | |
155 | ||
156 | struct platform_device mxcsdhc_device0 = { | |
157 | .name = "mxc-mmc", | |
158 | .id = 0, | |
159 | .num_resources = ARRAY_SIZE(mxcsdhc0_resources), | |
160 | .resource = mxcsdhc0_resources, | |
161 | }; | |
162 | ||
163 | struct platform_device mxcsdhc_device1 = { | |
164 | .name = "mxc-mmc", | |
165 | .id = 1, | |
166 | .num_resources = ARRAY_SIZE(mxcsdhc1_resources), | |
167 | .resource = mxcsdhc1_resources, | |
168 | }; | |
45001e92 ACA |
169 | |
170 | static struct resource rnga_resources[] = { | |
171 | { | |
172 | .start = RNGA_BASE_ADDR, | |
173 | .end = RNGA_BASE_ADDR + 0x28, | |
174 | .flags = IORESOURCE_MEM, | |
175 | }, | |
176 | }; | |
177 | ||
178 | struct platform_device mxc_rnga_device = { | |
179 | .name = "mxc_rnga", | |
180 | .id = -1, | |
181 | .num_resources = 1, | |
182 | .resource = rnga_resources, | |
183 | }; | |
2adc1d65 SH |
184 | #endif /* CONFIG_ARCH_MX31 */ |
185 | ||
ca489f8e VL |
186 | /* i.MX31 Image Processing Unit */ |
187 | ||
188 | /* The resource order is important! */ | |
189 | static struct resource mx3_ipu_rsrc[] = { | |
190 | { | |
191 | .start = IPU_CTRL_BASE_ADDR, | |
192 | .end = IPU_CTRL_BASE_ADDR + 0x5F, | |
193 | .flags = IORESOURCE_MEM, | |
194 | }, { | |
195 | .start = IPU_CTRL_BASE_ADDR + 0x88, | |
196 | .end = IPU_CTRL_BASE_ADDR + 0xB3, | |
197 | .flags = IORESOURCE_MEM, | |
198 | }, { | |
199 | .start = MXC_INT_IPU_SYN, | |
200 | .end = MXC_INT_IPU_SYN, | |
201 | .flags = IORESOURCE_IRQ, | |
202 | }, { | |
203 | .start = MXC_INT_IPU_ERR, | |
204 | .end = MXC_INT_IPU_ERR, | |
205 | .flags = IORESOURCE_IRQ, | |
206 | }, | |
207 | }; | |
208 | ||
209 | struct platform_device mx3_ipu = { | |
210 | .name = "ipu-core", | |
211 | .id = -1, | |
212 | .num_resources = ARRAY_SIZE(mx3_ipu_rsrc), | |
213 | .resource = mx3_ipu_rsrc, | |
214 | }; | |
215 | ||
216 | static struct resource fb_resources[] = { | |
217 | { | |
218 | .start = IPU_CTRL_BASE_ADDR + 0xB4, | |
219 | .end = IPU_CTRL_BASE_ADDR + 0x1BF, | |
220 | .flags = IORESOURCE_MEM, | |
221 | }, | |
222 | }; | |
223 | ||
224 | struct platform_device mx3_fb = { | |
225 | .name = "mx3_sdc_fb", | |
226 | .id = -1, | |
227 | .num_resources = ARRAY_SIZE(fb_resources), | |
228 | .resource = fb_resources, | |
229 | .dev = { | |
9c70e227 | 230 | .coherent_dma_mask = DMA_BIT_MASK(32), |
ca489f8e VL |
231 | }, |
232 | }; | |
9536ff33 | 233 | |
9c70e227 VL |
234 | static struct resource camera_resources[] = { |
235 | { | |
236 | .start = IPU_CTRL_BASE_ADDR + 0x60, | |
237 | .end = IPU_CTRL_BASE_ADDR + 0x87, | |
238 | .flags = IORESOURCE_MEM, | |
239 | }, | |
240 | }; | |
241 | ||
242 | struct platform_device mx3_camera = { | |
243 | .name = "mx3-camera", | |
244 | .id = 0, | |
245 | .num_resources = ARRAY_SIZE(camera_resources), | |
246 | .resource = camera_resources, | |
247 | .dev = { | |
248 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
249 | }, | |
250 | }; | |
251 | ||
eb05bbeb GL |
252 | static struct resource otg_resources[] = { |
253 | { | |
7bc07ebc SH |
254 | .start = MX31_OTG_BASE_ADDR, |
255 | .end = MX31_OTG_BASE_ADDR + 0x1ff, | |
eb05bbeb GL |
256 | .flags = IORESOURCE_MEM, |
257 | }, { | |
258 | .start = MXC_INT_USB3, | |
259 | .end = MXC_INT_USB3, | |
260 | .flags = IORESOURCE_IRQ, | |
261 | }, | |
262 | }; | |
263 | ||
264 | static u64 otg_dmamask = DMA_BIT_MASK(32); | |
265 | ||
266 | /* OTG gadget device */ | |
267 | struct platform_device mxc_otg_udc_device = { | |
268 | .name = "fsl-usb2-udc", | |
269 | .id = -1, | |
270 | .dev = { | |
271 | .dma_mask = &otg_dmamask, | |
272 | .coherent_dma_mask = DMA_BIT_MASK(32), | |
273 | }, | |
274 | .resource = otg_resources, | |
275 | .num_resources = ARRAY_SIZE(otg_resources), | |
276 | }; | |
277 | ||
c13a482c DM |
278 | /* OTG host */ |
279 | struct platform_device mxc_otg_host = { | |
280 | .name = "mxc-ehci", | |
281 | .id = 0, | |
282 | .dev = { | |
283 | .coherent_dma_mask = 0xffffffff, | |
284 | .dma_mask = &otg_dmamask, | |
285 | }, | |
286 | .resource = otg_resources, | |
287 | .num_resources = ARRAY_SIZE(otg_resources), | |
288 | }; | |
289 | ||
290 | /* USB host 1 */ | |
291 | ||
292 | static u64 usbh1_dmamask = ~(u32)0; | |
293 | ||
294 | static struct resource mxc_usbh1_resources[] = { | |
295 | { | |
7bc07ebc SH |
296 | .start = MX31_OTG_BASE_ADDR + 0x200, |
297 | .end = MX31_OTG_BASE_ADDR + 0x3ff, | |
c13a482c DM |
298 | .flags = IORESOURCE_MEM, |
299 | }, { | |
300 | .start = MXC_INT_USB1, | |
301 | .end = MXC_INT_USB1, | |
302 | .flags = IORESOURCE_IRQ, | |
303 | }, | |
304 | }; | |
305 | ||
306 | struct platform_device mxc_usbh1 = { | |
307 | .name = "mxc-ehci", | |
308 | .id = 1, | |
309 | .dev = { | |
310 | .coherent_dma_mask = 0xffffffff, | |
311 | .dma_mask = &usbh1_dmamask, | |
312 | }, | |
313 | .resource = mxc_usbh1_resources, | |
314 | .num_resources = ARRAY_SIZE(mxc_usbh1_resources), | |
315 | }; | |
316 | ||
317 | /* USB host 2 */ | |
318 | static u64 usbh2_dmamask = ~(u32)0; | |
319 | ||
320 | static struct resource mxc_usbh2_resources[] = { | |
321 | { | |
7bc07ebc SH |
322 | .start = MX31_OTG_BASE_ADDR + 0x400, |
323 | .end = MX31_OTG_BASE_ADDR + 0x5ff, | |
c13a482c DM |
324 | .flags = IORESOURCE_MEM, |
325 | }, { | |
326 | .start = MXC_INT_USB2, | |
327 | .end = MXC_INT_USB2, | |
328 | .flags = IORESOURCE_IRQ, | |
329 | }, | |
330 | }; | |
331 | ||
332 | struct platform_device mxc_usbh2 = { | |
333 | .name = "mxc-ehci", | |
334 | .id = 2, | |
335 | .dev = { | |
336 | .coherent_dma_mask = 0xffffffff, | |
337 | .dma_mask = &usbh2_dmamask, | |
338 | }, | |
339 | .resource = mxc_usbh2_resources, | |
340 | .num_resources = ARRAY_SIZE(mxc_usbh2_resources), | |
341 | }; | |
342 | ||
06606ff1 | 343 | #if defined(CONFIG_ARCH_MX35) |
9536ff33 SH |
344 | static struct resource mxc_fec_resources[] = { |
345 | { | |
346 | .start = MXC_FEC_BASE_ADDR, | |
347 | .end = MXC_FEC_BASE_ADDR + 0xfff, | |
3f4f54b4 | 348 | .flags = IORESOURCE_MEM, |
9536ff33 SH |
349 | }, { |
350 | .start = MXC_INT_FEC, | |
351 | .end = MXC_INT_FEC, | |
3f4f54b4 | 352 | .flags = IORESOURCE_IRQ, |
9536ff33 SH |
353 | }, |
354 | }; | |
355 | ||
356 | struct platform_device mxc_fec_device = { | |
357 | .name = "fec", | |
358 | .id = 0, | |
359 | .num_resources = ARRAY_SIZE(mxc_fec_resources), | |
360 | .resource = mxc_fec_resources, | |
361 | }; | |
362 | #endif | |
363 | ||
d8d982b1 SH |
364 | static struct resource imx_ssi_resources0[] = { |
365 | { | |
366 | .start = SSI1_BASE_ADDR, | |
367 | .end = SSI1_BASE_ADDR + 0xfff, | |
368 | .flags = IORESOURCE_MEM, | |
369 | }, { | |
370 | .start = MX31_INT_SSI1, | |
371 | .end = MX31_INT_SSI1, | |
372 | .flags = IORESOURCE_IRQ, | |
373 | }, | |
374 | }; | |
375 | ||
376 | static struct resource imx_ssi_resources1[] = { | |
377 | { | |
378 | .start = SSI2_BASE_ADDR, | |
379 | .end = SSI2_BASE_ADDR + 0xfff, | |
380 | .flags = IORESOURCE_MEM | |
381 | }, { | |
382 | .start = MX31_INT_SSI2, | |
383 | .end = MX31_INT_SSI2, | |
384 | .flags = IORESOURCE_IRQ, | |
385 | }, | |
386 | }; | |
387 | ||
388 | struct platform_device imx_ssi_device0 = { | |
389 | .name = "imx-ssi", | |
390 | .id = 0, | |
391 | .num_resources = ARRAY_SIZE(imx_ssi_resources0), | |
392 | .resource = imx_ssi_resources0, | |
393 | }; | |
394 | ||
395 | struct platform_device imx_ssi_device1 = { | |
396 | .name = "imx-ssi", | |
397 | .id = 1, | |
398 | .num_resources = ARRAY_SIZE(imx_ssi_resources1), | |
399 | .resource = imx_ssi_resources1, | |
400 | }; | |
401 | ||
a7dc12ba VZ |
402 | static struct resource imx_wdt_resources[] = { |
403 | { | |
404 | .flags = IORESOURCE_MEM, | |
405 | }, | |
406 | }; | |
407 | ||
408 | struct platform_device imx_wdt_device0 = { | |
6d38c1cf | 409 | .name = "imx2-wdt", |
a7dc12ba VZ |
410 | .id = 0, |
411 | .num_resources = ARRAY_SIZE(imx_wdt_resources), | |
412 | .resource = imx_wdt_resources, | |
413 | }; | |
414 | ||
ded518c6 VZ |
415 | static struct resource imx_rtc_resources[] = { |
416 | { | |
417 | .start = MX31_RTC_BASE_ADDR, | |
418 | .end = MX31_RTC_BASE_ADDR + 0x3fff, | |
419 | .flags = IORESOURCE_MEM, | |
420 | }, | |
421 | { | |
422 | .start = MX31_INT_RTC, | |
423 | .flags = IORESOURCE_IRQ, | |
424 | }, | |
425 | }; | |
426 | ||
427 | struct platform_device imx_rtc_device0 = { | |
428 | .name = "mxc_rtc", | |
429 | .id = -1, | |
430 | .num_resources = ARRAY_SIZE(imx_rtc_resources), | |
431 | .resource = imx_rtc_resources, | |
432 | }; | |
433 | ||
b1e89955 AP |
434 | static struct resource imx_kpp_resources[] = { |
435 | { | |
436 | .start = MX3x_KPP_BASE_ADDR, | |
437 | .end = MX3x_KPP_BASE_ADDR + 0xf, | |
438 | .flags = IORESOURCE_MEM | |
439 | }, { | |
440 | .start = MX3x_INT_KPP, | |
441 | .end = MX3x_INT_KPP, | |
442 | .flags = IORESOURCE_IRQ, | |
443 | }, | |
444 | }; | |
445 | ||
446 | struct platform_device imx_kpp_device = { | |
447 | .name = "imx-keypad", | |
448 | .id = -1, | |
449 | .num_resources = ARRAY_SIZE(imx_kpp_resources), | |
450 | .resource = imx_kpp_resources, | |
451 | }; | |
452 | ||
a7dc12ba | 453 | static int __init mx3_devices_init(void) |
9536ff33 | 454 | { |
a2ceeef5 | 455 | #if defined(CONFIG_ARCH_MX31) |
9536ff33 | 456 | if (cpu_is_mx31()) { |
a7dc12ba VZ |
457 | imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR; |
458 | imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff; | |
45001e92 | 459 | mxc_register_device(&mxc_rnga_device, NULL); |
9536ff33 | 460 | } |
a2ceeef5 UKK |
461 | #endif |
462 | #if defined(CONFIG_ARCH_MX35) | |
9536ff33 | 463 | if (cpu_is_mx35()) { |
7bc07ebc SH |
464 | otg_resources[0].start = MX35_OTG_BASE_ADDR; |
465 | otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff; | |
466 | otg_resources[1].start = MXC_INT_USBOTG; | |
467 | otg_resources[1].end = MXC_INT_USBOTG; | |
468 | mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400; | |
469 | mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff; | |
470 | mxc_usbh1_resources[1].start = MXC_INT_USBHS; | |
471 | mxc_usbh1_resources[1].end = MXC_INT_USBHS; | |
d8d982b1 SH |
472 | imx_ssi_resources0[1].start = MX35_INT_SSI1; |
473 | imx_ssi_resources0[1].end = MX35_INT_SSI1; | |
474 | imx_ssi_resources1[1].start = MX35_INT_SSI2; | |
475 | imx_ssi_resources1[1].end = MX35_INT_SSI2; | |
a7dc12ba VZ |
476 | imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR; |
477 | imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff; | |
9536ff33 | 478 | } |
a2ceeef5 | 479 | #endif |
9536ff33 SH |
480 | |
481 | return 0; | |
482 | } | |
483 | ||
484 | subsys_initcall(mx3_devices_init); |