projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input
[linux-2.6-block.git] / arch / arm / mach-mx25 / clock.c
CommitLineData
8c25c36f
SH		 1/*
2 * Copyright (C) 2009 by Sascha Hauer, Pengutronix
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/list.h>
22#include <linux/clk.h>
23#include <linux/io.h>
24
25#include <asm/clkdev.h>
26
27#include <mach/clock.h>
28#include <mach/hardware.h>
29#include <mach/common.h>
30#include <mach/mx25.h>
31
32#define CRM_BASE MX25_IO_ADDRESS(MX25_CRM_BASE_ADDR)
33
34#define CCM_MPCTL 0x00
35#define CCM_UPCTL 0x04
36#define CCM_CCTL 0x08
37#define CCM_CGCR0 0x0C
38#define CCM_CGCR1 0x10
39#define CCM_CGCR2 0x14
40#define CCM_PCDR0 0x18
41#define CCM_PCDR1 0x1C
42#define CCM_PCDR2 0x20
43#define CCM_PCDR3 0x24
44#define CCM_RCSR 0x28
45#define CCM_CRDR 0x2C
46#define CCM_DCVR0 0x30
47#define CCM_DCVR1 0x34
48#define CCM_DCVR2 0x38
49#define CCM_DCVR3 0x3c
50#define CCM_LTR0 0x40
51#define CCM_LTR1 0x44
52#define CCM_LTR2 0x48
53#define CCM_LTR3 0x4c
54
55static unsigned long get_rate_mpll(void)
56{
57 ulong mpctl = __raw_readl(CRM_BASE + CCM_MPCTL);
58
59 return mxc_decode_pll(mpctl, 24000000);
60}
61
62static unsigned long get_rate_upll(void)
63{
64 ulong mpctl = __raw_readl(CRM_BASE + CCM_UPCTL);
65
66 return mxc_decode_pll(mpctl, 24000000);
67}
68
69unsigned long get_rate_arm(struct clk *clk)
70{
71 unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
72 unsigned long rate = get_rate_mpll();
73
74 if (cctl & (1 << 14))
75 rate = (rate * 3) >> 1;
76
77 return rate / ((cctl >> 30) + 1);
78}
79
80static unsigned long get_rate_ahb(struct clk *clk)
81{
82 unsigned long cctl = readl(CRM_BASE + CCM_CCTL);
83
84 return get_rate_arm(NULL) / (((cctl >> 28) & 0x3) + 1);
85}
86
87static unsigned long get_rate_ipg(struct clk *clk)
88{
89 return get_rate_ahb(NULL) >> 1;
90}
91
92static unsigned long get_rate_per(int per)
93{
94 unsigned long ofs = (per & 0x3) * 8;
95 unsigned long reg = per & ~0x3;
96 unsigned long val = (readl(CRM_BASE + CCM_PCDR0 + reg) >> ofs) & 0x3f;
97 unsigned long fref;
98
99 if (readl(CRM_BASE + 0x64) & (1 << per))
100 fref = get_rate_upll();
101 else
102 fref = get_rate_ipg(NULL);
103
104 return fref / (val + 1);
105}
106
107static unsigned long get_rate_uart(struct clk *clk)
108{
109 return get_rate_per(15);
110}
111
112static unsigned long get_rate_i2c(struct clk *clk)
113{
114 return get_rate_per(6);
115}
116
117static unsigned long get_rate_nfc(struct clk *clk)
118{
119 return get_rate_per(8);
120}
121
faed4066
BS		 122static unsigned long get_rate_gpt(struct clk *clk)
123{
124 return get_rate_per(5);
125}
126
8c25c36f
SH		 127static unsigned long get_rate_otg(struct clk *clk)
128{
129 return 48000000; /* FIXME */
130}
131
132static int clk_cgcr_enable(struct clk *clk)
133{
134 u32 reg;
135
136 reg = __raw_readl(clk->enable_reg);
137 reg |= 1 << clk->enable_shift;
138 __raw_writel(reg, clk->enable_reg);
139
140 return 0;
141}
142
143static void clk_cgcr_disable(struct clk *clk)
144{
145 u32 reg;
146
147 reg = __raw_readl(clk->enable_reg);
148 reg &= ~(1 << clk->enable_shift);
149 __raw_writel(reg, clk->enable_reg);
150}
151
9611a9b6 152#define DEFINE_CLOCK(name, i, er, es, gr, sr, s) \
8c25c36f
SH		 153 static struct clk name = { \
154 .id = i, \
155 .enable_reg = CRM_BASE + er, \
156 .enable_shift = es, \
157 .get_rate = gr, \
158 .set_rate = sr, \
159 .enable = clk_cgcr_enable, \
160 .disable = clk_cgcr_disable, \
9611a9b6 161 .secondary = s, \
8c25c36f
SH		 162 }
163
faed4066 164DEFINE_CLOCK(gpt_clk, 0, CCM_CGCR0, 5, get_rate_gpt, NULL, NULL);
4cd3f96c 165DEFINE_CLOCK(uart_per_clk, 0, CCM_CGCR0, 15, get_rate_uart, NULL, NULL);
9611a9b6
SH		 166DEFINE_CLOCK(cspi1_clk, 0, CCM_CGCR1, 5, get_rate_ipg, NULL, NULL);
167DEFINE_CLOCK(cspi2_clk, 0, CCM_CGCR1, 6, get_rate_ipg, NULL, NULL);
168DEFINE_CLOCK(cspi3_clk, 0, CCM_CGCR1, 7, get_rate_ipg, NULL, NULL);
1c574023 169DEFINE_CLOCK(fec_ahb_clk, 0, CCM_CGCR0, 23, NULL, NULL, NULL);
4cd3f96c
SH		 170DEFINE_CLOCK(uart1_clk, 0, CCM_CGCR2, 14, get_rate_uart, NULL, &uart_per_clk);
171DEFINE_CLOCK(uart2_clk, 0, CCM_CGCR2, 15, get_rate_uart, NULL, &uart_per_clk);
172DEFINE_CLOCK(uart3_clk, 0, CCM_CGCR2, 16, get_rate_uart, NULL, &uart_per_clk);
173DEFINE_CLOCK(uart4_clk, 0, CCM_CGCR2, 17, get_rate_uart, NULL, &uart_per_clk);
174DEFINE_CLOCK(uart5_clk, 0, CCM_CGCR2, 18, get_rate_uart, NULL, &uart_per_clk);
9611a9b6
SH		 175DEFINE_CLOCK(nfc_clk, 0, CCM_CGCR0, 8, get_rate_nfc, NULL, NULL);
176DEFINE_CLOCK(usbotg_clk, 0, CCM_CGCR0, 28, get_rate_otg, NULL, NULL);
177DEFINE_CLOCK(pwm1_clk, 0, CCM_CGCR1, 31, get_rate_ipg, NULL, NULL);
178DEFINE_CLOCK(pwm2_clk, 0, CCM_CGCR2, 0, get_rate_ipg, NULL, NULL);
179DEFINE_CLOCK(pwm3_clk, 0, CCM_CGCR2, 1, get_rate_ipg, NULL, NULL);
180DEFINE_CLOCK(pwm4_clk, 0, CCM_CGCR2, 2, get_rate_ipg, NULL, NULL);
181DEFINE_CLOCK(kpp_clk, 0, CCM_CGCR1, 28, get_rate_ipg, NULL, NULL);
182DEFINE_CLOCK(tsc_clk, 0, CCM_CGCR2, 13, get_rate_ipg, NULL, NULL);
183DEFINE_CLOCK(i2c_clk, 0, CCM_CGCR0, 6, get_rate_i2c, NULL, NULL);
1c574023 184DEFINE_CLOCK(fec_clk, 0, CCM_CGCR1, 15, get_rate_ipg, NULL, &fec_ahb_clk);
8c25c36f
SH		 185
186#define _REGISTER_CLOCK(d, n, c) \
187 { \
188 .dev_id = d, \
189 .con_id = n, \
190 .clk = &c, \
191 },
192
193static struct clk_lookup lookups[] = {
194 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
195 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
196 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
197 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
198 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
199 _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
200 _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
201 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
202 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
203 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
204 _REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
205 _REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
206 _REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
207 _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
208 _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
209 _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
210 _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm4_clk)
211 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
212 _REGISTER_CLOCK("mx25-adc", NULL, tsc_clk)
213 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
214 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
215 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
a759544f 216 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
8c25c36f
SH		 217};
218
fadc0956 219int __init mx25_clocks_init(void)
8c25c36f
SH		 220{
221 int i;
222
223 for (i = 0; i < ARRAY_SIZE(lookups); i++)
224 clkdev_add(&lookups[i]);
225
828df43f
BS		 226 /* Turn off all clocks except the ones we need to survive, namely:
227 * EMI, GPIO1-3 (CCM_CGCR1[18:16]), GPT1, IOMUXC (CCM_CGCR1[27]), IIM,
228 * SCC
229 */
230 __raw_writel((1 << 19), CRM_BASE + CCM_CGCR0);
231 __raw_writel((0xf << 16) | (3 << 26), CRM_BASE + CCM_CGCR1);
232 __raw_writel((1 << 5), CRM_BASE + CCM_CGCR2);
233
8c25c36f
SH		 234 mxc_timer_init(&gpt_clk, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
235
236 return 0;
237}
Linux 6.x block layer and io_uring tree(s)