[linux-2.6-block.git] / arch / arm / mach-mvebu / pmsu.c

/*
 * Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
 *
 * Copyright (C) 2012 Marvell
 *
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory Clement <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada 370 and Armada XP SOCs have a power management service
 * unit which is responsible for powering down and waking up CPUs and
 * other SOC units
 */

#define pr_fmt(fmt) "mvebu-pmsu: " fmt

#include <linux/clk.h>
#include <linux/cpu_pm.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/mbus.h>
#include <linux/of_address.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/resource.h>
#include <linux/slab.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/tlbflush.h>
#include "common.h"


#define PMSU_BASE_OFFSET    0x100
#define PMSU_REG_SIZE	    0x1000

/* PMSU MP registers */
#define PMSU_CONTROL_AND_CONFIG(cpu)	    ((cpu * 0x100) + 0x104)
#define PMSU_CONTROL_AND_CONFIG_DFS_REQ		BIT(18)
#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ	BIT(16)
#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN	BIT(20)

#define PMSU_CPU_POWER_DOWN_CONTROL(cpu)    ((cpu * 0x100) + 0x108)

#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP	BIT(0)

#define PMSU_STATUS_AND_MASK(cpu)	    ((cpu * 0x100) + 0x10c)
#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT	BIT(16)
#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT	BIT(17)
#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP		BIT(20)
#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP		BIT(21)
#define PMSU_STATUS_AND_MASK_DBG_WAKEUP		BIT(22)
#define PMSU_STATUS_AND_MASK_IRQ_MASK		BIT(24)
#define PMSU_STATUS_AND_MASK_FIQ_MASK		BIT(25)

#define PMSU_EVENT_STATUS_AND_MASK(cpu)     ((cpu * 0x100) + 0x120)
#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE        BIT(1)
#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK   BIT(17)

#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)

/* PMSU fabric registers */
#define L2C_NFABRIC_PM_CTL		    0x4
#define L2C_NFABRIC_PM_CTL_PWR_DOWN		BIT(20)

/* PMSU delay registers */
#define PMSU_POWERDOWN_DELAY		    0xF04
#define PMSU_POWERDOWN_DELAY_PMU		BIT(1)
#define PMSU_POWERDOWN_DELAY_MASK		0xFFFE
#define PMSU_DFLT_ARMADA38X_DELAY	        0x64

/* CA9 MPcore SoC Control registers */

#define MPCORE_RESET_CTL		    0x64
#define MPCORE_RESET_CTL_L2			BIT(0)
#define MPCORE_RESET_CTL_DEBUG			BIT(16)

#define SRAM_PHYS_BASE  0xFFFF0000
#define BOOTROM_BASE    0xFFF00000
#define BOOTROM_SIZE    0x100000

#define ARMADA_370_CRYPT0_ENG_TARGET   0x9
#define ARMADA_370_CRYPT0_ENG_ATTR     0x1

extern void ll_disable_coherency(void);
extern void ll_enable_coherency(void);

extern void armada_370_xp_cpu_resume(void);
extern void armada_38x_cpu_resume(void);

static phys_addr_t pmsu_mp_phys_base;
static void __iomem *pmsu_mp_base;

static void *mvebu_cpu_resume;

static const struct of_device_id of_pmsu_table[] = {
	{ .compatible = "marvell,armada-370-pmsu", },
	{ .compatible = "marvell,armada-370-xp-pmsu", },
	{ .compatible = "marvell,armada-380-pmsu", },
	{ /* end of list */ },
};

void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
{
	writel(virt_to_phys(boot_addr), pmsu_mp_base +
		PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
}

extern unsigned char mvebu_boot_wa_start;
extern unsigned char mvebu_boot_wa_end;

/*
 * This function sets up the boot address workaround needed for SMP
 * boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
 * BootROM Mbus window, and instead remaps a crypto SRAM into which a
 * custom piece of code is copied to replace the problematic BootROM.
 */
int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
			     unsigned int crypto_eng_attribute,
			     phys_addr_t resume_addr_reg)
{
	void __iomem *sram_virt_base;
	u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;

	mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
	mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
				    SRAM_PHYS_BASE, SZ_64K);

	sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
	if (!sram_virt_base) {
		pr_err("Unable to map SRAM to setup the boot address WA\n");
		return -ENOMEM;
	}

	memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);

	/*
	 * The last word of the code copied in SRAM must contain the
	 * physical base address of the PMSU register. We
	 * intentionally store this address in the native endianness
	 * of the system.
	 */
	__raw_writel((unsigned long)resume_addr_reg,
		     sram_virt_base + code_len - 4);

	iounmap(sram_virt_base);

	return 0;
}

static int __init mvebu_v7_pmsu_init(void)
{
	struct device_node *np;
	struct resource res;
	int ret = 0;

	np = of_find_matching_node(NULL, of_pmsu_table);
	if (!np)
		return 0;

	pr_info("Initializing Power Management Service Unit\n");

	if (of_address_to_resource(np, 0, &res)) {
		pr_err("unable to get resource\n");
		ret = -ENOENT;
		goto out;
	}

	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
		pr_warn(FW_WARN "deprecated pmsu binding\n");
		res.start = res.start - PMSU_BASE_OFFSET;
		res.end = res.start + PMSU_REG_SIZE - 1;
	}

	if (!request_mem_region(res.start, resource_size(&res),
				np->full_name)) {
		pr_err("unable to request region\n");
		ret = -EBUSY;
		goto out;
	}

	pmsu_mp_phys_base = res.start;

	pmsu_mp_base = ioremap(res.start, resource_size(&res));
	if (!pmsu_mp_base) {
		pr_err("unable to map registers\n");
		release_mem_region(res.start, resource_size(&res));
		ret = -ENOMEM;
		goto out;
	}

 out:
	of_node_put(np);
	return ret;
}

static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
{
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;

	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN;
	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
}

enum pmsu_idle_prepare_flags {
	PMSU_PREPARE_NORMAL = 0,
	PMSU_PREPARE_DEEP_IDLE = BIT(0),
	PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
};

/* No locking is needed because we only access per-CPU registers */
static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
{
	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	u32 reg;

	if (pmsu_mp_base == NULL)
		return -EINVAL;

	/*
	 * Adjust the PMSU configuration to wait for WFI signal, enable
	 * IRQ and FIQ as wakeup events, set wait for snoop queue empty
	 * indication and mask IRQ and FIQ from CPU
	 */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT    |
	       PMSU_STATUS_AND_MASK_IRQ_WAKEUP       |
	       PMSU_STATUS_AND_MASK_FIQ_WAKEUP       |
	       PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT |
	       PMSU_STATUS_AND_MASK_IRQ_MASK         |
	       PMSU_STATUS_AND_MASK_FIQ_MASK;
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));

	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	/* ask HW to power down the L2 Cache if needed */
	if (flags & PMSU_PREPARE_DEEP_IDLE)
		reg |= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;

	/* request power down */
	reg |= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));

	if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
		/* Disable snoop disable by HW - SW is taking care of it */
		reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
		reg |= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
		writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	}

	return 0;
}

int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
{
	unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
	int ret;

	if (deepidle)
		flags |= PMSU_PREPARE_DEEP_IDLE;

	ret = mvebu_v7_pmsu_idle_prepare(flags);
	if (ret)
		return ret;

	v7_exit_coherency_flush(all);

	ll_disable_coherency();

	dsb();

	wfi();

	/* If we are here, wfi failed. As processors run out of
	 * coherency for some time, tlbs might be stale, so flush them
	 */
	local_flush_tlb_all();

	ll_enable_coherency();

	/* Test the CR_C bit and set it if it was cleared */
	asm volatile(
	"mrc	p15, 0, r0, c1, c0, 0 \n\t"
	"tst	r0, %0 \n\t"
	"orreq	r0, r0, #(1 << 2) \n\t"
	"mcreq	p15, 0, r0, c1, c0, 0 \n\t"
	"isb	"
	: : "Ir" (CR_C) : "r0");

	pr_debug("Failed to suspend the system\n");

	return 0;
}

static int armada_370_xp_cpu_suspend(unsigned long deepidle)
{
	return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
}

int armada_38x_do_cpu_suspend(unsigned long deepidle)
{
	unsigned long flags = 0;

	if (deepidle)
		flags |= PMSU_PREPARE_DEEP_IDLE;

	mvebu_v7_pmsu_idle_prepare(flags);
	/*
	 * Already flushed cache, but do it again as the outer cache
	 * functions dirty the cache with spinlocks
	 */
	v7_exit_coherency_flush(louis);

	scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);

	cpu_do_idle();

	return 1;
}

static int armada_38x_cpu_suspend(unsigned long deepidle)
{
	return cpu_suspend(false, armada_38x_do_cpu_suspend);
}

/* No locking is needed because we only access per-CPU registers */
void mvebu_v7_pmsu_idle_exit(void)
{
	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	u32 reg;

	if (pmsu_mp_base == NULL)
		return;
	/* cancel ask HW to power down the L2 Cache if possible */
	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));

	/* cancel Enable wakeup events and mask interrupts */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP | PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK | PMSU_STATUS_AND_MASK_FIQ_MASK);
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
}

static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	if (action == CPU_PM_ENTER) {
		unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
		mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
	} else if (action == CPU_PM_EXIT) {
		mvebu_v7_pmsu_idle_exit();
	}

	return NOTIFY_OK;
}

static struct notifier_block mvebu_v7_cpu_pm_notifier = {
	.notifier_call = mvebu_v7_cpu_pm_notify,
};

static struct platform_device mvebu_v7_cpuidle_device;

static int broken_idle(struct device_node *np)
{
	if (of_property_read_bool(np, "broken-idle")) {
		pr_warn("CPU idle is currently broken: disabling\n");
		return 1;
	}

	return 0;
}

static __init int armada_370_cpuidle_init(void)
{
	struct device_node *np;
	phys_addr_t redirect_reg;

	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
	if (!np)
		return -ENODEV;

	if (broken_idle(np))
		goto end;

	/*
	 * On Armada 370, there is "a slow exit process from the deep
	 * idle state due to heavy L1/L2 cache cleanup operations
	 * performed by the BootROM software". To avoid this, we
	 * replace the restart code of the bootrom by a a simple jump
	 * to the boot address. Then the code located at this boot
	 * address will take care of the initialization.
	 */
	redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
	mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
				 ARMADA_370_CRYPT0_ENG_ATTR,
				 redirect_reg);

	mvebu_cpu_resume = armada_370_xp_cpu_resume;
	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";

end:
	of_node_put(np);
	return 0;
}

static __init int armada_38x_cpuidle_init(void)
{
	struct device_node *np;
	void __iomem *mpsoc_base;
	u32 reg;

	pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
	return 0;

	np = of_find_compatible_node(NULL, NULL,
				     "marvell,armada-380-coherency-fabric");
	if (!np)
		return -ENODEV;

	if (broken_idle(np))
		goto end;

	of_node_put(np);

	np = of_find_compatible_node(NULL, NULL,
				     "marvell,armada-380-mpcore-soc-ctrl");
	if (!np)
		return -ENODEV;
	mpsoc_base = of_iomap(np, 0);
	BUG_ON(!mpsoc_base);

	/* Set up reset mask when powering down the cpus */
	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
	reg |= MPCORE_RESET_CTL_L2;
	reg |= MPCORE_RESET_CTL_DEBUG;
	writel(reg, mpsoc_base + MPCORE_RESET_CTL);
	iounmap(mpsoc_base);

	/* Set up delay */
	reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
	reg &= ~PMSU_POWERDOWN_DELAY_MASK;
	reg |= PMSU_DFLT_ARMADA38X_DELAY;
	reg |= PMSU_POWERDOWN_DELAY_PMU;
	writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);

	mvebu_cpu_resume = armada_38x_cpu_resume;
	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";

end:
	of_node_put(np);
	return 0;
}

static __init int armada_xp_cpuidle_init(void)
{
	struct device_node *np;

	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
	if (!np)
		return -ENODEV;

	if (broken_idle(np))
		goto end;

	mvebu_cpu_resume = armada_370_xp_cpu_resume;
	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";

end:
	of_node_put(np);
	return 0;
}

static int __init mvebu_v7_cpu_pm_init(void)
{
	struct device_node *np;
	int ret;

	np = of_find_matching_node(NULL, of_pmsu_table);
	if (!np)
		return 0;
	of_node_put(np);

	/*
	 * Currently the CPU idle support for Armada 38x is broken, as
	 * the CPU hotplug uses some of the CPU idle functions it is
	 * broken too, so let's disable it
	 */
	if (of_machine_is_compatible("marvell,armada380")) {
		cpu_hotplug_disable();
		pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
	}

	if (of_machine_is_compatible("marvell,armadaxp"))
		ret = armada_xp_cpuidle_init();
	else if (of_machine_is_compatible("marvell,armada370"))
		ret = armada_370_cpuidle_init();
	else if (of_machine_is_compatible("marvell,armada380"))
		ret = armada_38x_cpuidle_init();
	else
		return 0;

	if (ret)
		return ret;

	mvebu_v7_pmsu_enable_l2_powerdown_onidle();
	if (mvebu_v7_cpuidle_device.name)
		platform_device_register(&mvebu_v7_cpuidle_device);
	cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);

	return 0;
}

arch_initcall(mvebu_v7_cpu_pm_init);
early_initcall(mvebu_v7_pmsu_init);

static void mvebu_pmsu_dfs_request_local(void *data)
{
	u32 reg;
	u32 cpu = smp_processor_id();
	unsigned long flags;

	local_irq_save(flags);

	/* Prepare to enter idle */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
	reg |= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT |
	       PMSU_STATUS_AND_MASK_IRQ_MASK     |
	       PMSU_STATUS_AND_MASK_FIQ_MASK;
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));

	/* Request the DFS transition */
	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
	reg |= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));

	/* The fact of entering idle will trigger the DFS transition */
	wfi();

	/*
	 * We're back from idle, the DFS transition has completed,
	 * clear the idle wait indication.
	 */
	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));

	local_irq_restore(flags);
}

int mvebu_pmsu_dfs_request(int cpu)
{
	unsigned long timeout;
	int hwcpu = cpu_logical_map(cpu);
	u32 reg;

	/* Clear any previous DFS DONE event */
	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));

	/* Mask the DFS done interrupt, since we are going to poll */
	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	reg |= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));

	/* Trigger the DFS on the appropriate CPU */
	smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
				 NULL, false);

	/* Poll until the DFS done event is generated */
	timeout = jiffies + HZ;
	while (time_before(jiffies, timeout)) {
		reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
		if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
			break;
		udelay(10);
	}

	if (time_after(jiffies, timeout))
		return -ETIME;

	/* Restore the DFS mask to its original state */
	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));

	return 0;
}
Commit	Line	Data
7444dad2 GC	1	/*
	2	* Power Management Service Unit(PMSU) support for Armada 370/XP platforms.
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Yehuda Yitschak <yehuday@marvell.com>
	7	* Gregory Clement <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
	10	* This file is licensed under the terms of the GNU General Public
	11	* License version 2. This program is licensed "as is" without any
	12	* warranty of any kind, whether express or implied.
	13	*
	14	* The Armada 370 and Armada XP SOCs have a power management service
	15	* unit which is responsible for powering down and waking up CPUs and
	16	* other SOC units
	17	*/
	18
bd045a1e TP	19	#define pr_fmt(fmt) "mvebu-pmsu: " fmt
bd045a1e TP	20
a509ea84	21	#include <linux/clk.h>
d163ee16	22	#include <linux/cpu_pm.h>
a509ea84	23	#include <linux/delay.h>
7444dad2	24	#include <linux/init.h>
7444dad2	25	#include <linux/io.h>
3e328428	26	#include <linux/kernel.h>
3076cc58	27	#include <linux/mbus.h>
7444dad2	28	#include <linux/of_address.h>
a509ea84	29	#include <linux/of_device.h>
8c16babc	30	#include <linux/platform_device.h>
49754ffe	31	#include <linux/resource.h>
a509ea84	32	#include <linux/slab.h>
3e328428	33	#include <linux/smp.h>
c3e04cab GC	34	#include <asm/cacheflush.h>
c3e04cab GC	35	#include <asm/cp15.h>
e53b1fd4	36	#include <asm/smp_scu.h>
7444dad2	37	#include <asm/smp_plat.h>
c3e04cab GC	38	#include <asm/suspend.h>
c3e04cab GC	39	#include <asm/tlbflush.h>
49754ffe	40	#include "common.h"
7444dad2	41
7444dad2	42
0c3acc74 GC	43	#define PMSU_BASE_OFFSET 0x100
	44	#define PMSU_REG_SIZE 0x1000
	45
f713c7e7	46	/* PMSU MP registers */
c3e04cab GC	47	#define PMSU_CONTROL_AND_CONFIG(cpu) ((cpu * 0x100) + 0x104)
	48	#define PMSU_CONTROL_AND_CONFIG_DFS_REQ BIT(18)
	49	#define PMSU_CONTROL_AND_CONFIG_PWDDN_REQ BIT(16)
	50	#define PMSU_CONTROL_AND_CONFIG_L2_PWDDN BIT(20)
	51
	52	#define PMSU_CPU_POWER_DOWN_CONTROL(cpu) ((cpu * 0x100) + 0x108)
	53
	54	#define PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP BIT(0)
	55
	56	#define PMSU_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x10c)
	57	#define PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT BIT(16)
	58	#define PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT BIT(17)
	59	#define PMSU_STATUS_AND_MASK_IRQ_WAKEUP BIT(20)
	60	#define PMSU_STATUS_AND_MASK_FIQ_WAKEUP BIT(21)
	61	#define PMSU_STATUS_AND_MASK_DBG_WAKEUP BIT(22)
	62	#define PMSU_STATUS_AND_MASK_IRQ_MASK BIT(24)
	63	#define PMSU_STATUS_AND_MASK_FIQ_MASK BIT(25)
	64
a509ea84 TP	65	#define PMSU_EVENT_STATUS_AND_MASK(cpu) ((cpu * 0x100) + 0x120)
	66	#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE BIT(1)
	67	#define PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK BIT(17)
	68
f713c7e7 GC	69	#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124)
	70
	71	/* PMSU fabric registers */
	72	#define L2C_NFABRIC_PM_CTL 0x4
	73	#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20)
7444dad2	74
e53b1fd4 GC	75	/* PMSU delay registers */
	76	#define PMSU_POWERDOWN_DELAY 0xF04
	77	#define PMSU_POWERDOWN_DELAY_PMU BIT(1)
	78	#define PMSU_POWERDOWN_DELAY_MASK 0xFFFE
	79	#define PMSU_DFLT_ARMADA38X_DELAY 0x64
	80
	81	/* CA9 MPcore SoC Control registers */
	82
	83	#define MPCORE_RESET_CTL 0x64
	84	#define MPCORE_RESET_CTL_L2 BIT(0)
	85	#define MPCORE_RESET_CTL_DEBUG BIT(16)
	86
3076cc58 GC	87	#define SRAM_PHYS_BASE 0xFFFF0000
	88	#define BOOTROM_BASE 0xFFF00000
	89	#define BOOTROM_SIZE 0x100000
	90
3b9e4b14 GC	91	#define ARMADA_370_CRYPT0_ENG_TARGET 0x9
	92	#define ARMADA_370_CRYPT0_ENG_ATTR 0x1
	93
c3e04cab GC	94	extern void ll_disable_coherency(void);
	95	extern void ll_enable_coherency(void);
	96
6509dc74	97	extern void armada_370_xp_cpu_resume(void);
e53b1fd4 GC	98	extern void armada_38x_cpu_resume(void);
e53b1fd4 GC	99
3b9e4b14 GC	100	static phys_addr_t pmsu_mp_phys_base;
3b9e4b14 GC	101	static void __iomem *pmsu_mp_base;
6509dc74	102
752a9937	103	static void *mvebu_cpu_resume;
8c16babc	104
444d2d33	105	static const struct of_device_id of_pmsu_table[] = {
0c3acc74 GC	106	{ .compatible = "marvell,armada-370-pmsu", },
0c3acc74 GC	107	{ .compatible = "marvell,armada-370-xp-pmsu", },
b4bca249	108	{ .compatible = "marvell,armada-380-pmsu", },
7444dad2 GC	109	{ /* end of list */ },
	110	};
	111
05ad6906	112	void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
02e7b067 GC	113	{
	114	writel(virt_to_phys(boot_addr), pmsu_mp_base +
	115	PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu));
	116	}
	117
3076cc58 GC	118	extern unsigned char mvebu_boot_wa_start;
	119	extern unsigned char mvebu_boot_wa_end;
	120
	121	/*
	122	* This function sets up the boot address workaround needed for SMP
	123	* boot on Armada 375 Z1 and cpuidle on Armada 370. It unmaps the
	124	* BootROM Mbus window, and instead remaps a crypto SRAM into which a
	125	* custom piece of code is copied to replace the problematic BootROM.
	126	*/
	127	int mvebu_setup_boot_addr_wa(unsigned int crypto_eng_target,
	128	unsigned int crypto_eng_attribute,
	129	phys_addr_t resume_addr_reg)
	130	{
	131	void __iomem *sram_virt_base;
	132	u32 code_len = &mvebu_boot_wa_end - &mvebu_boot_wa_start;
	133
	134	mvebu_mbus_del_window(BOOTROM_BASE, BOOTROM_SIZE);
	135	mvebu_mbus_add_window_by_id(crypto_eng_target, crypto_eng_attribute,
	136	SRAM_PHYS_BASE, SZ_64K);
	137
	138	sram_virt_base = ioremap(SRAM_PHYS_BASE, SZ_64K);
	139	if (!sram_virt_base) {
	140	pr_err("Unable to map SRAM to setup the boot address WA\n");
	141	return -ENOMEM;
	142	}
	143
	144	memcpy(sram_virt_base, &mvebu_boot_wa_start, code_len);
	145
	146	/*
	147	* The last word of the code copied in SRAM must contain the
	148	* physical base address of the PMSU register. We
	149	* intentionally store this address in the native endianness
	150	* of the system.
	151	*/
	152	__raw_writel((unsigned long)resume_addr_reg,
	153	sram_virt_base + code_len - 4);
	154
	155	iounmap(sram_virt_base);
	156
	157	return 0;
	158	}
	159
898ef3e9	160	static int __init mvebu_v7_pmsu_init(void)
7444dad2 GC	161	{
7444dad2 GC	162	struct device_node *np;
bd045a1e TP	163	struct resource res;
bd045a1e TP	164	int ret = 0;
7444dad2 GC	165
7444dad2 GC	166	np = of_find_matching_node(NULL, of_pmsu_table);
bd045a1e TP	167	if (!np)
	168	return 0;
	169
	170	pr_info("Initializing Power Management Service Unit\n");
	171
	172	if (of_address_to_resource(np, 0, &res)) {
	173	pr_err("unable to get resource\n");
	174	ret = -ENOENT;
	175	goto out;
7444dad2 GC	176	}
7444dad2 GC	177
0c3acc74 GC	178	if (of_device_is_compatible(np, "marvell,armada-370-xp-pmsu")) {
	179	pr_warn(FW_WARN "deprecated pmsu binding\n");
	180	res.start = res.start - PMSU_BASE_OFFSET;
	181	res.end = res.start + PMSU_REG_SIZE - 1;
	182	}
	183
bd045a1e TP	184	if (!request_mem_region(res.start, resource_size(&res),
	185	np->full_name)) {
	186	pr_err("unable to request region\n");
	187	ret = -EBUSY;
	188	goto out;
	189	}
	190
3b9e4b14 GC	191	pmsu_mp_phys_base = res.start;
3b9e4b14 GC	192
bd045a1e TP	193	pmsu_mp_base = ioremap(res.start, resource_size(&res));
	194	if (!pmsu_mp_base) {
	195	pr_err("unable to map registers\n");
	196	release_mem_region(res.start, resource_size(&res));
	197	ret = -ENOMEM;
	198	goto out;
	199	}
	200
	201	out:
	202	of_node_put(np);
	203	return ret;
7444dad2 GC	204	}
7444dad2 GC	205
898ef3e9	206	static void mvebu_v7_pmsu_enable_l2_powerdown_onidle(void)
f713c7e7 GC	207	{
	208	u32 reg;
	209
	210	if (pmsu_mp_base == NULL)
	211	return;
	212
	213	/* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */
	214	reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	215	reg \|= L2C_NFABRIC_PM_CTL_PWR_DOWN;
	216	writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL);
	217	}
	218
5da964e0 GC	219	enum pmsu_idle_prepare_flags {
	220	PMSU_PREPARE_NORMAL = 0,
	221	PMSU_PREPARE_DEEP_IDLE = BIT(0),
	222	PMSU_PREPARE_SNOOP_DISABLE = BIT(1),
	223	};
c3e04cab GC	224
c3e04cab GC	225	/* No locking is needed because we only access per-CPU registers */
5da964e0	226	static int mvebu_v7_pmsu_idle_prepare(unsigned long flags)
c3e04cab GC	227	{
	228	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	229	u32 reg;
	230
	231	if (pmsu_mp_base == NULL)
bbb92284	232	return -EINVAL;
c3e04cab GC	233
	234	/*
	235	* Adjust the PMSU configuration to wait for WFI signal, enable
	236	* IRQ and FIQ as wakeup events, set wait for snoop queue empty
	237	* indication and mask IRQ and FIQ from CPU
	238	*/
	239	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	240	reg \|= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT \|
	241	PMSU_STATUS_AND_MASK_IRQ_WAKEUP \|
	242	PMSU_STATUS_AND_MASK_FIQ_WAKEUP \|
	243	PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT \|
	244	PMSU_STATUS_AND_MASK_IRQ_MASK \|
	245	PMSU_STATUS_AND_MASK_FIQ_MASK;
	246	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	247
	248	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	249	/* ask HW to power down the L2 Cache if needed */
5da964e0	250	if (flags & PMSU_PREPARE_DEEP_IDLE)
c3e04cab GC	251	reg \|= PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	252
	253	/* request power down */
	254	reg \|= PMSU_CONTROL_AND_CONFIG_PWDDN_REQ;
	255	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	256
5da964e0 GC	257	if (flags & PMSU_PREPARE_SNOOP_DISABLE) {
	258	/* Disable snoop disable by HW - SW is taking care of it */
	259	reg = readl(pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	260	reg \|= PMSU_CPU_POWER_DOWN_DIS_SNP_Q_SKIP;
	261	writel(reg, pmsu_mp_base + PMSU_CPU_POWER_DOWN_CONTROL(hw_cpu));
	262	}
c3e04cab	263
9ce35884 GC	264	return 0;
	265	}
	266
	267	int armada_370_xp_pmsu_idle_enter(unsigned long deepidle)
	268	{
5da964e0	269	unsigned long flags = PMSU_PREPARE_SNOOP_DISABLE;
9ce35884 GC	270	int ret;
9ce35884 GC	271
5da964e0 GC	272	if (deepidle)
	273	flags \|= PMSU_PREPARE_DEEP_IDLE;
	274
	275	ret = mvebu_v7_pmsu_idle_prepare(flags);
9ce35884 GC	276	if (ret)
9ce35884 GC	277	return ret;
c3e04cab GC	278
	279	v7_exit_coherency_flush(all);
	280
	281	ll_disable_coherency();
	282
	283	dsb();
	284
	285	wfi();
	286
	287	/* If we are here, wfi failed. As processors run out of
	288	* coherency for some time, tlbs might be stale, so flush them
	289	*/
	290	local_flush_tlb_all();
	291
	292	ll_enable_coherency();
	293
	294	/* Test the CR_C bit and set it if it was cleared */
	295	asm volatile(
0d461e1b	296	"mrc p15, 0, r0, c1, c0, 0 \n\t"
7ee20ff0	297	"tst r0, %0 \n\t"
0d461e1b GC	298	"orreq r0, r0, #(1 << 2) \n\t"
0d461e1b GC	299	"mcreq p15, 0, r0, c1, c0, 0 \n\t"
c3e04cab	300	"isb "
7ee20ff0	301	: : "Ir" (CR_C) : "r0");
c3e04cab	302
3b9e4b14	303	pr_debug("Failed to suspend the system\n");
c3e04cab GC	304
	305	return 0;
	306	}
	307
	308	static int armada_370_xp_cpu_suspend(unsigned long deepidle)
	309	{
bbb92284	310	return cpu_suspend(deepidle, armada_370_xp_pmsu_idle_enter);
c3e04cab GC	311	}
c3e04cab GC	312
626d6864	313	int armada_38x_do_cpu_suspend(unsigned long deepidle)
e53b1fd4 GC	314	{
	315	unsigned long flags = 0;
	316
	317	if (deepidle)
	318	flags \|= PMSU_PREPARE_DEEP_IDLE;
	319
	320	mvebu_v7_pmsu_idle_prepare(flags);
	321	/*
	322	* Already flushed cache, but do it again as the outer cache
	323	* functions dirty the cache with spinlocks
	324	*/
	325	v7_exit_coherency_flush(louis);
	326
	327	scu_power_mode(mvebu_get_scu_base(), SCU_PM_POWEROFF);
	328
	329	cpu_do_idle();
	330
	331	return 1;
	332	}
	333
	334	static int armada_38x_cpu_suspend(unsigned long deepidle)
	335	{
	336	return cpu_suspend(false, armada_38x_do_cpu_suspend);
	337	}
	338
c3e04cab	339	/* No locking is needed because we only access per-CPU registers */
898ef3e9	340	void mvebu_v7_pmsu_idle_exit(void)
c3e04cab GC	341	{
	342	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
	343	u32 reg;
	344
	345	if (pmsu_mp_base == NULL)
	346	return;
c3e04cab GC	347	/* cancel ask HW to power down the L2 Cache if possible */
	348	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	349	reg &= ~PMSU_CONTROL_AND_CONFIG_L2_PWDDN;
	350	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(hw_cpu));
	351
	352	/* cancel Enable wakeup events and mask interrupts */
	353	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	354	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_WAKEUP \| PMSU_STATUS_AND_MASK_FIQ_WAKEUP);
	355	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	356	reg &= ~PMSU_STATUS_AND_MASK_SNP_Q_EMPTY_WAIT;
	357	reg &= ~(PMSU_STATUS_AND_MASK_IRQ_MASK \| PMSU_STATUS_AND_MASK_FIQ_MASK);
	358	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(hw_cpu));
	359	}
	360
898ef3e9	361	static int mvebu_v7_cpu_pm_notify(struct notifier_block *self,
d163ee16 GC	362	unsigned long action, void *hcpu)
	363	{
	364	if (action == CPU_PM_ENTER) {
	365	unsigned int hw_cpu = cpu_logical_map(smp_processor_id());
752a9937	366	mvebu_pmsu_set_cpu_boot_addr(hw_cpu, mvebu_cpu_resume);
d163ee16	367	} else if (action == CPU_PM_EXIT) {
898ef3e9	368	mvebu_v7_pmsu_idle_exit();
d163ee16 GC	369	}
	370
	371	return NOTIFY_OK;
	372	}
	373
898ef3e9 GC	374	static struct notifier_block mvebu_v7_cpu_pm_notifier = {
898ef3e9 GC	375	.notifier_call = mvebu_v7_cpu_pm_notify,
d163ee16 GC	376	};
d163ee16 GC	377
3b9e4b14 GC	378	static struct platform_device mvebu_v7_cpuidle_device;
3b9e4b14 GC	379
9d2ea95a VD	380	static int broken_idle(struct device_node *np)
	381	{
	382	if (of_property_read_bool(np, "broken-idle")) {
	383	pr_warn("CPU idle is currently broken: disabling\n");
	384	return 1;
	385	}
	386
	387	return 0;
	388	}
	389
3b9e4b14	390	static __init int armada_370_cpuidle_init(void)
8c16babc GC	391	{
8c16babc GC	392	struct device_node *np;
3b9e4b14 GC	393	phys_addr_t redirect_reg;
	394
	395	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
	396	if (!np)
	397	return -ENODEV;
9d2ea95a VD	398
	399	if (broken_idle(np))
	400	goto end;
8c16babc GC	401
8c16babc GC	402	/*
3b9e4b14 GC	403	* On Armada 370, there is "a slow exit process from the deep
	404	* idle state due to heavy L1/L2 cache cleanup operations
	405	* performed by the BootROM software". To avoid this, we
	406	* replace the restart code of the bootrom by a a simple jump
	407	* to the boot address. Then the code located at this boot
	408	* address will take care of the initialization.
8c16babc	409	*/
3b9e4b14 GC	410	redirect_reg = pmsu_mp_phys_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(0);
	411	mvebu_setup_boot_addr_wa(ARMADA_370_CRYPT0_ENG_TARGET,
	412	ARMADA_370_CRYPT0_ENG_ATTR,
	413	redirect_reg);
8c16babc	414
3b9e4b14 GC	415	mvebu_cpu_resume = armada_370_xp_cpu_resume;
	416	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
	417	mvebu_v7_cpuidle_device.name = "cpuidle-armada-370";
	418
9d2ea95a VD	419	end:
9d2ea95a VD	420	of_node_put(np);
3b9e4b14 GC	421	return 0;
	422	}
	423
e53b1fd4 GC	424	static __init int armada_38x_cpuidle_init(void)
	425	{
	426	struct device_node *np;
	427	void __iomem *mpsoc_base;
	428	u32 reg;
	429
a17683ba	430	pr_warn("CPU idle is currently broken on Armada 38x: disabling\n");
548ae94c GC	431	return 0;
548ae94c GC	432
e53b1fd4 GC	433	np = of_find_compatible_node(NULL, NULL,
	434	"marvell,armada-380-coherency-fabric");
	435	if (!np)
	436	return -ENODEV;
9d2ea95a VD	437
	438	if (broken_idle(np))
	439	goto end;
	440
e53b1fd4 GC	441	of_node_put(np);
	442
	443	np = of_find_compatible_node(NULL, NULL,
	444	"marvell,armada-380-mpcore-soc-ctrl");
	445	if (!np)
	446	return -ENODEV;
	447	mpsoc_base = of_iomap(np, 0);
	448	BUG_ON(!mpsoc_base);
e53b1fd4 GC	449
	450	/* Set up reset mask when powering down the cpus */
	451	reg = readl(mpsoc_base + MPCORE_RESET_CTL);
	452	reg \|= MPCORE_RESET_CTL_L2;
	453	reg \|= MPCORE_RESET_CTL_DEBUG;
	454	writel(reg, mpsoc_base + MPCORE_RESET_CTL);
	455	iounmap(mpsoc_base);
	456
	457	/* Set up delay */
	458	reg = readl(pmsu_mp_base + PMSU_POWERDOWN_DELAY);
	459	reg &= ~PMSU_POWERDOWN_DELAY_MASK;
	460	reg \|= PMSU_DFLT_ARMADA38X_DELAY;
	461	reg \|= PMSU_POWERDOWN_DELAY_PMU;
	462	writel(reg, pmsu_mp_base + PMSU_POWERDOWN_DELAY);
	463
	464	mvebu_cpu_resume = armada_38x_cpu_resume;
	465	mvebu_v7_cpuidle_device.dev.platform_data = armada_38x_cpu_suspend;
	466	mvebu_v7_cpuidle_device.name = "cpuidle-armada-38x";
	467
9d2ea95a VD	468	end:
9d2ea95a VD	469	of_node_put(np);
e53b1fd4 GC	470	return 0;
	471	}
	472
3b9e4b14	473	static __init int armada_xp_cpuidle_init(void)
8c16babc GC	474	{
8c16babc GC	475	struct device_node *np;
8c16babc GC	476
	477	np = of_find_compatible_node(NULL, NULL, "marvell,coherency-fabric");
	478	if (!np)
54a4d1b8	479	return -ENODEV;
9d2ea95a VD	480
	481	if (broken_idle(np))
	482	goto end;
8c16babc	483
752a9937	484	mvebu_cpu_resume = armada_370_xp_cpu_resume;
54a4d1b8	485	mvebu_v7_cpuidle_device.dev.platform_data = armada_370_xp_cpu_suspend;
3b9e4b14	486	mvebu_v7_cpuidle_device.name = "cpuidle-armada-xp";
54a4d1b8	487
9d2ea95a VD	488	end:
9d2ea95a VD	489	of_node_put(np);
54a4d1b8 GC	490	return 0;
	491	}
	492
	493	static int __init mvebu_v7_cpu_pm_init(void)
	494	{
	495	struct device_node *np;
	496	int ret;
	497
8c16babc GC	498	np = of_find_matching_node(NULL, of_pmsu_table);
	499	if (!np)
	500	return 0;
	501	of_node_put(np);
	502
548ae94c GC	503	/*
	504	* Currently the CPU idle support for Armada 38x is broken, as
	505	* the CPU hotplug uses some of the CPU idle functions it is
	506	* broken too, so let's disable it
	507	*/
	508	if (of_machine_is_compatible("marvell,armada380")) {
	509	cpu_hotplug_disable();
a17683ba	510	pr_warn("CPU hotplug support is currently broken on Armada 38x: disabling\n");
548ae94c GC	511	}
548ae94c GC	512
54a4d1b8 GC	513	if (of_machine_is_compatible("marvell,armadaxp"))
54a4d1b8 GC	514	ret = armada_xp_cpuidle_init();
3b9e4b14 GC	515	else if (of_machine_is_compatible("marvell,armada370"))
3b9e4b14 GC	516	ret = armada_370_cpuidle_init();
e53b1fd4 GC	517	else if (of_machine_is_compatible("marvell,armada380"))
e53b1fd4 GC	518	ret = armada_38x_cpuidle_init();
54a4d1b8 GC	519	else
	520	return 0;
	521
	522	if (ret)
	523	return ret;
	524
898ef3e9	525	mvebu_v7_pmsu_enable_l2_powerdown_onidle();
548ae94c GC	526	if (mvebu_v7_cpuidle_device.name)
548ae94c GC	527	platform_device_register(&mvebu_v7_cpuidle_device);
898ef3e9	528	cpu_pm_register_notifier(&mvebu_v7_cpu_pm_notifier);
8c16babc GC	529
	530	return 0;
	531	}
	532
898ef3e9 GC	533	arch_initcall(mvebu_v7_cpu_pm_init);
898ef3e9 GC	534	early_initcall(mvebu_v7_pmsu_init);
a509ea84 TP	535
	536	static void mvebu_pmsu_dfs_request_local(void *data)
	537	{
	538	u32 reg;
	539	u32 cpu = smp_processor_id();
	540	unsigned long flags;
	541
	542	local_irq_save(flags);
	543
	544	/* Prepare to enter idle */
	545	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
	546	reg \|= PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT \|
	547	PMSU_STATUS_AND_MASK_IRQ_MASK \|
	548	PMSU_STATUS_AND_MASK_FIQ_MASK;
	549	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
	550
	551	/* Request the DFS transition */
	552	reg = readl(pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
	553	reg \|= PMSU_CONTROL_AND_CONFIG_DFS_REQ;
	554	writel(reg, pmsu_mp_base + PMSU_CONTROL_AND_CONFIG(cpu));
	555
	556	/* The fact of entering idle will trigger the DFS transition */
	557	wfi();
	558
	559	/*
	560	* We're back from idle, the DFS transition has completed,
	561	* clear the idle wait indication.
	562	*/
	563	reg = readl(pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
	564	reg &= ~PMSU_STATUS_AND_MASK_CPU_IDLE_WAIT;
	565	writel(reg, pmsu_mp_base + PMSU_STATUS_AND_MASK(cpu));
	566
	567	local_irq_restore(flags);
	568	}
	569
	570	int mvebu_pmsu_dfs_request(int cpu)
	571	{
	572	unsigned long timeout;
	573	int hwcpu = cpu_logical_map(cpu);
	574	u32 reg;
	575
	576	/* Clear any previous DFS DONE event */
	577	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	578	reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE;
	579	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	580
	581	/* Mask the DFS done interrupt, since we are going to poll */
	582	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	583	reg \|= PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
	584	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	585
	586	/* Trigger the DFS on the appropriate CPU */
	587	smp_call_function_single(cpu, mvebu_pmsu_dfs_request_local,
	588	NULL, false);
	589
	590	/* Poll until the DFS done event is generated */
	591	timeout = jiffies + HZ;
	592	while (time_before(jiffies, timeout)) {
	593	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
	594	if (reg & PMSU_EVENT_STATUS_AND_MASK_DFS_DONE)
	595	break;
	596	udelay(10);
	597	}
	598
599	if (time_after(jiffies, timeout))
600	return -ETIME;
601
602	/* Restore the DFS mask to its original state */
603	reg = readl(pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
604	reg &= ~PMSU_EVENT_STATUS_AND_MASK_DFS_DONE_MASK;
605	writel(reg, pmsu_mp_base + PMSU_EVENT_STATUS_AND_MASK(hwcpu));
606
607	return 0;
608	}