[linux-2.6-block.git] / arch / arm / mach-mvebu / platsmp.c

/*
 * Symmetric Multi Processing (SMP) support for Armada XP
 *
 * Copyright (C) 2012 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Yehuda Yitschak <yehuday@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 *
 * The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
 * This file implements the routines for preparing the SMP infrastructure
 * and waking up the secondary CPUs
 */

#include <linux/init.h>
#include <linux/smp.h>
#include <linux/clk.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/mbus.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include "common.h"
#include "armada-370-xp.h"
#include "pmsu.h"
#include "coherency.h"

#define ARMADA_XP_MAX_CPUS 4

#define AXP_BOOTROM_BASE 0xfff00000
#define AXP_BOOTROM_SIZE 0x100000

static struct clk *boot_cpu_clk;

static struct clk *get_cpu_clk(int cpu)
{
	struct clk *cpu_clk;
	struct device_node *np = of_get_cpu_node(cpu, NULL);

	if (WARN(!np, "missing cpu node\n"))
		return NULL;
	cpu_clk = of_clk_get(np, 0);
	if (WARN_ON(IS_ERR(cpu_clk)))
		return NULL;
	return cpu_clk;
}

static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	int ret, hw_cpu;

	pr_info("Booting CPU %d\n", cpu);

	hw_cpu = cpu_logical_map(cpu);
	mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);

	/*
	 * This is needed to wake up CPUs in the offline state after
	 * using CPU hotplug.
	 */
	arch_send_wakeup_ipi_mask(cpumask_of(cpu));

	/*
	 * This is needed to take secondary CPUs out of reset on the
	 * initial boot.
	 */
	ret = mvebu_cpu_reset_deassert(hw_cpu);
	if (ret) {
		pr_warn("unable to boot CPU: %d\n", ret);
		return ret;
	}

	return 0;
}

/*
 * When a CPU is brought back online, either through CPU hotplug, or
 * because of the boot of a kexec'ed kernel, the PMSU configuration
 * for this CPU might be in the deep idle state, preventing this CPU
 * from receiving interrupts. Here, we therefore take out the current
 * CPU from this state, which was entered by armada_xp_cpu_die()
 * below.
 */
static void armada_xp_secondary_init(unsigned int cpu)
{
	mvebu_v7_pmsu_idle_exit();
}

static void __init armada_xp_smp_init_cpus(void)
{
	unsigned int ncores = num_possible_cpus();

	if (ncores == 0 || ncores > ARMADA_XP_MAX_CPUS)
		panic("Invalid number of CPUs in DT\n");
}

static int armada_xp_sync_secondary_clk(unsigned int cpu)
{
	struct clk *cpu_clk = get_cpu_clk(cpu);

	if (!cpu_clk || !boot_cpu_clk)
		return 0;

	clk_prepare_enable(cpu_clk);
	clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk));

	return 0;
}

static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
{
	struct device_node *node;
	struct resource res;
	int err;

	flush_cache_all();
	set_cpu_coherent();

	boot_cpu_clk = get_cpu_clk(smp_processor_id());
	if (boot_cpu_clk) {
		clk_prepare_enable(boot_cpu_clk);
		cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS,
					  "arm/mvebu/sync_clocks:online",
					  armada_xp_sync_secondary_clk, NULL);
	}

	/*
	 * In order to boot the secondary CPUs we need to ensure
	 * the bootROM is mapped at the correct address.
	 */
	node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
	if (!node)
		panic("Cannot find 'marvell,bootrom' compatible node");

	err = of_address_to_resource(node, 0, &res);
	of_node_put(node);
	if (err < 0)
		panic("Cannot get 'bootrom' node address");

	if (res.start != AXP_BOOTROM_BASE ||
	    resource_size(&res) != AXP_BOOTROM_SIZE)
		panic("The address for the BootROM is incorrect");
}

#ifdef CONFIG_HOTPLUG_CPU
static void armada_xp_cpu_die(unsigned int cpu)
{
	/*
	 * CPU hotplug is implemented by putting offline CPUs into the
	 * deep idle sleep state.
	 */
	armada_370_xp_pmsu_idle_enter(true);
}

/*
 * We need a dummy function, so that platform_can_cpu_hotplug() knows
 * we support CPU hotplug. However, the function does not need to do
 * anything, because CPUs going offline can enter the deep idle state
 * by themselves, without any help from a still alive CPU.
 */
static int armada_xp_cpu_kill(unsigned int cpu)
{
	return 1;
}
#endif

const struct smp_operations armada_xp_smp_ops __initconst = {
	.smp_init_cpus		= armada_xp_smp_init_cpus,
	.smp_prepare_cpus	= armada_xp_smp_prepare_cpus,
	.smp_boot_secondary	= armada_xp_boot_secondary,
	.smp_secondary_init     = armada_xp_secondary_init,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= armada_xp_cpu_die,
	.cpu_kill               = armada_xp_cpu_kill,
#endif
};

CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
		      &armada_xp_smp_ops);

#define MV98DX3236_CPU_RESUME_CTRL_REG 0x08
#define MV98DX3236_CPU_RESUME_ADDR_REG 0x04

static const struct of_device_id of_mv98dx3236_resume_table[] = {
	{
		.compatible = "marvell,98dx3336-resume-ctrl",
	},
	{ /* end of list */ },
};

static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
{
	struct device_node *np;
	void __iomem *base;
	WARN_ON(hw_cpu != 1);

	np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
	if (!np)
		return -ENODEV;

	base = of_io_request_and_map(np, 0, of_node_full_name(np));
	of_node_put(np);
	if (IS_ERR(base))
		return PTR_ERR(base);

	writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
	writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);

	iounmap(base);

	return 0;
}

static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	int ret, hw_cpu;

	hw_cpu = cpu_logical_map(cpu);
	mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
					    armada_xp_secondary_startup);

	/*
	 * This is needed to wake up CPUs in the offline state after
	 * using CPU hotplug.
	 */
	arch_send_wakeup_ipi_mask(cpumask_of(cpu));

	/*
	 * This is needed to take secondary CPUs out of reset on the
	 * initial boot.
	 */
	ret = mvebu_cpu_reset_deassert(hw_cpu);
	if (ret) {
		pr_warn("unable to boot CPU: %d\n", ret);
		return ret;
	}

	return 0;
}

static const struct smp_operations mv98dx3236_smp_ops __initconst = {
	.smp_init_cpus		= armada_xp_smp_init_cpus,
	.smp_prepare_cpus	= armada_xp_smp_prepare_cpus,
	.smp_boot_secondary	= mv98dx3236_boot_secondary,
	.smp_secondary_init     = armada_xp_secondary_init,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_die		= armada_xp_cpu_die,
	.cpu_kill               = armada_xp_cpu_kill,
#endif
};

CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
		      &mv98dx3236_smp_ops);
Commit	Line	Data
45f5984a GC	1	/*
	2	* Symmetric Multi Processing (SMP) support for Armada XP
	3	*
	4	* Copyright (C) 2012 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Yehuda Yitschak <yehuday@marvell.com>
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	9	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	10	*
	11	* This file is licensed under the terms of the GNU General Public
	12	* License version 2. This program is licensed "as is" without any
	13	* warranty of any kind, whether express or implied.
	14	*
	15	* The Armada XP SoC has 4 ARMv7 PJ4B CPUs running in full HW coherency
	16	* This file implements the routines for preparing the SMP infrastructure
	17	* and waking up the secondary CPUs
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/smp.h>
	22	#include <linux/clk.h>
	23	#include <linux/of.h>
994c8c94	24	#include <linux/of_address.h>
87e1bed4	25	#include <linux/mbus.h>
45f5984a GC	26	#include <asm/cacheflush.h>
	27	#include <asm/smp_plat.h>
	28	#include "common.h"
	29	#include "armada-370-xp.h"
	30	#include "pmsu.h"
	31	#include "coherency.h"
	32
316fbbc4 GC	33	#define ARMADA_XP_MAX_CPUS 4
316fbbc4 GC	34
994c8c94 EG	35	#define AXP_BOOTROM_BASE 0xfff00000
	36	#define AXP_BOOTROM_SIZE 0x100000
	37
77bc8c28 LS	38	static struct clk *boot_cpu_clk;
77bc8c28 LS	39
b9b1de0f	40	static struct clk *get_cpu_clk(int cpu)
f6cec7cd SK	41	{
	42	struct clk *cpu_clk;
	43	struct device_node *np = of_get_cpu_node(cpu, NULL);
	44
	45	if (WARN(!np, "missing cpu node\n"))
	46	return NULL;
	47	cpu_clk = of_clk_get(np, 0);
	48	if (WARN_ON(IS_ERR(cpu_clk)))
	49	return NULL;
	50	return cpu_clk;
	51	}
	52
8bd26e3a	53	static int armada_xp_boot_secondary(unsigned int cpu, struct task_struct *idle)
45f5984a	54	{
05ad6906 TP	55	int ret, hw_cpu;
05ad6906 TP	56
45f5984a GC	57	pr_info("Booting CPU %d\n", cpu);
45f5984a GC	58
05ad6906 TP	59	hw_cpu = cpu_logical_map(cpu);
05ad6906 TP	60	mvebu_pmsu_set_cpu_boot_addr(hw_cpu, armada_xp_secondary_startup);
26337779 TP	61
	62	/*
	63	* This is needed to wake up CPUs in the offline state after
	64	* using CPU hotplug.
	65	*/
	66	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	67
	68	/*
	69	* This is needed to take secondary CPUs out of reset on the
	70	* initial boot.
	71	*/
05ad6906 TP	72	ret = mvebu_cpu_reset_deassert(hw_cpu);
	73	if (ret) {
	74	pr_warn("unable to boot CPU: %d\n", ret);
	75	return ret;
	76	}
45f5984a GC	77
	78	return 0;
	79	}
	80
26337779 TP	81	/*
	82	* When a CPU is brought back online, either through CPU hotplug, or
	83	* because of the boot of a kexec'ed kernel, the PMSU configuration
	84	* for this CPU might be in the deep idle state, preventing this CPU
	85	* from receiving interrupts. Here, we therefore take out the current
	86	* CPU from this state, which was entered by armada_xp_cpu_die()
	87	* below.
	88	*/
	89	static void armada_xp_secondary_init(unsigned int cpu)
	90	{
898ef3e9	91	mvebu_v7_pmsu_idle_exit();
26337779 TP	92	}
26337779 TP	93
45f5984a GC	94	static void __init armada_xp_smp_init_cpus(void)
45f5984a GC	95	{
a7160b7e	96	unsigned int ncores = num_possible_cpus();
b21dcafe	97
b21dcafe TP	98	if (ncores == 0 \|\| ncores > ARMADA_XP_MAX_CPUS)
b21dcafe TP	99	panic("Invalid number of CPUs in DT\n");
45f5984a GC	100	}
45f5984a GC	101
77bc8c28 LS	102	static int armada_xp_sync_secondary_clk(unsigned int cpu)
	103	{
	104	struct clk *cpu_clk = get_cpu_clk(cpu);
	105
	106	if (!cpu_clk \|\| !boot_cpu_clk)
	107	return 0;
	108
	109	clk_prepare_enable(cpu_clk);
	110	clk_set_rate(cpu_clk, clk_get_rate(boot_cpu_clk));
	111
	112	return 0;
	113	}
	114
b12634e3	115	static void __init armada_xp_smp_prepare_cpus(unsigned int max_cpus)
45f5984a	116	{
994c8c94 EG	117	struct device_node *node;
	118	struct resource res;
	119	int err;
	120
45f5984a	121	flush_cache_all();
952f4ca7	122	set_cpu_coherent();
994c8c94	123
77bc8c28 LS	124	boot_cpu_clk = get_cpu_clk(smp_processor_id());
	125	if (boot_cpu_clk) {
	126	clk_prepare_enable(boot_cpu_clk);
	127	cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_SYNC_CLOCKS,
	128	"arm/mvebu/sync_clocks:online",
	129	armada_xp_sync_secondary_clk, NULL);
	130	}
	131
994c8c94 EG	132	/*
	133	* In order to boot the secondary CPUs we need to ensure
	134	* the bootROM is mapped at the correct address.
	135	*/
	136	node = of_find_compatible_node(NULL, NULL, "marvell,bootrom");
	137	if (!node)
	138	panic("Cannot find 'marvell,bootrom' compatible node");
	139
	140	err = of_address_to_resource(node, 0, &res);
7d8f9ac1	141	of_node_put(node);
994c8c94 EG	142	if (err < 0)
	143	panic("Cannot get 'bootrom' node address");
	144
	145	if (res.start != AXP_BOOTROM_BASE \|\|
	146	resource_size(&res) != AXP_BOOTROM_SIZE)
	147	panic("The address for the BootROM is incorrect");
45f5984a GC	148	}
45f5984a GC	149
26337779 TP	150	#ifdef CONFIG_HOTPLUG_CPU
	151	static void armada_xp_cpu_die(unsigned int cpu)
	152	{
	153	/*
	154	* CPU hotplug is implemented by putting offline CPUs into the
	155	* deep idle sleep state.
	156	*/
	157	armada_370_xp_pmsu_idle_enter(true);
	158	}
	159
	160	/*
	161	* We need a dummy function, so that platform_can_cpu_hotplug() knows
	162	* we support CPU hotplug. However, the function does not need to do
	163	* anything, because CPUs going offline can enter the deep idle state
	164	* by themselves, without any help from a still alive CPU.
	165	*/
	166	static int armada_xp_cpu_kill(unsigned int cpu)
	167	{
	168	return 1;
	169	}
	170	#endif
	171
75305275	172	const struct smp_operations armada_xp_smp_ops __initconst = {
45f5984a GC	173	.smp_init_cpus = armada_xp_smp_init_cpus,
45f5984a GC	174	.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
45f5984a	175	.smp_boot_secondary = armada_xp_boot_secondary,
26337779	176	.smp_secondary_init = armada_xp_secondary_init,
45f5984a GC	177	#ifdef CONFIG_HOTPLUG_CPU
45f5984a GC	178	.cpu_die = armada_xp_cpu_die,
26337779	179	.cpu_kill = armada_xp_cpu_kill,
45f5984a GC	180	#endif
45f5984a GC	181	};
2c9b2240 TP	182
	183	CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
	184	&armada_xp_smp_ops);
db889778 CP	185
	186	#define MV98DX3236_CPU_RESUME_CTRL_REG 0x08
	187	#define MV98DX3236_CPU_RESUME_ADDR_REG 0x04
	188
	189	static const struct of_device_id of_mv98dx3236_resume_table[] = {
	190	{
	191	.compatible = "marvell,98dx3336-resume-ctrl",
	192	},
	193	{ /* end of list */ },
	194	};
	195
	196	static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
	197	{
	198	struct device_node *np;
	199	void __iomem *base;
	200	WARN_ON(hw_cpu != 1);
	201
	202	np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
	203	if (!np)
	204	return -ENODEV;
	205
	206	base = of_io_request_and_map(np, 0, of_node_full_name(np));
	207	of_node_put(np);
	208	if (IS_ERR(base))
	209	return PTR_ERR(base);
	210
	211	writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
76127d6f	212	writel(__pa_symbol(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
db889778 CP	213
	214	iounmap(base);
	215
	216	return 0;
	217	}
	218
	219	static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
	220	{
	221	int ret, hw_cpu;
	222
	223	hw_cpu = cpu_logical_map(cpu);
db889778 CP	224	mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
	225	armada_xp_secondary_startup);
	226
	227	/*
	228	* This is needed to wake up CPUs in the offline state after
	229	* using CPU hotplug.
	230	*/
	231	arch_send_wakeup_ipi_mask(cpumask_of(cpu));
	232
	233	/*
	234	* This is needed to take secondary CPUs out of reset on the
	235	* initial boot.
	236	*/
	237	ret = mvebu_cpu_reset_deassert(hw_cpu);
	238	if (ret) {
	239	pr_warn("unable to boot CPU: %d\n", ret);
	240	return ret;
	241	}
	242
	243	return 0;
	244	}
	245
	246	static const struct smp_operations mv98dx3236_smp_ops __initconst = {
	247	.smp_init_cpus = armada_xp_smp_init_cpus,
	248	.smp_prepare_cpus = armada_xp_smp_prepare_cpus,
	249	.smp_boot_secondary = mv98dx3236_boot_secondary,
	250	.smp_secondary_init = armada_xp_secondary_init,
	251	#ifdef CONFIG_HOTPLUG_CPU
	252	.cpu_die = armada_xp_cpu_die,
	253	.cpu_kill = armada_xp_cpu_kill,
	254	#endif
	255	};
	256
	257	CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
	258	&mv98dx3236_smp_ops);