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0fdebc5e | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
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2 | /* |
3 | * SMP support: Entry point for secondary CPUs | |
4 | * | |
5 | * Copyright (C) 2012 Marvell | |
6 | * | |
7 | * Yehuda Yitschak <yehuday@marvell.com> | |
8 | * Gregory CLEMENT <gregory.clement@free-electrons.com> | |
9 | * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> | |
10 | * | |
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11 | * This file implements the assembly entry point for secondary CPUs in |
12 | * an SMP kernel. The only thing we need to do is to add the CPU to | |
13 | * the coherency fabric by writing to 2 registers. Currently the base | |
14 | * register addresses are hard coded due to the early initialisation | |
15 | * problems. | |
16 | */ | |
17 | ||
18 | #include <linux/linkage.h> | |
19 | #include <linux/init.h> | |
20 | ||
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21 | #include <asm/assembler.h> |
22 | ||
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23 | /* |
24 | * Armada XP specific entry point for secondary CPUs. | |
25 | * We add the CPU to the coherency fabric and then jump to secondary | |
26 | * startup | |
27 | */ | |
28 | ENTRY(armada_xp_secondary_startup) | |
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29 | ARM_BE8(setend be ) @ go BE8 if entered LE |
30 | ||
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31 | bl ll_add_cpu_to_smp_group |
32 | ||
33 | bl ll_enable_coherency | |
34 | ||
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35 | b secondary_startup |
36 | ||
37 | ENDPROC(armada_xp_secondary_startup) |